JPH0863982A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE: To shorten a time required for verifying and to prevent over erasing and occurring of over program by erasing two monitoring cells having required structure, comparing a threshold value of the monitoring cell with the prescribed value, and controlling erasing of a main body cell in accordance with the compared result. CONSTITUTION: Monitoring cells B, C having cell constitution equivalent to a main body cell A of a memory cell array 20 are respectively erased and over erased. After that, threshold voltage of the cells B, C are compared with the corresponding prescribed values respectively by a comparator circuit 17, and erasing of plural cells of the array 20 is controlled through a control circuit 13 in accordance with the compared result. Thereby, operation for verifying all memory cells one by one is not required, a time required for verifying is shortened, and over erasing and occurrence of over program are prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically writable and electrically erasable nonvolatile semiconductor memory device or an electrically writable nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art A conventional nonvolatile semiconductor memory device will be described. FIG. 6 shows an example of conventional batch erase type NO.
The structure of an R-type E ² PROM is shown.

A memory cell array 20 is provided in which memory cells each having a transistor having a floating gate are arranged in a matrix. Around the memory cell array 20, a column decoder 19 that selects the bit line BL and a row decoder 2 that selects the word line WL.
1 and a sense amplifier 1 for reading data from a memory cell
8 are provided. The program voltage circuit 12 applies a program voltage to the bit line BL when writing to the memory cell, and the erase voltage circuit 11 applies a voltage for erasing the written data to the ground line of the memory cell. It is a thing. The data buffer 14 amplifies data when inputting / outputting data between the sense amplifier 18 and the outside. The verify circuit 15 reads the data written in the memory cell array and performs verification.
The address buffer 32 amplifies an address signal input from the outside and gives it to the address latch circuit 31, and the address latch circuit 31 latches this address signal and gives it to the column decoder 19 and the row decoder 21. The control circuit 13 controls the operations of the erase voltage circuit 11, the program voltage circuit 12, the data buffer 14, the verify circuit 15, and the address latch circuit 31, based on a control signal given from the outside.

Next, the write and erase operations in such a conventional device will be described.

First, the program voltage of, for example, 12 V output from the program voltage circuit 12 is applied to the control gate 45 shown in FIG. 8B. Further, 8 V is applied to the drain region 42 and 0 V is applied to the source region 41. As a result, electrons are injected into the floating gate to increase the threshold voltage of the memory cell, and the data writing is completed.

Thereafter, the erase operation is performed in the procedure shown in FIG. As in step 101, the address is set to the head address. The erase voltage VSSEA is generated from the erase voltage circuit 11. In the vertical cross section of the memory cell shown in FIG. 8A, the erase voltage V is applied to the source region 41.
SSEA is applied for a certain time TEW, the word line is held at 0 V, and the bit line is held in a floating state, so that the electrons in the floating gate 43 are removed toward the semiconductor substrate 40. In this way, the data written in all the memory cells are collectively erased (step 103).

After this, a verify command is input (step 104). After a certain recovery time Ter has passed since the erase operation (step 105), the verify circuit 15 checks whether or not the threshold voltage of the memory cell is a predetermined value. The result of verification is pass, and while the final address is not reached (step 10
6) advances the address by one address (step 1
08) Repeat verification.

When the result of the verify is fail, the address latch circuit 31 latches the address at that time, and the verify is interrupted. Then, batch erasing is performed again (step 103), and verification is performed from the failed address. Such an operation is repeated until the final address.

Here, the time TB required for verification is
It looks like the following equation (1). TB = {capacity + (number of erasures-1)} * Ter (1) where "capacity" is the R to be erased
The capacity is OM.

For example, NOR type E ² P of 1 to 4 MByte
In the ROM, the recovery time Ter is set to 6 μs. If the erase count is 100, the time T required for verification is
B is about 800 ms for 1M and about 3200 ms for 4M
Becomes

Next, the phenomenon of over-erasing that has occurred in the conventional device will be described. The cell shown in FIG. 8A is in a normal erased state and corresponds to logic "1" data. The memory cell shown in FIG. 8B is a cell in the written state and corresponds to logic "0" data.

Further, FIG. 9 shows the threshold distribution of the memory cells in the normal erased state in the hatched area 51, and the threshold distribution of the memory cells in the written state in the area 5.
It is shown in FIG. When, for example, 5 V is applied as the Vcc voltage to the control gate of the cell, the written cell remains in the off state and no current flows. A cell in a normal erased state is turned on and a current flows. In addition, even if 0V is applied to the control gate of the cell in the erased state,
It is turned off.

FIG. 12 shows a layout in which memory cells are arranged in a matrix. Bit lines BL1, BL2
, And word lines WL1, WL2, ... Are connected to memory cells A1, A2 ,. When reading the data of the memory cell A1, the control gate of the cell A1, that is, the word line WL1 is set to 0V. No current flows in cells other than the cell A1. In the cell A1, when the data is logic "1", a current flows and the potential of the bit line BL1 drops. In the case of logic "0" data, no current flows in the cell A and the potential of the bit line BL1 does not drop. In this way, it is determined whether the logical data is "1" or "0" depending on whether or not the potential of the bit line BL1 connected to the memory cell A1 to be read drops.

FIG. 10 shows the structure of a cell which has been overerased. The floating gate 43 is in a positively charged state as opposed to the state in which data is written and electrons are injected as shown in FIG. 8B. The distribution of the threshold voltage Vth at this time is shown in a region 53 of FIG. In such an over-erased cell, a current flows even if a potential of 0V is applied to the word line WL1. Therefore, the over-erased cell A
Even when reading cells A2, A3, ... Of other logic "0" data connected to the bit line BL1 to which 1 is connected, the potential of the bit line BL1 drops and it is erroneous that the data is logic "1" data. Will be read out. Such a problem of over-erasure has occurred in the conventional device.

Next, the operation of electrically writing data in the E ² PROM will be described. As an example, FIG. 13 shows the configuration of a NAND type E ² PROM which simultaneously writes a plurality of data. This device includes a register having a function as a static sense amplifier / latch circuit inside the device. Write and read operations are performed by transferring data between the register and the memory cell array, for example, with a storage capacity of 512 bytes of the register as one unit.

Memory cell A11 in the main body cell array 67
And page A consisting of A12 and A12 is to be written. Select line SL1 to high level, select line SL
2 is set to the low level, the cells A11 and A12 are connected to the bit lines BL1 and BL2 and separated from the ground potential terminal.

The procedure for writing is shown in the flowchart of FIG. First, an address is set at the head address in the page to be written (step 401).

0V is applied to the bit lines BL1 and BL2, and the program voltage generated by the internal voltage generating circuit 61 is applied to the word line WL1 for a predetermined time TPW. When writing is performed in this manner, the threshold voltage V of the cells A1 and A2 is
th becomes high (step 402).

After that, a verify operation for checking whether or not the threshold voltages of the cells A1 and A2 are a predetermined value is performed using the verify circuit 64 (step 403). If the result of the verify is fail, the verify operation is interrupted, the address is returned to the head address of the page, and the write is performed again. Then, verify it (step 4
03), the verification result is repeated until OK is obtained up to the final address (steps 404 and 405).

If there are variations in writing characteristics within the same page, the following problems occur. That is, even if the fast-writing cell becomes OK by the verification, the writing is repeated simultaneously for both cells until the other slow-writing cell becomes OK. For this reason, the problem of over-programming occurs in a cell in which writing is fast.

Next, the problem of this overprogram will be described. 15A shows the structure of the memory cell in the erased state, and FIG. 15B shows the structure of the memory cell in the normally written state. In FIG. 16, the threshold distribution of cells in the erased state is shown as a region 81, and the threshold distribution of cells in a normally written state is shown as a region 82.

Cell control gate (word line W
When, for example, 5 V is applied as the power supply voltage Vcc to L), the erased cells are turned on and the normally written cells are turned off. Further, when the power supply voltage Vcc is applied to the control gate of the normally written cell, it turns on.

FIG. 17 shows a 4M NAND type FLASH.
The main cell array of E ² PROM is shown. 0V is applied to the control gate (word line WL1) of the cell A1, and the power supply voltage Vcc is applied to the other control gates. At this time, when the cell A1 has the logic "1" data, it is turned on, and all the other cells are turned on. As a result, a cell current flows, the precharged bit line BL1 is discharged, and the potential drops. On the contrary, when the data in the cell A1 is logic "0", it is turned off, so that the potential of the bit line BL1 does not drop. Thus, this NAND type FLAS
Also in the HE ² PROM, it is determined whether the data is logic "1" or "0" depending on whether or not the potential of the bit line BL drops.

Here, FIG. 18 shows the distribution of the threshold voltage Vth of the overprogrammed cells. The over-programmed cell remains off even if the power supply voltage Vcc is applied to the word line WL. As a result, when reading another cell of logic "1" connected to the bit line BL to which the over-programmed cell is connected, the potential of the bit line BL does not drop and is therefore mistakenly called data of logic "0". Will be read as The problem of such over-program has occurred in the conventional device.

[0025]

As described above, the conventional device has some problems. First, in an electrically writable and electrically erasable non-volatile semiconductor memory device, after collectively erasing, all memory cells are verified one by one, and there is an unerased memory cell. The complicated work of performing batch erasure again was necessary. For this reason, a lot of time is spent, and this time increases as the memory capacity increases.

Secondly, the conventional device has a problem that the erase operation cannot be stopped before the over-erase occurs and the characteristics of the memory cell are deteriorated.

Third, in the electrically writable non-volatile semiconductor memory device, when simultaneous writing is performed, if there are fast writing cells and slow writing cells among the simultaneously written cells, the cells are changed to slow writing cells. By repeating the programming at the same time, there has been a problem of over-programming in a cell with fast writing.

The present invention has been made in view of the above circumstances, and in a nonvolatile semiconductor memory device capable of electrically writing and erasing, the verifying step after erasing is simplified, and overerase is prevented. An object of the present invention is to provide a semiconductor memory device capable of preventing the occurrence.

Further, according to the present invention, in the electrically writable non-volatile semiconductor memory device, when writing is performed collectively to a plurality of cells, 1 is applied to all the written cells.
An object of the present invention is to provide a semiconductor memory device capable of simplifying a complicated process of verifying each of them and preventing occurrence of over-programming.

[0030]

A nonvolatile semiconductor memory device according to the present invention has a memory cell array in which a plurality of memory cells are arranged, erases a plurality of bits of the memory cell array at the same time, and erases the memory. A non-volatile semiconductor memory device capable of electrically writing and erasing in which a cell threshold value is required to be within a predetermined range, the monitoring cell having a cell structure equivalent to the memory cell, and the monitoring cell. After erasing the cell,
An erase control circuit for comparing the threshold value of the monitoring cell with a predetermined value and controlling the operation of erasing the memory cell according to the comparison result is provided.

Alternatively, the non-volatile semiconductor memory device of the present invention has a memory cell array in which a plurality of memory cells are arranged, and a plurality of bits of the memory cell array are simultaneously written, and the threshold value of the memory cell after writing is An electrically writable non-volatile semiconductor memory device that needs to be within a predetermined range, and a monitoring cell having a cell structure equivalent to the memory cell,
After writing to the monitoring cell, a threshold value of the monitoring cell is compared with a predetermined value, and a write control circuit for controlling the operation of writing to the memory cell according to the comparison result is provided.

[0032]

In the electrically writable and erasable non-volatile semiconductor memory device, after the monitoring cell is erased, the threshold value of the monitoring cell is compared with a predetermined value to control the operation of erasing the memory cell. , The work of verifying all the memory cells one by one after erasing the memory cells is unnecessary, and over-erasure is prevented.

In the electrically writable nonvolatile semiconductor memory device, after writing to the monitoring cell, the threshold value of the monitoring cell is compared with a predetermined value to control the operation of writing to the memory cell, thereby controlling the memory cell. After writing data into the memory cells, the operation of verifying all the memory cells one by one is not necessary, and over-programming is prevented.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, the semiconductor memory device according to the first embodiment is a non-volatile semiconductor memory device capable of electrically writing and erasing. This device further includes two monitoring cells B and C in addition to the memory cell A on the main body side in the memory cell array 20 as shown in FIG. The monitoring cells B and C have a structure electrically equivalent to the memory cell A on the main body side.

The step-down circuit 22 generates the erase voltage VSSEB (= VSSEA-α) by reducing the erase voltage VSSEA generated by the erase voltage circuit 11 to a predetermined level α (where α> 0V),
It is applied to the source region of the monitoring cell B. The booster circuit 23 generates an erase voltage VSSEC (= VSSEA + β) obtained by boosting the erase voltage VSSEA output from the erase voltage generating circuit 11 to a predetermined level β (β> 0V), and applies it to the source region of the monitoring cell C. Is. The monitoring cell B is equivalent to a memory cell that is hard to erase among the memory cells on the main body side, and the monitoring cell C is equivalent to a memory cell that is easily erased.

The comparison circuit 17 is connected to the drain regions of the monitoring cells B and C, respectively. The comparison circuit 17 charges the signal line connected to each drain region. When a voltage higher than each threshold voltage is applied to the gates of the monitoring cells B and C, the monitoring cells B and C become conductive, and the charged signal lines are discharged and the potential drops. From this phenomenon, the comparison circuit 17 detects conduction or non-conduction of the monitoring cells B and C. The same elements as those shown in FIG. 6 are denoted by the same reference numerals and the description thereof will be omitted.

The erase operation in the device of this embodiment having such a configuration will be described below.

The program voltage is output from the program voltage circuit 12 for a certain period of time, electrons are injected into the floating gate, the threshold voltage of the memory cell is increased, and data is written.

After that, the erase operation is performed in the procedure shown in the flow chart of FIG. First, step 20
The erase command is input as in 1. Then, batch erasing is performed as in step 202. Erase voltage circuit 1
The erase voltage VSSEA is generated from 1 and is applied to the source regions of all the memory cells A on the main body side for a fixed time TEW.

At the same time, the erase voltage VSSEA is stepped down by the voltage α by the step-down circuit 22, and the erase voltage VSSEB is output and applied to the ground terminal of the monitoring cell B. Further, the erase voltage VSSEA is boosted by the voltage β by the booster circuit 23, and the erase voltage VSSEC is output and applied to the ground terminal of the monitoring cell C.

After this, a verify command is input as in step 203. After a certain recovery time has elapsed as in step 204, it is checked in step 205 whether the verification result is OK. That is,
The data verify circuit 15 and the comparison circuit 17 check whether or not the threshold voltages of the monitoring cells B and C have a predetermined value when the data is erased.

Specifically, for the monitoring cell B, verification is performed at a predetermined value, for example, 3.5V,
When the cell current is turned on and the cell current flows, it corresponds to the logic "0" data and it is determined that the erasure is insufficient. Conversely, monitoring cell B
When is turned on and a current flows, it corresponds to logic "1" data and is in an erased state.

For the monitoring cell C, verification is performed at a predetermined value, for example, 0 V, and if it is kept in the off state, it can be determined that overerasing has not occurred. On the contrary, when it is turned on and the cell current flows, it is found that the cell is in the over-erased state.

The timing for stopping the erase operation is
It is assumed that the monitoring cell B is in the erased state and the monitoring cell C is over-erased.

The operation of stopping the erasing may be performed as follows, for example. The verifying circuit 15 verifies the monitoring cells B and C, and the comparing circuit 17 compares the data and outputs the data to the outside from an external input / output terminal (not shown). Then, based on this data, it is externally determined whether to continue or stop the erase operation. Alternatively, the comparison circuit 17 may perform an operation of determining whether to compare and stop without outputting the signal to the outside, and give the control circuit 13 a signal instructing to continue or end the erase operation.

The first embodiment has such memory cells B and C for monitoring, and a voltage lower than the erase voltage VSSEA applied to the memory cell A on the main body side and a voltage higher than the erase voltage VSSEA are applied at the time of batch erase. Apply. In this way,
By equivalently creating memory cells that are not erased unless a high voltage is applied and memory cells that are erased at a low voltage, the degree of erase and the occurrence of over-erase are monitored, and all memory cells on the main body side are erased. It eliminates the need to inspect quantities one by one. This reduces inspection time,
Also, over-erasure is prevented.

Next, a second embodiment of the present invention will be described with reference to the drawings. The second embodiment is an electrically writable non-volatile semiconductor memory device having a structure as shown in FIG.

Compared with the conventional apparatus shown in FIG. 13 described above, the following points are different. Memory cell array 6 on the main unit side
7 monitoring cells B and C having a configuration electrically equivalent to that of memory cell 7. A write voltage VPPB (= VPPA −) different from the write voltage VPPA generated by the internal voltage generation circuit 94 applied to the memory cells on the main body side is applied to the two monitoring cells B and C, respectively.
α) and VPPC (= VPPA + β) are applied. The write voltages VPPB and VPPC are generated by internal voltage generating circuits 92 and 93, respectively.

Then, the respective write voltages VPPB and VPPC are applied to the gates of the monitoring cells B and C, respectively. As a result, the monitoring cell B, which is a slow-writing memory cell, and the monitoring cell C, which is a fast-writing memory cell, are created equivalently.

FIG. 5A shows the structure when writing is performed to the memory cell on the main body side. A predetermined amount of electrons are injected into the floating gate 43.
On the other hand, the monitoring cell B corresponds to a cell in which writing is slow and has a structure as shown in FIG. That is, the amount of electrons injected into the floating gate 43 is smaller than that of the memory cell on the main body side. The monitoring cell C corresponds to a cell in which writing is fast and has a large amount of injected electrons.

The comparison circuit 91 uses this monitoring cell B.
And the drains of C and write voltage VPP
It is determined whether or not B and VPPC have been applied to make them conductive. The same elements as those shown in FIG. 13 are denoted by the same reference numerals and the description thereof will be omitted.

FIG. 4 shows the procedure of the write operation in this embodiment. Under the control of the control circuit 62, the write voltage VPP is applied to the monitoring cells B and C for a certain time.
B and VPPC are simultaneously applied to perform writing (step 301).

Next, as step 302, verification is performed on the monitoring cells B and C. As described above, the comparison circuit 91 determines whether or not cell currents flow through the monitoring cells B and C, respectively.

For the monitoring cell B, verification is performed at a preset predetermined value, for example, 0.5V,
When it is turned on and a cell current flows, it corresponds to logic "1" data, and it is determined that writing is insufficient. On the contrary, when the cell current flows through the monitoring cell B, it is determined that the writing is completed.

The monitoring cell C is verified with a predetermined value of, for example, 4 V, and if the cell current flows, it is determined that it is not in the over-programmed state. On the contrary, when the cell current does not flow, it is determined that over-programming has already been performed.

The specific timing at which writing should be stopped is immediately after the monitoring cell B is in the written state and the monitoring cell C is in the over-programmed state.

The structure for stopping writing may be, for example, as follows. The verifying circuit 64 verifies the monitoring cells B and C, and the comparing circuit 9
The determination result is output to the outside, and whether the writing is continued or stopped is controlled by means provided outside.
Alternatively, the control circuit 62 is instructed to continue or stop writing based on the result determined inside the comparison circuit 91.

According to the second embodiment, it is possible to eliminate the need for verifying all the target memory cells when writing the memory cells on the main body side. By using the monitoring cells B and C equivalently corresponding to the slow-writing memory cell and the fast-writing memory cell, the verify time is significantly shortened as compared with the conventional case. Also, in the past, the verify time also increased with the increase in memory capacity.
According to this embodiment, the size can be shortened regardless of the memory capacity. For example, if the erase recovery time Ter is 6 μs and the number of times of erasing is 100, the verification can be performed in about 0.6 μs regardless of the memory capacity.

Further, according to the present embodiment, the upper and lower limits of the write amount can be controlled by using the two monitoring cells B and C, so that the problems of insufficient writing and overwriting can be solved.

In this embodiment, since it is sufficient to add two monitoring cells to the memory cell array on the main body side, there is no fear that the chip size will increase.

The above-mentioned embodiments are merely examples and do not limit the present invention. For example, each of the embodiments has two monitoring cells. However, it is sufficient that at least one monitoring cell is provided, and the threshold voltage after erasing or writing to this monitoring cell is checked to control the erasing or writing of the memory cell on the main body side.

[0062]

As described above, according to the present invention, erasing or writing is performed using a monitoring cell having a configuration equivalent to the memory cell on the main body side, and the threshold value of this monitoring cell is compared with a predetermined value. By controlling the erasing or writing operation of the memory cells, the work of verifying all the memory cells becomes unnecessary, and overerasure or overprogramming can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a procedure for erasing data in the nonvolatile semiconductor memory device.

FIG. 3 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing a procedure for erasing data in the nonvolatile semiconductor memory device.

FIG. 5 is a vertical cross-sectional view showing a structure of an element when writing is performed to a memory cell and a monitoring cell on a main body side in the same nonvolatile semiconductor memory device.

FIG. 6 is a block diagram showing a configuration of a conventional nonvolatile semiconductor memory device.

FIG. 7 is a flowchart showing a procedure for erasing data in the nonvolatile semiconductor memory device.

FIG. 8 is a vertical cross-sectional view showing structures of elements of a cell in a normal erased state and a cell in which writing is performed in the same nonvolatile semiconductor memory device.

FIG. 9 is an explanatory diagram showing distributions of threshold voltages of cells in a normal erased state and written cells in the same nonvolatile semiconductor memory device.

FIG. 10 is a vertical cross-sectional view showing the structure of an element of a cell in which overerasing is performed in the same nonvolatile semiconductor memory device.

FIG. 11 is an explanatory diagram showing a threshold voltage distribution of cells in which overerasure has been performed in the same nonvolatile semiconductor memory device.

FIG. 12 is a circuit diagram showing an arrangement of a cell array of another conventional nonvolatile semiconductor memory device.

FIG. 13 is a block diagram showing the configuration of still another conventional nonvolatile semiconductor memory device.

FIG. 14 is a flowchart showing a writing procedure in the nonvolatile semiconductor memory device.

FIG. 15 is a vertical cross-sectional view showing structures of elements in a cell in an erased state and a cell in which normal writing has been performed in the same nonvolatile semiconductor memory device.

FIG. 16 is an explanatory diagram showing threshold voltage distributions of cells in an erased state and cells in which normal writing has been performed in the same nonvolatile semiconductor memory device.

FIG. 17 is a circuit diagram showing the configuration of still another conventional nonvolatile semiconductor memory device.

FIG. 18 is an explanatory diagram showing a distribution of threshold voltages of cells on which over-programming is performed in the same nonvolatile semiconductor memory device.

[Explanation of symbols]

 11 erase voltage circuit 12 program voltage circuit 13 control circuit 14 data buffer 15 verify circuit 16 address buffer 17 comparison circuit 18 sense amplifier 19,68 column decoder 20,67 memory cell array 21,70 row decoder 22,92 step-down circuit 23,93 step-up Circuit 40 Semiconductor substrate 41 Source region 42 Drain region 43 Floating gate 45 Gate electrode 62 Control circuit 63 Data buffer 64 Verify circuit 66 Address buffer 69 Sense amplifier / latch circuit 91 Comparison circuit 94 Internal voltage generation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/788 29/792 H01L 27/10 434 29/78 371

Claims (16)

[Claims] 1. A memory cell array in which a plurality of memory cells are arranged, a plurality of bits of the memory cell array are simultaneously erased, and the threshold value of the memory cell after the erase is required to be within a predetermined range. In a nonvolatile semiconductor memory device capable of electrically writing and erasing, a monitoring cell having a cell structure equivalent to the memory cell, and a threshold value and a predetermined value of the monitoring cell after erasing the monitoring cell And an erase control circuit for controlling the operation of erasing the memory cell in accordance with the comparison result with a non-volatile semiconductor memory device. 2. The non-volatile semiconductor memory device according to claim 1, wherein the monitoring cell is erased by applying a voltage different from an erase voltage used when erasing the memory cell. 3. At least 2 as the monitoring cell.
2. The non-volatile semiconductor memory device according to claim 1, further comprising one of them, wherein an erase voltage different from an erase voltage used when the memory cell is erased is applied to erase. 4. The non-volatile semiconductor memory device according to claim 1, wherein the monitoring cell is erased at the same time when the memory cell is erased. 5. The non-volatile semiconductor memory device according to claim 1, wherein the monitoring cell is erased by applying a voltage for the same time as when the memory cell is erased. 6. The non-volatile memory according to claim 1, wherein the erase control circuit has an output means for outputting a signal indicating the threshold value of the monitoring cell to the outside when the threshold value of the monitoring cell substantially matches the predetermined value. Semiconductor memory device. 7. The erase control circuit alternately performs an operation of erasing the memory cell and the monitoring cell and an operation of comparing a threshold value of the monitoring cell with the predetermined value, and a threshold value of the monitoring cell is changed. The operation of erasing the memory cell and the monitoring cell is continued until the threshold value of the monitoring cell substantially matches the predetermined value, and the operation of erasing the memory cell and the monitoring cell is stopped when the threshold value of the monitoring cell substantially matches the predetermined value. The method according to claim 1, wherein
The nonvolatile semiconductor memory device described. 8. The non-volatile semiconductor memory device according to claim 1, wherein the erase control circuit controls an operation of erasing the memory cell based on a signal applied from the outside. 9. A memory cell array in which a plurality of memory cells are arranged, and it is necessary that a plurality of bits of the memory cell array are simultaneously written, and the threshold value of the memory cell after writing is within a predetermined range. In the electrically writable non-volatile semiconductor memory device, a monitoring cell having a cell structure equivalent to the memory cell is written, and after writing to the monitoring cell, the threshold value of the monitoring cell is compared with a predetermined value. And a write control circuit for controlling an operation of writing to the memory cell according to the comparison result. 10. The non-volatile semiconductor memory device according to claim 9, wherein the monitoring cell is written by applying a voltage different from a write voltage used when writing to the memory cell. 11. The monitoring cell according to claim 9, wherein at least two monitoring cells are provided, and the monitoring cells are written by applying different voltages to write voltages used when writing to the memory cells. Nonvolatile semiconductor memory device. 12. The non-volatile semiconductor memory device according to claim 9, wherein the monitoring cell is written simultaneously when writing to the memory cell. 13. The non-volatile semiconductor memory device according to claim 9, wherein the monitoring cell is written by applying a voltage for the same time as when writing to the memory cell. 14. The nonvolatile memory according to claim 9, wherein the write control circuit has an output means for outputting a signal indicating that the threshold value of the monitoring cell substantially coincides with the predetermined value, to the outside. Semiconductor memory device. 15. The write control circuit performs an operation of writing to the memory cell and the monitoring cell,
Alternately performing an operation of comparing the threshold voltage of the monitoring cell and the predetermined value, until the threshold of the monitoring cell substantially matches the predetermined value, continue the operation of writing to the memory cell and the monitoring cell, 10. The non-volatile semiconductor memory device according to claim 9, wherein when the threshold voltage of the monitoring cell is substantially equal to the predetermined value, the write operation to the memory cell and the monitoring cell is stopped. 16. The nonvolatile semiconductor memory device according to claim 9, wherein the write control circuit controls an operation of writing to the memory cell based on a signal applied from the outside.