CN104051012A - Memory erase method and device - Google Patents

Memory erase method and device Download PDF

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Publication number
CN104051012A
CN104051012A CN201310084243.3A CN201310084243A CN104051012A CN 104051012 A CN104051012 A CN 104051012A CN 201310084243 A CN201310084243 A CN 201310084243A CN 104051012 A CN104051012 A CN 104051012A
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China
Prior art keywords
erase
erase verification
voltage
verification
target
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CN201310084243.3A
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Chinese (zh)
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CN104051012B (en
Inventor
张现聚
丁冲
苏志强
程莹
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北京兆易创新科技股份有限公司
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Abstract

The invention provides a memory erase method and a device. The method comprises the following steps: preprogramming operation is carried out on a target erase block; first erase pulse is applied to carry out first erase operation on the target erase block which undergoes preprogramming operation; first excessive erase verification operation is carried out on the target erase block; first erase verification operation is carried out on the target erase block; whether the first erase verification operation is successful is judged; second erase pulse is applied to carry out second erase operation on the target erase block which has undergone the preprogramming operation; second excessive erase verification operation is carried out on the target erase block; second erase verification operation is carried out on the target erase block; whether the second erase verification operation is successful is judged; and third excessive erase verification operation is carried out on the target erase block. According to the invention, excessive erase risks are greatly reduced; a lot of time required by excessive erase restoration is shortened; and erase reliability and speed of a memory are raised.

Description

A kind of method and apparatus of memory erase

Technical field

The present invention relates to semiconductor memory technologies field, particularly relate to a kind of method and apparatus of memory erase.

Background technology

In storer, exist two kinds of basic unit of storage cell, erase (wiping) cell and program (programming) cell, also be " 1 " cell and " 0 " cell, therefore correspondence also just exists the basic operation of wiping and programming these two kinds of memory cells.Wherein, " 0 " cell is become to the process of " 1 " cell, be called and wipe; Otherwise be called programming.

With reference to Fig. 1, be depicted as a kind of traditional memory erase authentication mechanism process flow diagram, its principle is as follows: first to carrying out the target erase block block of erase operation, carry out Pre_PGM (pre-programmed) operation, object is that all cell are programmed for to same " 0 " cell, even if also cell is in threshold state.Then, first erase pulse (erasing pulse) arrives, and to having carried out the cell of Pre_PGM, wipes.And then carry out OEV1 (crossing erase verification) operation, to be the threshold voltage wiped by crossing for existing carry out once weak programming lower than " 1 " cell of 0V to object that (" weak " refers to respect to the about 9V of common program (programming) voltage, here weak program voltage is probably in 0V~2V left and right), more than shifting its threshold voltage onto 0V, such as 1V left and right, to eliminate the leakage current that may cause.Next step is EV (erase verification) operation, if but, again wipes, second erasing pulse arrives, so move in circles, until EV by or erase counter (erasing pulse number of times) reach maximum number, then jump out circulation, carry out OEV2 operation.OEV2 is similar with OEV1, and object is further to raise the threshold voltage of " 1 " cell to eliminate possible subthreshold voltage conducting leakage current.So far, completed the erase operation to target erase block block.

With reference to Fig. 2, be depicted as a kind of traditional memory erase principle schematic, above-mentioned legacy memory erase mechanism exists very large shortcoming.First, Erase process can cause Over Erased Cell (cross eraseable memory unit), as above shown in oblique line part, thereby brings leakage current; Secondly, the OEV that Over Erased Cell is carried out repairs can expend a large amount of time again, thereby reduces whole erasing speed.

Therefore, one of problem that those skilled in the art are in the urgent need to address is, has proposed a kind of erase verification mechanism of wiping risk that reduced, and has not only greatly reduced to cross and has wiped risk, and shortened to cross to wipe and repaired the required plenty of time, that has improved storer wipes reliability and speed.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of method and apparatus of memory erase, has not only greatly reduced to cross and has wiped risk, and shortened to cross to wipe and repaired the required plenty of time, and that has improved storer wipes reliability and speed.

In order to address the above problem, the invention discloses a kind of method of memory erase, comprising:

Step 101, carries out pre-programmed operation to target erase block;

Step 102, applies the first erasing pulse the target erase block through pre-programmed operation is carried out to the first erase operation;

Step 103, carries out first to described target erase block and crosses erase verification operation;

Step 104, whether the number of times that applies the first erasing pulse described in judgement reaches the first erasing times of maximum preset; If so, perform step 112, if not, perform step 105;

Step 105, carries out the first erase verification operation to described target erase block;

Step 106, judges that whether described the first erase verification operation is successful; If so, perform step 107, if not, return to step 102;

Step 107, applies the second erasing pulse the described target erase block through pre-programmed operation is carried out to the second erase operation;

Step 108, carries out second to described target erase block and crosses erase verification operation;

Step 109, whether the number of times that judgement applies the second erasing pulse reaches the second erasing times of maximum preset; If so, perform step 112, if not, perform step 110;

Step 110, carries out the second erase verification operation to described target erase block;

Step 111, judges that whether described the second erase verification operation is successful; If so, perform step 112, if not, return to step 107;

Step 112, carries out the 3rd to described target erase block and crosses erase verification operation.

Preferably, the intensity of described the first erasing pulse applying in the first erase operation, is greater than the intensity of the second erasing pulse applying in described the second erase operation;

And/or,

The described time that applies the first erasing pulse in the first erase operation, be more than or equal to time of the second erasing pulse applying in described the second erase operation.

Preferably, described judge the first erase verification operation whether successfully step comprise:

Storage unit in described target erase block is applied the first erase verification voltage and generates first threshold electric current;

Judge that whether described first threshold electric current is higher than the first predetermined current value;

If so, judge that described the first erase verification operates successfully;

If not, judge described the first erase verification operation failure.

Preferably, described judge the second erase verification operation whether successfully step comprise:

Storage unit in described target erase block is applied the second erase verification voltage and generates Second Threshold electric current;

Judge that whether described Second Threshold electric current is higher than the second predetermined current value;

If so, judge that described the second erase verification operates successfully;

If not, judge described the second erase verification operation failure.

Preferably, the described the 3rd cross voltage that erase verification operation applies for storage unit and higher than first, cross erase verification operation and second and cross erase verification and operate the voltage applying for storage unit.

Preferably, the voltage that the voltage that described the first erase verification operation applies for storage unit applies for storage unit higher than the second erase verification operation.

Preferably, described pre-programmed is operating as the storage unit in target erase block is programmed for to 0 value; Described cross erase verification be operating as adopt default program voltage for threshold voltage lower than specific voltage value, and the storage unit that value is 1 is programmed; Wherein, described specific voltage value is 0V, and described default program voltage is the arbitrary value in 0V-2V.

The device that the embodiment of the invention also discloses a kind of memory erase, comprising:

Pre-programmed module, for carrying out pre-programmed operation to target erase block;

First wipes module, for applying the first erasing pulse, the target erase block through pre-programmed operation is carried out to the first erase operation;

First crosses erase verification module, for described target erase block being carried out to first, crosses erase verification operation;

Whether first number judge module, reach the first erasing times of maximum preset for applying the number of times of the first erasing pulse described in judging; If so, call the 3rd and excessively wipe module, if not, call the first erase verification module;

The first erase verification module, for carrying out the first erase verification operation to described target erase block;

Whether first wipes judge module, successful for judging described the first erase verification operation; If so, call second and wipe, if not, call first and wipe module;

Second wipes module, for applying the second erasing pulse, the described target erase block through pre-programmed operation is carried out to the second erase operation;

Second crosses erase verification module, for described target erase block being carried out to second, crosses erase verification operation;

Second time number is sentenced module, and whether the number of times that applies the second erasing pulse for judging reaches the second erasing times of maximum preset; If so, call the 3rd and excessively wipe module, if not, call the second erase verification module;

The second erase verification module, for carrying out the second erase verification operation to described target erase block;

Whether second wipes judge module, successful for judging described the second erase verification operation; If so, call the 3rd and excessively wipe module, if not, return to second and wipe module;

The 3rd wipes module excessively, for described target erase block being carried out to the 3rd, crosses erase verification operation.

Preferably, the intensity of described the first erasing pulse applying in the first erase operation, is greater than the intensity of the second erasing pulse applying in described the second erase operation;

And/or,

The described time that applies the first erasing pulse in the first erase operation, be more than or equal to time of the second erasing pulse applying in described the second erase operation.

Preferably, described first wipe judge module and comprise:

The first voltage submodule, for applying the first erase verification voltage and generate first threshold electric current described target erase block storage unit;

The first electric current judgement submodule, for judging that whether described first threshold electric current is higher than the first predetermined current value; If so, call first and be proved to be successful submodule, if not, call the first authentication failed submodule;

First is proved to be successful submodule, for judging that described the first erase verification operates successfully;

The first authentication failed submodule, for judging described the first erase verification operation failure.

Preferably, described second wipe judge module and comprise:

Second voltage submodule, for applying the second erase verification voltage and generate Second Threshold electric current described target erase block storage unit;

The second electric current judgement submodule, for judging that whether described Second Threshold electric current is higher than the second predetermined current value; If so, call second and be proved to be successful submodule, if not, call the second authentication failed submodule;

Second is proved to be successful submodule, for judging that described the second erase verification operates successfully;

The second authentication failed submodule is judged described the second erase verification operation failure.

Preferably, the described the 3rd cross voltage that erase verification operation applies for storage unit and higher than first, cross erase verification operation and second and cross erase verification and operate the voltage applying for storage unit.

Preferably, the voltage that the voltage that described the first erase verification operation applies for storage unit applies for storage unit higher than the second erase verification operation.

Preferably, described pre-programmed is operating as the storage unit in target erase block is programmed for to 0 value; Described cross erase verification be operating as adopt default program voltage for threshold voltage lower than specific voltage value, and the storage unit that value is 1 is programmed; Wherein, described specific voltage value is 0V, and described default program voltage is the arbitrary value in 0V-2V.

Compared with prior art, the present invention includes following advantage:

Erasing speed is one of important performance indexes of storer in practice, in order to improve memory erase speed, the present invention proposes a kind of erase verification mechanism of wiping risk that reduced, by introduce the circulation of twice erase operation in erase process, not only greatly reduced to cross and wiped risk, and shortened and crossed erase verification and repair the required plenty of time, thereby improved greatly storer wipe reliability and speed, greatly improved memory performance.

Accompanying drawing explanation

Fig. 1 is a kind of traditional memory erase authentication mechanism process flow diagram;

Fig. 2 is a kind of traditional memory erase principle schematic;

Fig. 3 is the flow chart of steps of the embodiment of the method for a kind of memory erase of the present invention;

Fig. 4 is a kind of Erase Pulse erasing pulse schematic diagram of the present invention;

Fig. 5 is a kind of erase verification mechanism principle schematic diagram of wiping risk that reduced of the present invention;

Fig. 6 is the structured flowchart of the device embodiment of a kind of memory erase of the present invention.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.

One of core idea of the present invention is, by introduce the circulation of twice erase operation in erase process, not only greatly reduced to cross and wiped risk, and shortened erase verification and repaired the required plenty of time, thereby that has improved greatly storer wipes reliability and speed, has greatly improved memory performance.

With reference to Fig. 3, show the flow chart of steps of the embodiment of the method for a kind of memory erase of the present invention, described method specifically can comprise the steps:

Step 101, carries out pre-programmed operation to target erase block;

In embodiments of the present invention, described pre-programmed operation (Pre_PGM) is can be 0 value by the storage unit programming in target erase block; In specific implementation, pre-programmed operation is to write 0 for the cell in target erase block (block), that is to say and makes cell in high threshold voltage state, to improve the stability of erase operation.

Be understandable that, in practice, for the cell in target erase block (block), be not that each must carry out pre-programmed step, be that data in some cell were exactly " 0 " originally, so just can unnecessary execution pre-programmed operation for this part cell; And only to carrying out the cell of pre-programmed operation, the cell that is " 1 " as data carries out pre-programmed operation.

Step 102, applies the first erasing pulse the target erase block through pre-programmed operation is carried out to the first erase operation;

After target erase block being completed to pre-programmed operation, then start Erase1 (wiping for the first time) circulation, the erase pulse (erasing pulse) that applies circulation for the first time wipes having carried out the cell of pre-programmed operation.

Step 103, carries out first to described target erase block and crosses erase verification operation;

In embodiments of the present invention, described cross erase verification be operating as adopt default program voltage for threshold voltage lower than specific voltage value, and the storage unit that value is 1 is programmed; Wherein, described specific voltage value can be 0V, and described default program voltage can be the arbitrary value in 0V-2V.

For having applied the target erase block of the erasing pulse of circulation for the first time, then carry out OEV1 (first crosses erase verification) operation, to be the threshold voltage wiped of the mistake for existing carry out once weak programming lower than " 1 " cell of 0V to object that (" weak " is with respect to the about 9V of common program (programming) voltage, here weak program (programming) voltage is probably in 0V-2V left and right), more than shifting the threshold voltage of cell onto 0V, such as 1V left and right, to eliminate the leakage current that may cause.

Step 104, whether the number of times that applies the first erasing pulse described in judgement reaches the first erasing times of maximum preset; If so, perform step 112, if not, perform step 105;

In specific implementation, may can not arrive normal state through the cell crossing after erase verification operation always, for fear of the endless loop that is absorbed in that causes erase operation, maximum can be set and apply erasing pulse number of times, when applying the number of times of erasing pulse and reach maximum impulse number of times, can jump out the circulation of erase operation for the first time.

Step 105, carries out the first erase verification operation to described target erase block;

Described the first erase verification operates by apply the first erase verification voltage at cell grid, thereby reads cell electric current, and itself and the first erase verification reference current value are compared, and then is used for judging whether successfully first wipe.

Step 106, judges that whether described the first erase verification operation is successful; If so, perform step 107, if not, return to step 102;

In a preferred embodiment of the present invention, described step 106 specifically can comprise following sub-step:

Sub-step S11, applies the first erase verification voltage and generates first threshold electric current storage unit in described target erase block;

Sub-step S12, judges that whether described first threshold electric current is higher than the first predetermined current value; If so, carry out sub-step S13, if not, carry out sub-step S14;

Sub-step S13, judges that described the first erase verification operates successfully;

Sub-step S14, judges described the first erase verification operation failure.

In practice, whether the successful method of the first erase operation is to use the first erase verification voltage to go the data of reading to store in cell in verification.When the first erase verification voltage is added to cell grid, cell can produce corresponding electric current, with default reference current value, compares, and judgement is " 1 " or " 0 ", and judged result can be verified and wipe successfully or failure thus.

Step 107, applies the second erasing pulse the described target erase block through pre-programmed operation is carried out to the second erase operation;

In a preferred embodiment of the present invention, the intensity of described the first erasing pulse applying in the first erase operation, can be greater than the intensity of the second erasing pulse applying in described the second erase operation;

And/or,

The described time that applies the first erasing pulse in the first erase operation, can be more than or equal to time of the second erasing pulse applying in described the second erase operation.

With reference to Fig. 4, be depicted as a kind of Erase Pulse erasing pulse schematic diagram of the present invention, as follows for the actual conditions of the first erasing pulse applying and the second erasing pulse:

Condition 1: the erasing pulse Erase Pulse1 in erase cycles for the first time used is longer than the time of the erasing pulse Erase Pulse2 in erase cycles for the second time in embodiments of the present invention, such as 8ms, 10ms etc., but be not limited to this, Erase Pulse2 used is shorter than the time of Erase Pulse1 in embodiments of the present invention, such as 1ms, 2ms etc., but be not limited to this.

Condition 2: generally, the Erase erasing voltage intensity V2 that the erasing voltage intensity V1 that in erase cycles, Erase applies is for the first time greater than or at least equals to use in Erase2 circulation in erase cycles for the second time, but be not limited to this.

It should be noted that, two above-mentioned conditions, no matter be to meet separately or meet simultaneously, all belong to protection scope of the present invention, and the present invention does not limit this.

Step 108, carries out second to described target erase block and crosses erase verification operation;

For having applied the target erase block of the erasing pulse of circulation for the second time, then carry out OEV2 (crossing erase verification) operation, to be the threshold voltage wiped by crossing to existing equally carry out more than once weak programming shifts the threshold voltage of cell onto 0V lower than " 1 " cell of 0V object, the realization condition of OEV2 can be identical with OEV1 conditional, can further eliminate the leakage current that may cause.

Step 109, whether the number of times that judgement applies the second erasing pulse reaches the second erasing times of maximum preset; If so, perform step 112, if not, perform step 110;

Preferably, for the erase operation in erase cycles for the second time, maximum can be set equally and apply erasing pulse number of times, when applying the number of times of erasing pulse and reach maximum impulse number of times, can jump out the circulation of erase operation for the first time, avoid causing the endless loop that is absorbed in of secondary erase operation.

Step 110, carries out the second erase verification operation to described target erase block;

In a preferred embodiment of the present invention, the voltage that the voltage that described the first erase verification operation applies for storage unit can apply for storage unit higher than the second erase verification operation.

Described the second erase verification operation can be by apply the second erase verification voltage at cell grid, thereby read cell electric current, and its and the second erase verification reference current value are compared, and then be used for judging whether successfully second wipe.For fear of the threshold voltage of cell is too lowered, the voltage that voltage that the first erase verification operation applies for storage unit applies for storage unit higher than the second erase verification operation can be set.

Step 111, judges that whether described the second erase verification operation is successful; If so, perform step 112, if not, return to step 107;

In a preferred embodiment of the present invention, described step 111 specifically can comprise following sub-step:

Sub-step S21, applies the second erase verification voltage and generates Second Threshold electric current storage unit in described target erase block;

Sub-step S22, judges that whether described Second Threshold electric current is higher than the second predetermined current value; If so, carry out sub-step S23, if not, carry out sub-step S24;

Sub-step S23, judges that described the second erase verification operates successfully;

Sub-step S24, judges described the second erase verification operation failure.

In practice, whether verification second is wiped successful method and verification first to wipe successful method identical, is to use the second erase verification voltage to go the data of reading to store in cell.When the second erase verification voltage is added to cell grid, cell can produce corresponding electric current, with default reference current value, compares, and judgement is " 1 " or " 0 ", and judged result can be verified and wipe successfully or failure thus.

Step 112, carries out the 3rd to described target erase block and crosses erase verification operation.

In a preferred embodiment of the present invention, the described the 3rd crosses voltage that erase verification operation applies for storage unit can cross erase verification operation and second higher than first and cross erase verification and operate the voltage applying for storage unit.

Particularly, in embodiments of the present invention, the 3rd described voltage that erase verification operation applies for storage unit excessively can be 0.8V, the first described voltage that erase verification operates and the second mistake erase verification operation applies for storage unit excessively can be 0.3V-0.4V, the 3rd crosses voltage that erase verification operation applies for storage unit is greater than first and crosses erase verification operation and second and cross erase verification and operate the voltage applying for storage unit, can further make to push away on the threshold voltage of cell.

Further combined with of the present invention a kind of shown in Fig. 5, reduced the erase verification mechanism principle schematic diagram of wiping risk below the present embodiment was described, wherein, X-axis represents Threshold Voltage (threshold V T), and Y-axis represents the number of cell, and specific implementation step is as follows:

Step1: target erase block is applied to program voltage (PV) and carry out pre-programmed operation, make cell in high threshold voltage state;

Step2: target erase block is carried out to erase operation for the first time, make cell in low threshold voltage state, then for the cell wiping, carrying out first wipes verification EV1, avoids the threshold voltage of cell too low, occurs leakage current.

Step3: target erase block is carried out to erase operation for the second time, the threshold voltage of cell is further reduced, then carrying out second for the cell wiping wipes verification EV2 equally, avoids the threshold voltage of cell too low, occurs leakage current.In embodiments of the present invention, the voltage that the voltage that EV1 applies for storage unit can apply for storage unit higher than EV2.

By above-mentioned steps, make the threshold voltage of cell in normal condition, can mistake when reading like this (read) voltage in use and reading the data in cell.

It should be noted that, for embodiment of the method, for simple description, therefore it is all expressed as to a series of combination of actions, but those skilled in the art should know, the application is not subject to the restriction of described sequence of movement, because according to the application, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in instructions all belongs to preferred embodiment, and related action might not be that the application is necessary.

With reference to Fig. 6, be depicted as the structured flowchart of the device embodiment of a kind of memory erase of the present invention, specifically can comprise as lower module:

Pre-programmed module 201, for carrying out pre-programmed operation to target erase block;

First wipes module 202, for applying the first erasing pulse, the target erase block through pre-programmed operation is carried out to the first erase operation;

First crosses erase verification module 203, for described target erase block being carried out to first, crosses erase verification operation;

In a preferred embodiment of the present invention, the voltage that the voltage that described the first erase verification operation applies for storage unit can apply for storage unit higher than the second erase verification operation.

In a preferred embodiment of the present invention, it can be 0 value that described pre-programmed is operating as the storage unit programming in target erase block; Described cross erase verification operation can for adopt default program voltage for threshold voltage lower than specific voltage value, and the storage unit that value is 1 is programmed; Wherein, described specific voltage value can be 0V, and described default program voltage can be the arbitrary value in 0V-2V.

Whether first number judge module 204, reach the first erasing times of maximum preset for applying the number of times of the first erasing pulse described in judging; If so, call the 3rd and excessively wipe module 212, if not, call the first erase verification module 205;

The first erase verification module 205, for carrying out the first erase verification operation to described target erase block;

In a preferred embodiment of the present invention, described first wipes judge module can comprise following submodule:

The first voltage submodule, for applying the first erase verification voltage and generate first threshold electric current described target erase block storage unit;

The first electric current judgement submodule, for judging that whether described first threshold electric current is higher than the first predetermined current value; If so, call first and be proved to be successful submodule, if not, call the first authentication failed submodule;

First is proved to be successful submodule, for judging that described the first erase verification operates successfully;

The first authentication failed submodule, for judging described the first erase verification operation failure.

Whether first wipes judge module 206, successful for judging described the first erase verification operation; If so, call second and wipe 207, if not, call first and wipe module 202;

Second wipes module 207, for applying the second erasing pulse, the described target erase block through pre-programmed operation is carried out to the second erase operation;

In a preferred embodiment of the present invention, the intensity of described the first erasing pulse applying in the first erase operation, can be greater than the intensity of the second erasing pulse applying in described the second erase operation;

And/or,

The described time that applies the first erasing pulse in the first erase operation, can be more than or equal to time of the second erasing pulse applying in described the second erase operation.

Second crosses erase verification module 208, for described target erase block being carried out to second, crosses erase verification operation;

Second time number is sentenced module 209, and whether the number of times that applies the second erasing pulse for judging reaches the second erasing times of maximum preset; If so, call the 3rd and excessively wipe module 212, if not, call the second erase verification module 210;

The second erase verification module 210, for carrying out the second erase verification operation to described target erase block;

Whether second wipes judge module 211, successful for judging described the second erase verification operation; If so, call the 3rd and excessively wipe module 212, if not, return to second and wipe module 207;

In a preferred embodiment of the present invention, described second wipes judge module can comprise following submodule:

Second voltage submodule, for applying the second erase verification voltage and generate Second Threshold electric current described target erase block storage unit;

The second electric current judgement submodule, for judging that whether described Second Threshold electric current is higher than the second predetermined current value; If so, call second and be proved to be successful submodule, if not, call the second authentication failed submodule;

Second is proved to be successful submodule, for judging that described the second erase verification operates successfully;

The second authentication failed submodule is judged described the second erase verification operation failure.

The 3rd wipes module 212 excessively, for described target erase block being carried out to the 3rd, crosses erase verification operation.

In a preferred embodiment of the present invention, the described the 3rd crosses voltage that erase verification operation applies for storage unit crosses erase verification operation and second higher than first and crosses erase verification and operate the voltage applying for storage unit.

For device embodiment, because it is substantially similar to embodiment of the method, so description is fairly simple, relevant part is referring to the part explanation of embodiment of the method.

Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and each embodiment stresses is the difference with other embodiment, between each embodiment identical similar part mutually referring to.

Method and apparatus to a kind of memory erase provided by the present invention above, be described in detail, applied specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.

Claims (14)

1. a method for memory erase, is characterized in that, comprising:
Step 101, carries out pre-programmed operation to target erase block;
Step 102, applies the first erasing pulse the target erase block through pre-programmed operation is carried out to the first erase operation;
Step 103, carries out first to described target erase block and crosses erase verification operation;
Step 104, whether the number of times that applies the first erasing pulse described in judgement reaches the first erasing times of maximum preset; If so, perform step 112, if not, perform step 105;
Step 105, carries out the first erase verification operation to described target erase block;
Step 106, judges that whether described the first erase verification operation is successful; If so, perform step 107, if not, return to step 102;
Step 107, applies the second erasing pulse the described target erase block through pre-programmed operation is carried out to the second erase operation;
Step 108, carries out second to described target erase block and crosses erase verification operation;
Step 109, whether the number of times that judgement applies the second erasing pulse reaches the second erasing times of maximum preset; If so, perform step 112, if not, perform step 110;
Step 110, carries out the second erase verification operation to described target erase block;
Step 111, judges that whether described the second erase verification operation is successful; If so, perform step 112, if not, return to step 107;
Step 112, carries out the 3rd to described target erase block and crosses erase verification operation.
2. method according to claim 1, is characterized in that, the intensity of described the first erasing pulse applying in the first erase operation is greater than the intensity of the second erasing pulse applying in described the second erase operation;
And/or,
The described time that applies the first erasing pulse in the first erase operation, be more than or equal to time of the second erasing pulse applying in described the second erase operation.
3. the method for claim 1, is characterized in that, described judge the first erase verification operation whether successfully step comprise:
Storage unit in described target erase block is applied the first erase verification voltage and generates first threshold electric current;
Judge that whether described first threshold electric current is higher than the first predetermined current value;
If so, judge that described the first erase verification operates successfully;
If not, judge described the first erase verification operation failure.
4. the method for claim 1, is characterized in that, described judge the second erase verification operation whether successfully step comprise:
Storage unit in described target erase block is applied the second erase verification voltage and generates Second Threshold electric current;
Judge that whether described Second Threshold electric current is higher than the second predetermined current value;
If so, judge that described the second erase verification operates successfully;
If not, judge described the second erase verification operation failure.
5. the method for claim 1, is characterized in that, the described the 3rd crosses voltage that erase verification operation applies for storage unit crosses erase verification operation and second higher than first and cross erase verification and operate the voltage applying for storage unit.
6. the method for claim 1, is characterized in that, the voltage that the voltage that described the first erase verification operation applies for storage unit applies for storage unit higher than the second erase verification operation.
7. the method as described in claim 1 or 5, is characterized in that, described pre-programmed is operating as the storage unit in target erase block is programmed for to 0 value; Described cross erase verification be operating as adopt default program voltage for threshold voltage lower than specific voltage value, and the storage unit that value is 1 is programmed; Wherein, described specific voltage value is 0V, and described default program voltage is the arbitrary value in 0V-2V.
8. a device for memory erase, is characterized in that, comprising:
Pre-programmed module, for carrying out pre-programmed operation to target erase block;
First wipes module, for applying the first erasing pulse, the target erase block through pre-programmed operation is carried out to the first erase operation;
First crosses erase verification module, for described target erase block being carried out to first, crosses erase verification operation;
Whether first number judge module, reach the first erasing times of maximum preset for applying the number of times of the first erasing pulse described in judging; If so, call the 3rd and excessively wipe module, if not, call the first erase verification module;
The first erase verification module, for carrying out the first erase verification operation to described target erase block;
Whether first wipes judge module, successful for judging described the first erase verification operation; If so, call second and wipe, if not, call first and wipe module;
Second wipes module, for applying the second erasing pulse, the described target erase block through pre-programmed operation is carried out to the second erase operation;
Second crosses erase verification module, for described target erase block being carried out to second, crosses erase verification operation;
Second time number is sentenced module, and whether the number of times that applies the second erasing pulse for judging reaches the second erasing times of maximum preset; If so, call the 3rd and excessively wipe module, if not, call the second erase verification module;
The second erase verification module, for carrying out the second erase verification operation to described target erase block;
Whether second wipes judge module, successful for judging described the second erase verification operation; If so, call the 3rd and excessively wipe module, if not, return to second and wipe module;
The 3rd wipes module excessively, for described target erase block being carried out to the 3rd, crosses erase verification operation.
9. device according to claim 8, is characterized in that, the intensity of described the first erasing pulse applying in the first erase operation is greater than the intensity of the second erasing pulse applying in described the second erase operation;
And/or,
The described time that applies the first erasing pulse in the first erase operation, be more than or equal to time of the second erasing pulse applying in described the second erase operation.
10. device as claimed in claim 8, is characterized in that, described first wipes judge module comprises:
The first voltage submodule, for applying the first erase verification voltage and generate first threshold electric current described target erase block storage unit;
The first electric current judgement submodule, for judging that whether described first threshold electric current is higher than the first predetermined current value; If so, call first and be proved to be successful submodule, if not, call the first authentication failed submodule;
First is proved to be successful submodule, for judging that described the first erase verification operates successfully;
The first authentication failed submodule, for judging described the first erase verification operation failure.
11. devices as claimed in claim 8, is characterized in that, described second wipes judge module comprises:
Second voltage submodule, for applying the second erase verification voltage and generate Second Threshold electric current described target erase block storage unit;
The second electric current judgement submodule, for judging that whether described Second Threshold electric current is higher than the second predetermined current value; If so, call second and be proved to be successful submodule, if not, call the second authentication failed submodule;
Second is proved to be successful submodule, for judging that described the second erase verification operates successfully;
The second authentication failed submodule is judged described the second erase verification operation failure.
12. devices as claimed in claim 8, is characterized in that, the described the 3rd crosses voltage that erase verification operation applies for storage unit crosses erase verification operation and second higher than first and cross erase verification and operate the voltage applying for storage unit.
13. devices as claimed in claim 8, is characterized in that, the voltage that the voltage that described the first erase verification operation applies for storage unit applies for storage unit higher than the second erase verification operation.
14. devices as described in claim 8 or 12, is characterized in that, described pre-programmed is operating as the storage unit in target erase block is programmed for to 0 value; Described cross erase verification be operating as adopt default program voltage for threshold voltage lower than specific voltage value, and the storage unit that value is 1 is programmed; Wherein, described specific voltage value is 0V, and described default program voltage is the arbitrary value in 0V-2V.
CN201310084243.3A 2013-03-15 2013-03-15 Memory erase method and device CN104051012B (en)

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