TWI443665B - Over-erased verification and repair methods for flash memory - Google Patents

Description

Reverse or gate type flash memory and its over-wipe verification and repair method

The invention relates to an anti-gate type flash (NOR type stack flash) and an over-erased verification and repair method thereof

The design of the inverse or gate type flash memory includes an erase operation to clear the contents of all memory cells to the same value. However, under the erase operation, some memory cells may be over-erased, causing the threshold voltage of the transistors (such as MOS) in the memory cells to be too low, which is easy to cause leakage. Current (leakage).

In order to solve the above leakage current problem, it is necessary to deal with the above-mentioned over-wiping problem.

The invention discloses an anti-gate type flash memory and an over-wipe verification and repair method thereof. The method performs an erase line verification on a sector of the inverse or gate type flash memory, and performs an erase line repair on the line that cannot be verified by the erase line. In addition, the method performs an over-erasing bit verification on a row-by-bit individual that cannot be verified by the over-erase row by the over-erase row, and the bit that cannot be verified by the over-erased bit. The element performs an erase erase bit repair.

The above described objects, features, and advantages of the invention will be apparent from the description and appended claims appended claims

Figure 1 illustrates an embodiment of a memory cell array (corresponding to a sector) in a NOR type stack flash. The number is 100. In an erase operation, there may be over-erased problems. For example, taking the memory unit of the first row (the memory cells connected by the data line BL1) as an example, if some memory cells in the first row are less easily erased during the erasing process, the pair will continue to be All memory cells in the first row are erased until all memory cells on the first row are erased. However, such an operation may erase the memory cells that are not easily erased, but may cause other memory cells in the first row to be over-erased. One phenomenon of over-wiping is that the threshold voltage of the transistor (such as MOS) of the memory cell is suppressed to be low, resulting in leakage current.

Regarding the above-mentioned erasure problem, the case proposes an appropriate solution, which involves "over erasing line verification", "over erasing line repair", "over erasing bit verification" and "over erasing bit repair" technology. . The following is described separately.

Regarding "over-wipe verification", the verification object is a whole line of memory cells. The verification result obtained by this technique is whether there is any erasing problem in the memory cell of the line. It must be noted that over-wipe verification does not necessarily indicate exactly which memory unit the line is having. The over-erase verification technique can be implemented by any over-wipe verification technique developed in the art using "column" as a verification unit.

Regarding "over erasing line repair", an entire erasing memory unit is uniformly erased and repaired, and the memory unit of the line is not individually repaired. The over-erasing repair technique can be implemented by any over-wiping repair technique developed in the art using "column" as a repair unit.

Regarding "over-wipe bit verification", the verification object is a single memory. The unit (bit) or a single group of memory units (bytes), the result of the verification is whether the memory unit of the bit/byte has been erased. The over-erasing bit verification technique can be implemented by any over-wiping verification technique developed in the art by using "bit" or "byte" as a verification unit. The following are discussed in terms of "bits" for the convenience of discussion. It should be noted that the following discussion of "bits" includes examples of "bytes".

Regarding "over erasing bit repair", a single memory unit (bit) or a single group of memory cells (bytes) is erased and repaired. The over-erasing bit repair technique can be implemented by any over-wiping repair technique developed in the art by using "bit" or "byte" as a repair unit. Similarly, the following is discussed in terms of "bits" for the convenience of discussion. It should be noted that the following discussion of "bits" includes examples of "bytes".

In addition, regarding the above-mentioned "over erasing line repair" and "over erasing bit repair", the purpose thereof is to increase the threshold voltage of the repaired memory unit or the transistor (such as MOS) in the memory unit. To avoid leakage currents. The above technique for raising the threshold voltage of a transistor is generally called "soft program or post program". The unified operator of the entire line of memory units is called "line soft programming" and can be used in the "over erasing line repair". It is called "bit soft programming" for each bit operator, and can be used in the "over erasing bit repair".

This paragraph describes an embodiment of the inverse or gate type flash memory over-wipe verification and repair method disclosed in the present application. The method is directed to a sector (sector corresponding to the foregoing memory cell array 100) on a reverse or gate type flash memory. For each column, the above-mentioned "over-wipe verification" is performed individually, and the above-mentioned "over-wipe line repair" is performed on a line that cannot be verified by "erasing the line". In addition, the method further performs the above-mentioned "over-wipe bit verification" by using the "over-wipe-line repair" line by bit-by-bit (for each bit or byte). The above "over erasing bit repair" is performed on the bit that cannot pass the "erasing bit verification". This verification and repair method does not need to be a verification operation for each memory unit in the sector in order to ensure that each memory cell in the sector has no erasing problem as in the conventional technology. In fact, the verification and repair method of this case is to use the "line" as the verification and repair unit to deal with the erasing problem. Only the line that cannot be remedied by the "erasing line" is required to perform each bit. Wipe verification and repair. The method disclosed in this case can complete the erasure verification and repair of one sector in a shorter time and with less operation.

Taking the memory cell matrix 100 disclosed in FIG. 1 as an example, the technique disclosed in the present invention selects a row of memory cells, for example, the first row of memory cells connected by the bit line BL1, as an initial setting of a "test row". Next, the above "test line verification" is performed on the "test line (first line)". Then, it is judged whether or not the "test line (first line)" passes the above "over erasing line verification". If the "test line (first line)" passes the "erasing line verification", an unverified line is selected from the sector (memory cell array 100) - for example, the second line connected by the bit line BL2 Line Memory Unit - Update the "Test Line" and return to the above "Test Line" to perform the "Erase Line Verification" step to switch to the "Secondary Line Verification" of the memory unit of the second line. Or, if the above judgment indicates that the "test line (first line)" has not passed the "erasing line verification", the "test line (first line)" is "erased" Line repair." If the "test line (first line)" cannot pass the "erasing line verification" by "over erasing line repair", then the multiple bits of the "test line (first line)" are executed individually. The above "Erase erase bit verification" and the above "over erase bit repair" for the bit that cannot pass the "Erase erase bit verification"; in addition, if "The test line (first line)" No bit in the cell cannot be unverified from the sector (memory cell array 100) by "over erasing bit repair" by "erase erasing bit" - for example, bit line BL2 Connected second row memory unit - update "test line" and return to the above "test line" to perform "over erase line verification" step to switch to "erasing" the second line of memory cells Line verification." In some implementations, it is considered that a bit in the "test line (first line)" cannot pass the "erasing bit-repair" condition by the "erasing bit-repair", in which a "failure" is issued. The message "displays" the inverse or gate type flash memory over-erasing verification and repair method failed.

FIG. 2 is a flow chart showing an embodiment of the method for verifying and repairing the anti-gate type flash memory over erasing of the present invention, wherein the erasing verification and repair of a sector are explained.

Step S202 is for initial setting of the "test line" (as described above, selecting one line from the memory cell array 100 as a "test line"), and zeroing the "line test loop number". Step S204 performs "erasing line verification" on the "test line". Step S206 determines whether the "test line" passes the "erasing line verification". If it is determined in step S206 that the "test line" cannot pass the "erasing line verification", the flow proceeds to "over erasing line repair" (including the loop formed by steps S208, S212, S214, S204 and S206 of Fig. 2).

This paragraph discusses the "over erasing line repair". First, step S208 is performed, Determine whether the "number of line test loops" reaches a first upper limit (can be set by the user according to requirements). If it is determined in step S208 that the "number of line test loops" has not reached the first upper limit, step S212 is executed to perform "line soft programming" on the "test line". Next, in step S214, "the number of line test loops" is incremented by one. Then, returning to step S204, the "test line" processed by "line soft programming" is again subjected to "erasing line verification", and in step S206, it is determined whether the current "test line" passes the "erasing line". verification". If the step S206 shows that the "test line" processed by "line soft programming" can pass the "erasing line verification", step S216 is executed to determine whether there are any unverified lines in the sector, and steps are performed. S218: Select one of the unverified lines to update the "test line" and return to the "line test loop number". Then, the flow returns to step S204 to perform "over-wipe verification" and subsequent actions on the updated "test line". However, if the "test line" functioned by "soft programming" cannot pass the "erasing line verification" (determined by step S206), as shown in the flowchart of FIG. 2, step S208 is executed again to judge the current Whether or not the "line test loop number" reaches the first upper limit is determined to execute step S212 or to execute step S210. In step S210, it is determined in step S208 that the "row test loop number" reaches the first upper limit. If it is determined in step S208 that the "number of line test loops" reaches the first upper limit, the disclosed method determines that the "test line" cannot pass "erasing line verification" by "over erasing line repair". The flow proceeds to step S210, the "test line" bit by bit is "over erased bit verification", and the "over erase bit correction" is performed for the bit that cannot be "erased by the erased bit". Some embodiments are further illustrated in FIG. 2, and after step S210, a step S220 is further performed to determine whether all the bits of the "test row" can be successfully passed. Erase bit verification." If all can be successful, the flow proceeds to step S216. If it is not successful, a failure message is sent indicating that the reverse or gate flash memory over-validation verification and repair method failed.

This section compares the memory cell array of FIG. 1 with an embodiment of step S220 of FIG. 2 - over-wipe verification and repair with "bits" as the object. Assume that the current "test line" is "the first line (the line of memory cells connected to the bit line BL1)". If the "test line (first line)" needs to be erased and verified with "bit" as the object, select one element from the "test line (first line)" (for example, by word) The memory unit controlled by the line WL1, that is, the memory unit of the first row and the first column) is used as an initial setting of a "test bit", and the "test bit (the memory unit of the first row and the first column) "Over erase level verification" and determine whether the "test bit (memory unit in the first row of the first row)" passes the "erased by bit erase". If the "test bit (memory unit in the first row and first column)" passes the "erased by bit erase", then an unverified bit is selected from "the test line (first line)" - For example, the memory unit controlled by the word line WL2, that is, the memory unit of the first row and the second column - updates the "test bit" and returns to the above-mentioned "test bit" to perform "erasing bit verification" The step of switching to the memory cell of the first row and the second column is "over erase bit verification". Or, if the "test bit (memory unit in the first column of the first row)" fails to pass the "erased by bit erase", then the "test bit" (memory of the first row and the first column) Unit)" performs "Erase erase bit repair". If the "test bit (memory unit in the first row of the first row)" cannot pass the "erase erase bit verification" by the "erase erase bit repair", a failure message is displayed indicating that the execution is reversed or The gate flash memory over erase verification and repair method failed.

Fig. 3 discloses an embodiment of the erasure verification and repair using "bits" as a flowchart. Flow 300 can be used to implement step S220 of Figure 2.

Step S302 is used to initially set the "test bit" (as described above, select one bit from the current "test line" as the "test bit"), and zero the "bit test loop". In step S304, "erasing bit verification" is performed on the "test bit". Step S306 determines whether the "test bit" passes the "erasing bit verification". If it is determined in step S306 that the "test bit" cannot pass the "erasing bit verification", the flow proceeds to "over erasing bit repair" (including steps S308, S310, S312, S304 and S306 of FIG. 3). Loop).

This paragraph discusses the "over erasing bit repair". First, step S308 is executed to determine whether the "bit test loop number" reaches a second upper limit (which can be set by the user according to requirements). In a case where the "bit test loop number" does not reach the second upper limit, step S310 is executed to perform "bit soft programming" on the "test bit". Next, in step S312, the "bit test loop number" is incremented by one. Then, returning to step S304, the "test bit" that has been processed by the "bit soft programming" is again subjected to "over erasing bit verification", and in step S306, it is determined whether the current "test bit" has passed " Over erase bit verification." If the "test bit" processed by the "bit soft programming" has passed the "erasing the bit verification", the step S314 is executed to determine whether there is still an unverified test in the "test line". The bit is executed, and step S316 is executed to update the "test bit" from the unverified bits and return to the "bit test loop number". Then, the process returns to step S304 to perform an "over-wipe bit verification" on the updated "test bit". And follow-up actions. However, if the "test bit" functioned by the "bit soft programming" cannot pass the "erasing of the erasing bit" (as determined by step S306), as shown in the flowchart of FIG. 3, step S308 is executed again. Determine whether the current "bit test loop number" reaches the second upper limit. If the "bit test loop number" does not reach the second upper limit, then step S310 is performed to continue the "over erase bit repair". If the "bit test loop number" has reached the second upper limit, it means that the "test bit" cannot be over-erased by the "erased bit" and the disclosed method will fail to be published. information.

Figure 4 illustrates an embodiment of the inverse or gate type flash memory of the present invention. The inverse or gate type flash memory 400 includes at least one sector (which may be the memory cell array 100 shown in FIG. 1) and a controller 402. The controller 402 can implement the above-described over-wipe verification and repair technology, including performing the above-mentioned "over-wipe verification" on the memory cell array 100 line by line, and performing the line that cannot pass the "erasing line verification". The above "over erasing line repair", and for the line that cannot be verified by "erasing line erasure", the above-mentioned "over erasing bit verification" is performed individually on a bit-by-bit basis, and The above "over erasing bit repair" is performed by the bit of the "erasing bit verification".

In addition, the controller 402 can also be used to implement the aforementioned other over-erasing verification and repair techniques.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧Memory Cell Array

400‧‧‧Anti-gate type flash memory

402‧‧‧ Controller

BL1...BLM‧‧‧ bit line

Multiple steps of S202...S220‧‧‧ sector erasure verification and repair

S302...S316‧‧‧Steps S220 - Multiple steps of an embodiment of over-wipe verification and repair for the "bits" of the current "test line"

WL1...WLN‧‧‧ character line

1 is a diagram showing an embodiment of a memory cell array in a NOR type stack flash; FIG. 2 is a flow chart showing the inverse or gate type flash memory over-wipe verification of the present invention. An embodiment of the repair method, wherein the erasing verification and repair of a sector are explained; FIG. 3 is a flow chart exposing an implementation method of over-wiping verification and repair using "bit" as a target, The disclosed process 300 can be used to implement step S220 of FIG. 2; and FIG. 4 illustrates an embodiment of the inverse or gate type flash memory of the present invention.

S202...S220‧‧‧Multiple steps for erasing verification and repair of a sector

Claims (7)

An anti-gate type flash memory over-wipe verification and repair method, comprising: performing a wipe-by-line verification on a sector on a sector of a reverse or gate type flash memory, and failing to pass the Erasing the row of the row verification to perform an erase row repair; and for the row that cannot be verified by the erase erase row by the erase erase row, the bitwise individual performs an erase erase bit verification, and It is not possible to perform an erase erase bit repair by the bit that has been erased by the erased bit. The method of claim 1, further comprising: selecting a row of memory cells from the sector as an initial setting of a test line; performing the over-wipe verification on the test line; determining the test line Whether the verification is performed by the erase line; if the test line is verified by the erase line, the untested line is selected from the sector to update the test line, and the above-mentioned over-erasing is performed on the test line. The step of verifying the line; and if the test line does not pass the erase line verification, the line is repaired by the erase line, wherein: if the test line cannot be repaired by the erase line If the row verification is erased, the over-erasing bit verification is performed on the plurality of bits in the test row, and the over-erasing bit repair is performed on the bit that cannot be verified by the over-erased bit; If no bit in the test line cannot be verified by the over erase bit by the over erase bit, the unselected from the sector is selected. The past line updates the test line and returns to the step of performing the erase line verification on the test line. The method of claim 2, wherein, if the over-erasing row cannot be repaired, the bit in the test row verified by the over-erasing row cannot be repaired by the over-erasing bit. The over-erasing bit verification verifies that the above-mentioned inverse or gate type flash memory over-erasing verification and repair method fails. The method of claim 3, further comprising setting an initial value of the number of test loops to zero, and performing the following steps when performing the erase erase repair: determining whether the test loop number of the row is Up to a first upper limit; when the number of test loops reaches the first upper limit, it is determined that the test line cannot be verified by the over erase line by the over erase line; and the number of loops tested in the line is not When the first upper limit is reached, a soft programming is performed on the test line, and the number of test loops is increased by one, and it is determined again whether the test line passes the erase erase line verification, wherein: if the test line can be borrowed By the line soft programming, the over-erase row verification is performed, the untested row is selected from the sector to update the test row, and the row test loop number is zeroed to additionally perform the modified test row. After the line verification is performed; and if the test line cannot pass the erase line verification by the line soft programming, the step of determining whether the line test loop number reaches the first upper limit is re-executed. The method of claim 4, further comprising: the verification that the over-erasing line cannot be verified by the over-erasing line Selecting one of the bits of the test line as an initial setting of a test bit; performing the over-erasing bit verification on the test bit; determining whether the test bit is verified by the over-erased bit; The test bit is verified by the over-erased bit, and the untested bit is selected from the test row to update the test bit, and the step of performing the over-erasing bit verification on the test bit is returned. And if the test bit is not verified by the erased bit, the over-pad repair is performed on the test bit, wherein: if the test bit cannot be repaired by the over-erased bit The over-erasing bit verification verifies that the above-mentioned inverse or gate type flash memory over-erasing verification and repair method fails. The method of claim 5, further comprising determining that the test line cannot set the initial value of the one-bit test loop number to be verified by the over-erase line repair by the over-erasing line verification. Zero, and performing the following step of erasing the bit repair: determining whether the number of loops of the bit test reaches a second upper limit; determining the test when the number of loops of the bit test reaches the second upper limit The bit cannot be verified by the over-erasing row by the over-erasing bit; and when the bit-testing loop does not reach the second upper limit, the test bit is subjected to one-bit soft programming, and Adding the number of loops of the bit test to 1 and judging whether the test bit is verified by the erase line, wherein: if the test bit is soft-programmed by the bit, the erased bit is verified by the bit And selecting, from the test line, the unverified bit to update the test bit, and returning to the bit test loop number, and returning to the step of performing the erase erase bit verification on the test bit; and If the test bit cannot be verified by the bit erase bit by the bit soft programming, return to the step of determining whether the bit test loop number reaches the second upper limit. An anti-gate type flash memory, comprising: at least one sector, comprising a memory cell array; and a controller for performing an erase line verification on the memory cell array of the sector row by row, and Performing an erase line repair on the line that cannot be verified by the erase line, and performing an erase bit on the bit by bit for the line that cannot be verified by the erase line by the erase line. Meta-verification, and an erasing bit repair for a bit that cannot be verified by the erased bit.