CN113409840A - State register and write operation method, chip and device thereof - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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Abstract
The invention provides a state register and a write operation method, a chip and a device thereof.A grid electrode of each memory cell is connected to different word lines, a drain electrode of each memory cell is connected to different bit lines, when only part of the memory cells need to be programmed or erased, only corresponding voltage is applied to the word line of the memory cell needing to be operated, and the voltage is not applied to the word lines of other memory cells, so that the memory cell needing no operation can not be subjected to extra pressure, and the influence of the extra pressure on the electrical characteristics of the memory cell is avoided.
Description
Technical Field
The invention relates to the technical field of semiconductor storage, in particular to a state register and a write operation method, a chip and a device thereof.
Background
Generally, there are some independent small storage areas inside the chip, such as status registers, the status memory generally includes a plurality of memory cells, a plurality of word lines and a plurality of bit lines, and all the memory cells of the existing status memory are generally disposed on different bit lines of the same word line. For example, the state memory shown in fig. 4 has two memory cells (cell 0 and cell1, which are only examples and are not limited to two memory cells), and the two memory cells are disposed on the same word line WL _0 (in the figure, the horizontal line WL is a word line, and the vertical line bl is a bit line). The flow of the state memory in the writing operation comprises at least one time of erasing and erasing verification, programming verification and updating data of the state register to the logic control module, wherein when the programming operation and the erasing operation are executed, voltage is applied to the grids of the memory cells through the word lines, and because all the memory cells share one word line, the voltage is simultaneously applied to the grids of all the memory cells, so that stress is caused to the memory cells which do not need to be operated, and the electrical characteristics of the memory cells are degraded.
Disclosure of Invention
In view of the foregoing disadvantages of the prior art, embodiments of the present invention provide a status register, a method, a chip, and an apparatus for writing a status register, which can avoid stressing memory cells that do not need to be operated when performing a program operation or an erase operation.
In a first aspect, an embodiment of the present application provides a status register, which includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines; the drains of the plurality of memory cells are connected to different bit lines; the gates of the plurality of memory cells are connected to different word lines.
According to the state register, as the gates of the memory cells are connected to different word lines, when only part of the memory cells need to be programmed or erased, only the corresponding voltage is applied to the word line of the memory cell needing to be operated, and the voltage is not applied to the word lines of other memory cells, so that the memory cell needing no operation does not bear extra pressure, and the influence on the electrical characteristics of the memory cell caused by the extra pressure is avoided.
In some embodiments, the status register includes 16 of the word lines and 16 of the bit lines.
In other embodiments, the status register includes 22 of the word lines and 22 of the bit lines.
In a second aspect, an embodiment of the present application provides a chip, including the status register.
In a third aspect, an embodiment of the present application provides a write operation method for a status register, where based on the status register, the method includes the steps of:
acquiring a write instruction;
and (4) erasing judgment: judging whether an erasing operation is needed, if so, jumping to an erasing step, otherwise, jumping to a programming judgment step;
erasing: applying a first negative voltage to the word line corresponding to the memory cell which needs to be erased and has a value of 0, so that the value of the corresponding memory cell is changed from 0 to 1;
and (3) erasing verification: detecting whether the values of all memory cells needing to be erased are 1, if so, passing the verification, otherwise, jumping back to the erasing step;
and (3) programming judgment: judging whether programming operation is needed, if so, skipping to the programming step, otherwise, skipping to the data updating step;
programming: applying a first positive voltage to a word line corresponding to a memory cell to be programmed according to the write command, so that the value of the corresponding memory cell is changed from 1 to 0;
and (3) programming verification: detecting whether the values of the cells needing to be programmed are all 0, if so, passing the verification, otherwise, jumping back to the programming step;
and (3) updating data: and updating the data of the state register to the logic control module.
Preferably, the step of erase verifying comprises:
applying a read voltage to word lines corresponding to all memory cells to be erased, and applying a corresponding drain voltage to bit lines corresponding to all memory cells to be erased;
the drain current of each memory cell to be erased is acquired to detect whether the value of each memory cell to be erased is 1.
Preferably, the step of program verifying comprises:
applying a read voltage on a word line corresponding to a memory cell to be programmed, and applying a corresponding drain voltage on a bit line corresponding to the memory cell to be programmed;
the drain current of each memory cell to be programmed is acquired to detect whether the value of each memory cell to be programmed is 0.
In a fourth aspect, an embodiment of the present application provides a write operation apparatus for a status register, configured to perform a write operation on the status register, where the write operation apparatus includes:
the acquisition module is used for acquiring a write instruction;
the erasing judgment module is used for judging whether the erasing operation is needed or not;
the erasing module is used for executing the erasing operation when the erasing operation is needed: applying a first negative voltage to the word line corresponding to the memory cell which needs to be erased and has a value of 0, so that the value of the corresponding memory cell is changed from 0 to 1;
an erase verify module to perform an erase verify operation: detecting whether the values of all memory cells needing to be erased are 1, if so, passing the verification, otherwise, jumping back to the erasing step;
the programming judgment module is used for judging whether programming operation is needed or not;
the programming module is used for executing the programming operation when the programming operation is needed: applying a first positive voltage to a word line corresponding to a memory cell to be programmed according to the write command, so that the value of the corresponding memory cell is changed from 1 to 0;
a program verify module to perform a program verify operation: detecting whether the values of the cells needing to be programmed are all 0, if so, passing the verification, otherwise, jumping back to the programming step;
and the updating module is used for updating the data of the state register to the logic control module.
Preferably, the erase verify module, when performing the erase verify operation:
applying a read voltage to word lines corresponding to all memory cells to be erased, and applying a corresponding drain voltage to bit lines corresponding to all memory cells to be erased;
the drain current of each memory cell to be erased is acquired to detect whether the value of each memory cell to be erased is 1.
Preferably, the program verification module, when performing the program verification operation:
applying a read voltage on a word line corresponding to a memory cell to be programmed, and applying a corresponding drain voltage on a bit line corresponding to the memory cell to be programmed;
the drain current of each memory cell to be programmed is acquired to detect whether the value of each memory cell to be programmed is 0.
Has the advantages that:
according to the state register and the write operation method, the chip and the device thereof provided by the embodiment of the application, as the grid electrodes of the storage units are connected to different word lines, when only part of the storage units are required to be programmed or erased, only the corresponding voltage is applied to the word line of the storage unit required to be operated, and the voltage is not applied to the word lines of other storage units, so that the storage unit not required to be operated cannot be subjected to extra pressure, and the influence of the extra pressure on the electrical characteristics of the storage unit is avoided.
Drawings
Fig. 1 is a schematic structural diagram of a status register according to an embodiment of the present application.
Fig. 2 is a flowchart of a write operation method of a status register according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a write operation apparatus for a status register according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a conventional status register.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The following disclosure provides embodiments or examples for implementing different configurations of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art will recognize applications of other processes and/or uses of other materials.
Referring to fig. 1, a status register according to an embodiment of the present invention includes a plurality of memory cells 1, a plurality of word lines 2 (horizontal lines WL in fig. 1), and a plurality of bit lines 3 (vertical lines bl in fig. 1); the drains of the plurality of memory cells 1 are connected to different bit lines 3; the gates of the plurality of memory cells 1 are connected to different word lines 2.
Therefore, in the state register, the word line 2 and the bit line 3 connected to different memory cells 1 are different from each other, and the memory cells 1 are independent from each other to some extent. Because the gate of each memory cell1 is connected to different word lines 2, when only part of the memory cells 1 need to be programmed or erased, only the corresponding voltage is applied to the word line 2 of the memory cell1 needing to be operated, and the voltage is not applied to the word lines 2 of other memory cells 1, so that the memory cell1 not needing to be operated does not receive extra pressure, and the influence on the electrical characteristics of the memory cell1 caused by the extra pressure is avoided.
In practical applications, the number of memory cells 1 does not exceed the minimum of the number of word lines 2 and the number of bit lines 3, i.e.: assuming that the number of word lines 2 is n1, the number of bit lines 3 is n2, and the number of memory cells 1 is n3, then n3 ≦ min (n 1, n 2). It is thereby ensured that the word line 2 and the bit line 3 to which each memory cell1 is connected are different. Although fig. 1 shows a case where there are two memory cells 1, it is not limited thereto.
In practical applications, the common status registers are specified as 16X16 (i.e., 16 word lines 2 and 16 bit lines 3) and 22X22 (i.e., 22 word lines 2 and 22 bit lines 3). Thus, in some embodiments, the status register includes 16 of the word lines and 16 of the bit lines. In other embodiments, the status register includes 22 of the word lines and 22 of the bit lines. So that the compatibility of the status register is high.
In addition, the embodiment of the application also provides a chip comprising the state register.
Referring to fig. 2, an embodiment of the present application further provides a write operation method for a status register, which is based on the foregoing status register and includes the steps of:
acquiring a write instruction;
and (4) erasing judgment: judging whether an erasing operation is needed, if so, jumping to an erasing step, otherwise, jumping to a programming judgment step;
erasing: applying a first negative voltage to the word line corresponding to the memory cell which needs to be erased and has a value of 0, so that the value of the corresponding memory cell is changed from 0 to 1;
and (3) erasing verification: detecting whether the values of all memory cells needing to be erased are 1, if so, passing the verification, otherwise, jumping back to the erasing step;
and (3) programming judgment: judging whether programming operation is needed, if so, skipping to the programming step, otherwise, skipping to the data updating step;
programming: applying a first positive voltage to a word line corresponding to a memory cell to be programmed according to the write command, so that the value of the corresponding memory cell is changed from 1 to 0;
and (3) programming verification: detecting whether the values of the cells needing to be programmed are all 0, if so, passing the verification, otherwise, jumping back to the programming step;
and (3) updating data: and updating the data of the state register to the logic control module.
Because the gate of each memory cell1 is connected to different word lines 2, when only part of the memory cells 1 need to be programmed or erased, only the corresponding voltage is applied to the word line 2 of the memory cell1 needing to be operated, and the voltage is not applied to the word lines 2 of other memory cells 1, so that the memory cell1 not needing to be operated does not receive extra pressure, and the influence on the electrical characteristics of the memory cell1 caused by the extra pressure is avoided.
The voltage values of the first positive voltage and the first negative voltage can be set according to actual needs, for example, the first positive voltage is 9V, and the first negative voltage is-9V.
In some preferred embodiments, the step of determining the erasure includes:
detecting whether the values of all memory cells needing to be erased are 1;
and if so, judging that the erasing operation is not needed, otherwise, judging that the erasing operation is needed.
Specifically, when detecting whether all memory cells needing to be erased have a value of 1:
applying a read voltage to word lines corresponding to all memory cells to be erased, and applying a corresponding drain voltage to bit lines corresponding to all memory cells to be erased;
the drain current of each memory cell to be erased is acquired to detect whether the value of each memory cell to be erased is 1.
The voltage values of the read voltage and the drain voltage can be set according to actual needs, for example, the read voltage is 4V, and the drain voltage is 1V.
In some preferred embodiments, the step of erase verifying comprises:
if the verification is not passed, the first verification time is + 1; the initial value of the first verification number is 0;
judging whether the first verification frequency reaches a preset first threshold value or not;
if so, the write operation process is ended and a signal indicating an erase failure is issued.
Thereby avoiding trapping in a dead cycle due to a failure to erase successfully all the time.
Further, the step of erase verification includes:
applying a read voltage to word lines corresponding to all memory cells to be erased, and applying a corresponding drain voltage to bit lines corresponding to all memory cells to be erased;
the drain current of each memory cell to be erased is acquired to detect whether the value of each memory cell to be erased is 1.
The voltage values of the read voltage and the drain voltage can be set according to actual needs, for example, the read voltage is 4V, and the drain voltage is 1V.
In some preferred embodiments, the step of programming the determination comprises:
detecting whether the values of all memory cells needing to be programmed are 0;
and if so, judging that the programming operation is not needed, otherwise, judging that the programming operation is needed.
Specifically, when detecting whether the values of all memory cells to be programmed are 0:
applying a read voltage on word lines corresponding to all memory cells to be programmed, and applying corresponding drain voltages on bit lines corresponding to all memory cells to be programmed;
the drain current of each memory cell to be programmed is acquired to detect whether the value of each memory cell to be programmed is 0.
The voltage values of the read voltage and the drain voltage can be set according to actual needs, for example, the read voltage is 4V, and the drain voltage is 1V.
In some preferred embodiments, the step of program verifying comprises:
if the verification is not passed, the second verification times are + 1; the initial value of the second verification number is 0;
judging whether the second verification frequency reaches a preset second threshold value or not;
if so, the write operation process is ended and a signal indicating a programming failure is issued.
Thereby avoiding trapping dead cycles due to a failure to program successfully all the time.
Further, the step of program verifying includes:
applying a read voltage on a word line corresponding to a memory cell to be programmed, and applying a corresponding drain voltage on a bit line corresponding to the memory cell to be programmed;
the drain current of each memory cell to be programmed is acquired to detect whether the value of each memory cell to be programmed is 0.
Referring to fig. 3, an embodiment of the present application further provides a status register write operation apparatus, configured to perform a write operation on the aforementioned status register, where the apparatus includes:
an obtaining module 100, configured to obtain a write instruction;
an erasing judgment module 200, configured to judge whether an erasing operation needs to be performed;
the erasing module 300 is used for executing the erasing operation when the erasing operation is needed: applying a first negative voltage to the word line corresponding to the memory cell which needs to be erased and has a value of 0, so that the value of the corresponding memory cell is changed from 0 to 1;
an erase verify module 400 to perform an erase verify operation: detecting whether the values of all memory cells needing to be erased are 1, if so, passing the verification, otherwise, jumping back to the erasing step;
a programming judgment module 500, configured to judge whether a programming operation is required;
a programming module 600, configured to perform a programming operation when the programming operation is needed: applying a first positive voltage to a word line corresponding to a memory cell to be programmed according to the write command, so that the value of the corresponding memory cell is changed from 1 to 0;
a program verify module 700 to perform a program verify operation: detecting whether the values of the cells needing to be programmed are all 0, if so, passing the verification, otherwise, jumping back to the programming step;
the update module 800 is configured to update the data of the status register to the logic control module.
Because the gate of each memory cell1 is connected to different word lines 2, when only part of the memory cells 1 need to be programmed or erased, only the corresponding voltage is applied to the word line 2 of the memory cell1 needing to be operated, and the voltage is not applied to the word lines 2 of other memory cells 1, so that the memory cell1 not needing to be operated does not receive extra pressure, and the influence on the electrical characteristics of the memory cell1 caused by the extra pressure is avoided.
The voltage values of the first positive voltage and the first negative voltage can be set according to actual needs, for example, the first positive voltage is 9V, and the first negative voltage is-9V.
In some preferred embodiments, the erasure determining module 200, when determining whether an erasure operation is required:
detecting whether the values of all memory cells needing to be erased are 1;
and if so, judging that the erasing operation is not needed, otherwise, judging that the erasing operation is needed.
Specifically, when detecting whether all memory cells needing to be erased have a value of 1:
applying a read voltage to word lines corresponding to all memory cells to be erased, and applying a corresponding drain voltage to bit lines corresponding to all memory cells to be erased;
the drain current of each memory cell to be erased is acquired to detect whether the value of each memory cell to be erased is 1.
The voltage values of the read voltage and the drain voltage can be set according to actual needs, for example, the read voltage is 4V, and the drain voltage is 1V.
In some preferred embodiments, the erase verify module 400, when performing an erase verify operation:
if the verification is not passed, the first verification time is + 1; the initial value of the first verification number is 0;
judging whether the first verification frequency reaches a preset first threshold value or not;
if so, the write operation process is ended and a signal indicating an erase failure is issued.
Thereby avoiding trapping in a dead cycle due to a failure to erase successfully all the time.
Further, the erase verify module 400, when performing an erase verify operation:
applying a read voltage to word lines corresponding to all memory cells to be erased, and applying a corresponding drain voltage to bit lines corresponding to all memory cells to be erased;
the drain current of each memory cell to be erased is acquired to detect whether the value of each memory cell to be erased is 1.
The voltage values of the read voltage and the drain voltage can be set according to actual needs, for example, the read voltage is 4V, and the drain voltage is 1V.
In some preferred embodiments, the program determining module 500, when determining whether a program operation is required:
detecting whether the values of all memory cells needing to be programmed are 0;
and if so, judging that the programming operation is not needed, otherwise, judging that the programming operation is needed.
Specifically, when detecting whether the values of all memory cells to be programmed are 0:
applying a read voltage on word lines corresponding to all memory cells to be programmed, and applying corresponding drain voltages on bit lines corresponding to all memory cells to be programmed;
the drain current of each memory cell to be programmed is acquired to detect whether the value of each memory cell to be programmed is 0.
The voltage values of the read voltage and the drain voltage can be set according to actual needs, for example, the read voltage is 4V, and the drain voltage is 1V.
In some preferred embodiments, the program verification module 700, when performing a program verification operation:
if the verification is not passed, the second verification times are + 1; the initial value of the second verification number is 0;
judging whether the second verification frequency reaches a preset second threshold value or not;
if so, the write operation process is ended and a signal indicating a programming failure is issued.
Thereby avoiding trapping dead cycles due to a failure to program successfully all the time.
Further, the program verification module 700, when performing the program verification operation:
applying a read voltage on a word line corresponding to a memory cell to be programmed, and applying a corresponding drain voltage on a bit line corresponding to the memory cell to be programmed;
the drain current of each memory cell to be programmed is acquired to detect whether the value of each memory cell to be programmed is 0.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, which are substantially the same as the present invention.
Claims (10)
1. A status register includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines; the drains of the plurality of memory cells are connected to different bit lines; wherein the gates of the plurality of memory cells are connected to different word lines.
2. The status register of claim 1, comprising 16 of the word lines and 16 of the bit lines.
3. The status register of claim 1, comprising 22 of said word lines and 22 of said bit lines.
4. A chip comprising a status register according to any of claims 1-3.
5. A method for writing a status register, the status register according to any one of claims 1 to 3, comprising the steps of:
acquiring a write instruction;
and (4) erasing judgment: judging whether an erasing operation is needed, if so, jumping to an erasing step, otherwise, jumping to a programming judgment step;
erasing: applying a first negative voltage to the word line corresponding to the memory cell which needs to be erased and has a value of 0, so that the value of the corresponding memory cell is changed from 0 to 1;
and (3) erasing verification: detecting whether the values of all memory cells needing to be erased are 1, if so, passing the verification, otherwise, jumping back to the erasing step;
and (3) programming judgment: judging whether programming operation is needed, if so, skipping to the programming step, otherwise, skipping to the data updating step;
programming: applying a first positive voltage to a word line corresponding to a memory cell to be programmed according to the write command, so that the value of the corresponding memory cell is changed from 1 to 0;
and (3) programming verification: detecting whether the values of the cells needing to be programmed are all 0, if so, passing the verification, otherwise, jumping back to the programming step;
and (3) updating data: and updating the data of the state register to the logic control module.
6. The method of claim 5, wherein the step of erasing the verify comprises:
applying a read voltage to word lines corresponding to all memory cells to be erased, and applying a corresponding drain voltage to bit lines corresponding to all memory cells to be erased;
the drain current of each memory cell to be erased is acquired to detect whether the value of each memory cell to be erased is 1.
7. The method of claim 5, wherein the step of program verifying comprises:
applying a read voltage on a word line corresponding to a memory cell to be programmed, and applying a corresponding drain voltage on a bit line corresponding to the memory cell to be programmed;
the drain current of each memory cell to be programmed is acquired to detect whether the value of each memory cell to be programmed is 0.
8. A status register write operation apparatus for writing to a status register according to any one of claims 1 to 3, comprising:
the acquisition module is used for acquiring a write instruction;
the erasing judgment module is used for judging whether the erasing operation is needed or not;
the erasing module is used for executing the erasing operation when the erasing operation is needed: applying a first negative voltage to the word line corresponding to the memory cell which needs to be erased and has a value of 0, so that the value of the corresponding memory cell is changed from 0 to 1;
an erase verify module to perform an erase verify operation: detecting whether the values of all memory cells needing to be erased are 1, if so, passing the verification, otherwise, jumping back to the erasing step;
the programming judgment module is used for judging whether programming operation is needed or not;
the programming module is used for executing the programming operation when the programming operation is needed: applying a first positive voltage to a word line corresponding to a memory cell to be programmed according to the write command, so that the value of the corresponding memory cell is changed from 1 to 0;
a program verify module to perform a program verify operation: detecting whether the values of the cells needing to be programmed are all 0, if so, passing the verification, otherwise, jumping back to the programming step;
and the updating module is used for updating the data of the state register to the logic control module.
9. The apparatus of claim 8, wherein the erase verify module, when performing the erase verify operation:
applying a read voltage to word lines corresponding to all memory cells to be erased, and applying a corresponding drain voltage to bit lines corresponding to all memory cells to be erased;
the drain current of each memory cell to be erased is acquired to detect whether the value of each memory cell to be erased is 1.
10. The apparatus of claim 8, wherein the program verify module, when performing the program verify operation:
applying a read voltage on a word line corresponding to a memory cell to be programmed, and applying a corresponding drain voltage on a bit line corresponding to the memory cell to be programmed;
the drain current of each memory cell to be programmed is acquired to detect whether the value of each memory cell to be programmed is 0.
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