CN115312108B - Read-write method of memory chip, electronic device and storage medium - Google Patents
Read-write method of memory chip, electronic device and storage medium Download PDFInfo
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- CN115312108B CN115312108B CN202211230098.0A CN202211230098A CN115312108B CN 115312108 B CN115312108 B CN 115312108B CN 202211230098 A CN202211230098 A CN 202211230098A CN 115312108 B CN115312108 B CN 115312108B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
The application relates to the technical field of memory chips, and particularly provides a read-write method of a memory chip, an electronic device and a storage medium, wherein the method comprises the following steps: before reading or writing a target storage array, acquiring over-erasing flag bit information corresponding to the target storage array, wherein the over-erasing flag bit information is used for identifying whether an unrepaired over-erasing phenomenon is generated in the last erasing process of the corresponding storage array; when the over-erasure flag bit information identifies that an unrepaired over-erasure phenomenon occurs in the last erasure process of the target storage array, performing over-erasure repair on the target storage array; the method can effectively avoid the problem of reading failure or programming failure of the target storage array caused by over-erasing phenomenon, and can solve the problems of reading error and programming failure under the condition of ensuring high electrifying speed of the storage chip.
Description
Technical Field
The present disclosure relates to the field of memory chip technologies, and in particular, to a method for reading and writing a memory chip, an electronic device, and a storage medium.
Background
In the process of erasing a memory array in a memory chip, if abnormal power failure occurs, the memory array can generate an over-erasing phenomenon. The memory chip generally performs over-erase check and repair of the entire memory array during power-on, and the processing method causes the power-on time of the memory chip to be too long, and in some occasions requiring a fast response speed of power-on, the memory chip may skip over-erase check and repair steps of the entire memory array, such as a process of reading a system boot program in the memory chip when power-on is performed, but if the over-erase repair process is directly skipped, a read error or a program failure may be caused, wherein the read error may even cause a serious problem that the system cannot be booted due to a boot failure of the boot program of the read system in some applications.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
The application aims to provide a reading and writing method of a storage chip, an electronic device and a storage medium, which can solve the problem of reading error programming failure under the condition of ensuring high electrifying speed of the storage chip.
In a first aspect, the present application provides a method for reading and writing a memory chip, which includes the following steps:
before reading or writing a target storage array, acquiring over-erasing flag bit information corresponding to the target storage array, wherein the over-erasing flag bit information is used for identifying whether the corresponding storage array generates an over-erasing phenomenon in the last erasing process;
when the over-erasure flag bit information identifies that the target storage array generates an over-erasure phenomenon in the last erasing process, performing over-erasure repair on the target storage array;
and performing read or write operation on the target storage array.
According to the read-write method of the memory chip, before read or write operation is carried out on a target memory array, over-erasure flag bit information corresponding to the target memory array is obtained, and if the over-erasure flag bit information identifies that the target memory array generates an unrepaired over-erasure phenomenon in the last erasing process, over-erasure repair is carried out on the target memory array; when the over-erase flag bit information identifies that the target storage array does not generate an unrepaired over-erase phenomenon in the last erasing process or completes over-erase repair, the method directly performs read or write operation on the target storage array, so that the method can solve the problems of read errors and programming failure under the condition of ensuring high power-on speed of a storage chip.
Optionally, the read-write method of the memory chip further includes the steps of:
and after the target storage array completes over-erasure repair, performing read or write operation on the target storage array.
Optionally, each memory array in the memory chip has a corresponding flag bit for storing the over-erase flag bit information.
Optionally, the memory chip includes a plurality of memory arrays, and the step of acquiring, before performing a read or write operation on a target memory array, over-erase flag bit information corresponding to the target memory array, where the over-erase flag bit information is used to identify whether an unrepaired over-erase phenomenon occurs in a last erase process of the corresponding memory array includes:
recording the over-erasure flag bit information of a plurality of storage arrays by using a plurality of continuous flag bits so that the over-erasure flag bit information forms multi-byte data;
before reading or writing the target storage array, reading and analyzing the over-erasure flag bit information corresponding to the target storage array from the multi-byte data.
Optionally, the read-write method of the memory chip further includes the steps of:
and when the over-erasure flag bit information identifies that the target storage array does not generate an unrepaired over-erasure phenomenon, directly performing read or write operation on the target storage array.
Optionally, if the storage array corresponding to the over-erase flag bit information identifier generates an unrepaired over-erase phenomenon in a last erase process, the over-erase flag bit information is 0, and if the storage array corresponding to the over-erase flag bit information identifier does not generate an unrepaired over-erase phenomenon in the last erase process, the over-erase flag bit information is 1.
Optionally, the memory chip includes a low voltage alarm module, where the low voltage alarm module is configured to generate alarm information when a power supply voltage of the memory chip is low, and the over-erase flag bit information identifies whether an unrepaired over-erase phenomenon occurs in a last erase process of a corresponding memory array based on the following steps:
if the low-voltage alarm module generates alarm information in the last erasing process of the storage array, the storage array corresponding to the over-erasing flag bit information identifier generates an unrepaired over-erasing phenomenon in the last erasing process; if the low-voltage alarm module does not generate alarm information in the last erasing process of the storage array, the storage array corresponding to the over-erasing flag bit information identification does not generate an unrepaired over-erasing phenomenon in the last erasing process.
Optionally, the read-write method of the memory chip further includes the steps of:
and after the target storage array is subjected to over-erasure repair, refreshing the over-erasure flag bit information corresponding to the target storage array.
After the target storage array is subjected to the over-erasure repair, the technical scheme refreshes the over-erasure flag bit information corresponding to the target storage array, so that the situation that the target storage array is subjected to the over-erasure repair repeatedly due to the fact that the over-erasure flag bit information still identifies that the target storage array generates an unrepaired over-erasure phenomenon in the last erasing process is avoided.
In a second aspect, the present application further provides an electronic device, comprising a processor and a memory, where the memory stores computer-readable instructions, and the computer-readable instructions, when executed by the processor, perform the steps of the method as provided in the first aspect.
In a third aspect, the present application also provides a storage medium having a computer program stored thereon, where the computer program runs the steps of the method as provided in the first aspect when executed by a processor.
As can be seen from the above, according to the read-write method of the memory chip, the electronic device and the storage medium provided by the present application, before performing read or write operation on the target storage array, the over-erase flag bit information corresponding to the target storage array is obtained, and if the over-erase flag bit information identifies that the target storage array generates an unrepaired over-erase phenomenon in the last erase process, the over-erase repair is performed on the target storage array; when the over-erase flag bit information identifies that the target storage array does not generate an unrepaired over-erase phenomenon in the last erasing process or completes over-erase repair, the method directly performs read or write operation on the target storage array, so that the method can solve the problems of read errors and programming failure under the condition of ensuring high power-on speed of a storage chip.
Drawings
Fig. 1 is a flowchart of a method for reading a memory chip according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 101. a processor; 102. a memory; 103. a communication bus.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not construed as indicating or implying relative importance.
In the process of erasing a memory array in a memory chip, if abnormal power failure occurs, the memory array can generate an over-erasing phenomenon.
The memory chip generally performs over-erase check and repair of the entire memory array during power-on, but the detection and repair process all targets all memory arrays of the entire memory chip, that is, the power-on process needs to repair all over-erase phenomena of the entire memory chip, so that the power-on time of the memory chip is long, and the memory chip cannot be used in some occasions with a fast power-on reaction speed, therefore, in some occasions with a fast power-on reaction speed, the memory chip can directly skip over-erase check and repair processes to perform fast power-on, although skipping over-erase check and repair processes of all memory arrays can effectively accelerate the power-on speed, but a problem of a read error or a program failure may be caused. In order to avoid the situation of system startup failure in the memory chip, the prior art generally puts the startup program and the cyclically erased address of the system in different arrays, but this approach sacrifices the memory resource of the memory chip to some extent.
In a first aspect, as shown in fig. 1, the present application provides a method for reading and writing a memory chip, which includes the following steps:
s1, before reading or writing a target storage array, acquiring over-erasing zone bit information corresponding to the target storage array, wherein the over-erasing zone bit information is used for identifying whether an unrepaired over-erasing phenomenon is generated in the last erasing process of the corresponding storage array;
s2, when the over-erasure flag bit information identifies that the target storage array generates an unrepaired over-erasure phenomenon in the last erasing process, performing over-erasure repair on the target storage array;
and S3, performing read or write operation on the target storage array.
The target storage arrays in the step S1 are a plurality of storage arrays in the storage chip that need to be read or written, the over-erase flag bit information in the step S1 is stored in the flag bit that is not volatile in power down, the over-erase flag bit information is used to identify whether the corresponding storage array generates an unrepaired over-erase phenomenon in the last erase process, the number of the over-erase flag bit information is the same as that of the storage arrays in the storage chip, and each storage array has the corresponding over-erase flag bit information. The method and the device can judge whether the memory array generates the unrepaired over-erasing phenomenon by detecting whether the memory array generates the abnormal power failure in the last erasing process, and can judge whether the memory array generates the unrepaired over-erasing phenomenon by detecting the leakage of the bit line in the memory array. It should be understood that the number of target storage arrays may be one or more.
When the over-erasure flag bit information identifies that the target storage array generates an unrepaired over-erasure phenomenon in the last erasing process, the step S2 carries out over-erasure repair on the target storage array based on the existing over-erasure repair algorithm; when the over-erase flag bit information identifies that the target storage array does not generate an unrepaired over-erase phenomenon, a read or write operation is directly performed on the target storage array (i.e., step S3 is performed). The target storage array subjected to the read or write operation in the step S3 is a target storage array in which the over-erase flag information identifies that no unrepaired over-erase phenomenon is generated in the last erase process or a target storage array in which the over-erase repair is completed based on the step S2.
According to the method, the over-erase repair check and repair process is set before the read or write operation is performed on the target storage array, so that the over-erase check and the over-erase repair are not required to be performed on all storage arrays of the storage chip in the power-on process, but the read or write operation is performed on the target storage array to perform the check and the over-erase repair on the target storage array, and therefore the corresponding target storage array can be repaired pertinently while the power-on efficiency is ensured, so that the subsequent read or write operation is ensured to be performed smoothly.
The working principle of the embodiment is as follows: the embodiment judges whether the target storage array generates an unrepaired over-erasing phenomenon in the last erasing process by acquiring the over-erasing flag bit information corresponding to the target storage array, if so, the target storage array is subjected to over-erasing repair, after the over-erasing repair is completed, the flag bit is restored to the state that the target storage array does not generate the unrepaired over-erasing phenomenon in the last erasing process, then a starting program is read, the target storage array is subjected to read or write operation after the starting is successful, and if not, the target storage array is directly subjected to read or write operation. In addition, since the over-erase flag bit information is acquired before the write operation is performed on the target storage array in the embodiment, and the over-erase repair is performed on the target storage array when the over-erase flag bit information identifies that the target storage array generates an unrepaired over-erase phenomenon in the last erase process, the embodiment can solve the problem that the over-erased storage unit cannot be programmed and fails to be written due to the unrepaired over-erase phenomenon generated in the last erase process.
According to the read-write method of the memory chip, before a target memory array is read or written, over-erasure flag bit information corresponding to the target memory array is obtained, and if the over-erasure flag bit information marks that an unrepaired over-erasure phenomenon is generated in the last erasing process of the target memory array, over-erasure repair is performed on the target memory array; when the over-erase flag bit information identifies that the target storage array does not generate an unrepaired over-erase phenomenon in the last erasing process or completes over-erase repair, the method directly performs read or write operation on the target storage array, so that the method can solve the problems of read errors and programming failure under the condition of ensuring high power-on speed of a storage chip.
In some embodiments, the method for reading and writing the memory chip further comprises the following steps:
and after the target storage array completes the over-erasing repair, performing read or write operation on the target storage array.
Specifically, after the over-erase repair of the target memory array is completed, the memory cells in the target memory array do not have the problem of electric leakage, so that the problem of reading errors of data of other memory cells caused by the electric leakage of the memory cells and the problem of programming failure of the memory cells can be avoided, and the reading or writing operation performed on the target memory array can be smoothly completed at the moment.
In some embodiments, the memory chip includes a plurality of memory arrays, and step S1 includes:
s11, recording over-erasure flag bit information of a plurality of storage arrays by using a plurality of continuous flag bits so that the over-erasure flag bit information forms multi-byte data;
and S12, reading and analyzing the over-erasure flag bit information corresponding to the target storage array from the multi-byte data before reading or writing the target storage array.
The number of the zone bits in step S11 is the same as the number of the over-erased zone bit information, each zone bit has the corresponding over-erased zone bit information, and after the plurality of over-erased zone bit information are recorded to the plurality of continuous zone bits, the plurality of over-erased zone bit information constitute the multi-byte data. Before performing a read or write operation on the target storage array, step S12 reads and parses the over-erasure flag bit information corresponding to the target storage array in the multi-byte data. For example, when the over-erase flag bit information is 0, the corresponding storage array is identified to have an unrepaired over-erase phenomenon in the last erase process, when the over-erase flag bit information is 1, the corresponding storage array is identified to have no unrepaired over-erase phenomenon in the last erase process, the storage chip includes 4 storage arrays, the over-erase flag bit information corresponding to the storage array a is 1, the over-erase flag bit information corresponding to the storage array B is 1, the over-erase flag bit information corresponding to the storage array C is 1, the over-erase flag bit information corresponding to the storage array D is 0, the multi-byte data generated in step S11 is 1110, and if the target storage array is the storage array C, the over-erase flag bit information obtained in step S12 is 1; if the target storage array is the storage array D, the over-erasure flag bit information obtained in step S12 is 0.
In some embodiments, each memory array in the memory chip has a corresponding flag bit for storing over-erased flag bit information.
Specifically, each storage array corresponds to the flag bit one by one, so that the memory chip can accurately distinguish whether the unrepaired over-erase phenomena exist in different storage arrays, and can accurately and conveniently search the storage arrays with the unrepaired over-erase phenomena.
In some embodiments, if the storage array corresponding to the over-erase flag bit information identifier generates an unrepaired over-erase phenomenon in the last erase process, the over-erase flag bit information is 0, and if the storage array corresponding to the over-erase flag bit information identifier does not generate an unrepaired over-erase phenomenon in the last erase process, the over-erase flag bit information is 1.
In some embodiments, the memory chip includes a low voltage alarm module, the low voltage alarm module is configured to generate alarm information when a power supply voltage of the memory chip is low, and the over-erase flag bit information identifies whether an unrepaired over-erase phenomenon occurs in a last erase process of the corresponding memory array based on the following steps:
if the low-voltage alarm module generates alarm information in the last erasing process of the storage array, the storage array corresponding to the over-erasing zone bit information identification generates an unrepaired over-erasing phenomenon in the last erasing process; if the low-voltage alarm module does not generate alarm information in the last erasing process of the storage array, the storage array corresponding to the over-erasing zone bit information identification does not generate an unrepaired over-erasing phenomenon in the last erasing process.
The low-voltage alarm module is arranged in the storage chip and used for detecting the power supply voltage of the storage chip and generating alarm information when the power supply voltage is low, for example, when the power supply voltage is lower than a preset voltage threshold value, the low-voltage alarm module generates the alarm information. The working principle of the embodiment is as follows: if the low-voltage alarm module generates alarm information in the last erasing process of the storage array, the storage array is considered to generate an over-erasing phenomenon in the last erasing process, and the storage array corresponding to the over-erasing zone bit information identifier generates an unrepaired over-erasing phenomenon in the last erasing process; if the low-voltage alarm module does not generate alarm information in the last erasing process of the storage array, the storage array is considered not to have an erasing phenomenon in the last erasing process, and the storage array corresponding to the over-erasing zone bit information identification does not have an unrepaired over-erasing phenomenon in the last erasing process.
The over-erase flag bit information of the above embodiment identifies that the corresponding storage array does not generate an unrepaired over-erase phenomenon in the last erase process under a default condition, and in the erase operation process of the storage array, if the power down speed is too high, the threshold voltage of the over-erase flag bit information corresponding to the storage array may not be programmed to be very high, so that even if the over-erase phenomenon that is not repaired is generated, the over-erase flag bit information is misjudged as that the over-erase phenomenon is not generated or the generated over-erase phenomenon is repaired. To address the above issues, in some embodiments, a lower threshold voltage is selected as the threshold voltage for the over-erased flag bit information. The working principle of the embodiment is as follows: because the threshold voltage of the over-erased flag bit information is low, that is, the over-erased flag bit information selects a low threshold voltage judgment standard, even if a rapid power failure occurs, the over-erased flag bit information of the embodiment can identify that the corresponding storage array generates an unrepaired over-erase phenomenon in the last erase process, thereby effectively avoiding the situation that the over-erased flag bit information cannot identify the corresponding storage array generates the unrepaired over-erase phenomenon in the last erase process due to the over-high power failure speed.
In some embodiments, the method for reading and writing the memory chip further comprises the steps of:
and S4, after the target storage array is subjected to over-erasure repair, refreshing over-erasure flag bit information corresponding to the target storage array.
After the target storage array is subjected to the over-erase repair, the embodiment refreshes the over-erase flag bit information corresponding to the target storage array, so that the over-erase flag bit information identifies that the target storage array does not generate an unrepaired over-erase phenomenon in the last erase process, and the situation that the target storage array is repeatedly subjected to the over-erase repair due to the fact that the over-erase flag bit information still identifies that the target storage array generates the unrepaired over-erase phenomenon in the last erase process is avoided.
From the above, according to the read-write method for the memory chip provided by the application, before the read-write operation is performed on the target memory array, the over-erasure flag bit information corresponding to the target memory array is acquired, and if the over-erasure flag bit information identifies that the target memory array generates an unrepaired over-erasure phenomenon in the last erasing process, the target memory array is subjected to over-erasure repair; when the over-erase flag bit information identifies that the target storage array does not generate an unrepaired over-erase phenomenon in the last erasing process or completes over-erase repair, the method directly performs read or write operation on the target storage array, so that the method can solve the problems of read errors and programming failure under the condition of ensuring high power-on speed of a storage chip.
In a second aspect, please refer to fig. 2, where fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and the present application provides an electronic device including: a processor 101 and a memory 102, the processor 101 and the memory 102 being interconnected and communicating with each other via a communication bus 103 and/or other form of connection mechanism (not shown), the memory 102 storing a computer program executable by the processor 101, the computer program being executable by the processor 101 to perform the method of any of the alternative implementations of the embodiments when the computing device is run to perform the following functions: before reading or writing a target storage array, acquiring over-erasing flag bit information corresponding to the target storage array, wherein the over-erasing flag bit information is used for identifying whether an unrepaired over-erasing phenomenon is generated in the last erasing process of the corresponding storage array; when the over-erasure flag bit information identifies that the target storage array generates an unrepaired over-erasure phenomenon in the last erasing process, performing over-erasure repair on the target storage array; a read or write operation is performed on the target storage array.
In a third aspect, the present application provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program executes the method in any optional implementation manner of the embodiments to implement the following functions: before reading or writing a target storage array, acquiring over-erasing flag bit information corresponding to the target storage array, wherein the over-erasing flag bit information is used for identifying whether an unrepaired over-erasing phenomenon is generated in the last erasing process of the corresponding storage array; when the over-erasure flag bit information identifies that the target storage array generates an unrepaired over-erasure phenomenon in the last erasing process, performing over-erasure repair on the target storage array; a read or write operation is performed on the target storage array. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
As can be seen from the above, according to the read-write method of the memory chip, the electronic device and the storage medium provided by the present application, before performing read or write operation on the target storage array, the over-erase flag bit information corresponding to the target storage array is obtained, and if the over-erase flag bit information identifies that the target storage array generates an unrepaired over-erase phenomenon in the last erase process, the over-erase repair is performed on the target storage array; when the over-erase flag bit information identifies that the target storage array does not generate an unrepaired over-erase phenomenon in the last erasing process or completes over-erase repair, the method directly performs read or write operation on the target storage array, so that the method can solve the problems of read errors and programming failures under the condition of ensuring high power-on speed of a storage chip.
In the embodiments provided in the present application, it should be understood that the disclosed method may be implemented in other ways.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may ascend to one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A read-write method of a memory chip is characterized by comprising the following steps:
before a read or write operation is performed on a target storage array, the target storage array stores a starting program of a system, and over-erasure flag bit information corresponding to the target storage array is acquired, wherein the over-erasure flag bit information is used for identifying whether an unrepaired over-erasure phenomenon occurs in the last erasure process of the corresponding storage array;
when the over-erasure flag bit information identifies that an unrepaired over-erasure phenomenon is generated in the last erasing process of the target storage array, performing over-erasure repair on the target storage array;
and performing read or write operation on the target storage array.
2. A method for reading from and writing to a memory chip as claimed in claim 1, wherein the method further comprises the steps of:
and after the target storage array finishes over-erasure repair, performing read or write operation on the target storage array.
3. The method according to claim 1, wherein the memory chip includes a plurality of memory arrays, and the step of obtaining the over-erase flag bit information corresponding to the target memory array before performing the read or write operation on the target memory array, where the over-erase flag bit information is used to identify whether the corresponding memory array generates an unrepaired over-erase phenomenon in the last erase process, includes:
recording the over-erasure flag bit information of a plurality of storage arrays by using a plurality of continuous flag bits so that the over-erasure flag bit information forms multi-byte data;
before reading or writing operation is carried out on a target storage array, reading and analyzing the over-erasure flag bit information corresponding to the target storage array from the multi-byte data.
4. The method of claim 1, wherein each memory array in the memory chip has a corresponding flag bit for storing over-erased flag bit information.
5. A method for reading from and writing to a memory chip as claimed in claim 1, wherein the method further comprises the steps of:
and when the over-erasure flag bit information identifies that the target storage array does not generate an unrepaired over-erasure phenomenon, directly performing read or write operation on the target storage array.
6. The method according to claim 1, wherein the over-erase flag bit information is 0 if the memory array corresponding to the over-erase flag bit information identifier has an unrepaired over-erase phenomenon during a previous erase process, and the over-erase flag bit information is 1 if the memory array corresponding to the over-erase flag bit information identifier has no unrepaired over-erase phenomenon during the previous erase process.
7. The method according to claim 1, wherein the memory chip includes a low voltage alarm module, the low voltage alarm module is configured to generate alarm information when a power supply voltage of the memory chip is low, and the over-erase flag bit information identifies whether the corresponding memory array generates an unrepaired over-erase phenomenon in a last erase process based on the following steps:
if the low-voltage alarm module generates alarm information in the last erasing process of the storage array, the storage array corresponding to the over-erasing zone bit information identification generates an unrepaired over-erasing phenomenon in the last erasing process; and if the low-voltage alarm module does not generate alarm information in the last erasing process of the storage array, the storage array corresponding to the over-erasing zone bit information identification does not generate an unrepaired over-erasing phenomenon in the last erasing process.
8. A method for reading from and writing to a memory chip as claimed in claim 1, wherein the method further comprises the steps of:
and after the target storage array is subjected to over-erasure repair, refreshing the over-erasure flag bit information corresponding to the target storage array.
9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method according to any one of claims 1 to 8.
10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211230098.0A CN115312108B (en) | 2022-09-30 | 2022-09-30 | Read-write method of memory chip, electronic device and storage medium |
Applications Claiming Priority (1)
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844847A (en) * | 1995-12-08 | 1998-12-01 | Nec Corporation | Method and Nonvolatile semiconductor memory for repairing over-erased cells |
| US6205059B1 (en) * | 1998-10-05 | 2001-03-20 | Advanced Micro Devices | Method for erasing flash electrically erasable programmable read-only memory (EEPROM) |
| JP2002230981A (en) * | 2001-01-29 | 2002-08-16 | Sharp Corp | Non-volatile semiconductor memory, and its erasing method |
| CN102543194A (en) * | 2010-12-28 | 2012-07-04 | 上海复旦微电子股份有限公司 | Erasing method for flash memory |
| CN104347118A (en) * | 2013-08-02 | 2015-02-11 | 英飞凌科技股份有限公司 | System and Method to Emulate Electrically Erasable Programmable Read-Only Memory |
| CN104751885A (en) * | 2013-12-30 | 2015-07-01 | 北京兆易创新科技股份有限公司 | FLASH chip and erasure or programming method for responding to FLASH chip abnormal power-down |
| CN105511803A (en) * | 2015-11-26 | 2016-04-20 | 北京兆易创新科技股份有限公司 | Processing method of erasing interruption of storage mediums |
| CN112270945A (en) * | 2020-10-22 | 2021-01-26 | 深圳市芯天下技术有限公司 | Method, device, storage medium and terminal for recording power failure during erasing |
| CN114758689A (en) * | 2022-04-08 | 2022-07-15 | 珠海博雅科技股份有限公司 | Erasing method and power-on repair method for nonvolatile memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9275740B2 (en) * | 2013-08-05 | 2016-03-01 | CNEXLABS, Inc. | Method and apparatus for improving data integrity using threshold voltage recalibration |
-
2022
- 2022-09-30 CN CN202211230098.0A patent/CN115312108B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844847A (en) * | 1995-12-08 | 1998-12-01 | Nec Corporation | Method and Nonvolatile semiconductor memory for repairing over-erased cells |
| US6205059B1 (en) * | 1998-10-05 | 2001-03-20 | Advanced Micro Devices | Method for erasing flash electrically erasable programmable read-only memory (EEPROM) |
| JP2002230981A (en) * | 2001-01-29 | 2002-08-16 | Sharp Corp | Non-volatile semiconductor memory, and its erasing method |
| CN102543194A (en) * | 2010-12-28 | 2012-07-04 | 上海复旦微电子股份有限公司 | Erasing method for flash memory |
| CN104347118A (en) * | 2013-08-02 | 2015-02-11 | 英飞凌科技股份有限公司 | System and Method to Emulate Electrically Erasable Programmable Read-Only Memory |
| CN104751885A (en) * | 2013-12-30 | 2015-07-01 | 北京兆易创新科技股份有限公司 | FLASH chip and erasure or programming method for responding to FLASH chip abnormal power-down |
| CN105511803A (en) * | 2015-11-26 | 2016-04-20 | 北京兆易创新科技股份有限公司 | Processing method of erasing interruption of storage mediums |
| CN112270945A (en) * | 2020-10-22 | 2021-01-26 | 深圳市芯天下技术有限公司 | Method, device, storage medium and terminal for recording power failure during erasing |
| CN114758689A (en) * | 2022-04-08 | 2022-07-15 | 珠海博雅科技股份有限公司 | Erasing method and power-on repair method for nonvolatile memory |
Non-Patent Citations (1)
| Title |
|---|
| "65nm_NOR_MLC快闪存储器的低功耗高压电路设计和快速编程算法研究";史维华;《中国博士学位论文全文数据库(电子期刊)》;20150515;全文 * |
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