CN112270945A - Method, device, storage medium and terminal for recording power failure during erasing - Google Patents
Method, device, storage medium and terminal for recording power failure during erasing Download PDFInfo
- Publication number
- CN112270945A CN112270945A CN202011141943.8A CN202011141943A CN112270945A CN 112270945 A CN112270945 A CN 112270945A CN 202011141943 A CN202011141943 A CN 202011141943A CN 112270945 A CN112270945 A CN 112270945A
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- erasing
- block
- power failure
- erased
- power
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
Abstract
The invention discloses a method, a device, a storage medium and a terminal for recording whether power failure occurs during erasing, wherein the method comprises the steps of erasing a block needing to be erased, performing over-erasure repair on the block subjected to the erasing, and programming a power failure flag unit in the block subjected to the over-erasure repair; the detection of the power failure flag unit is added after the conventional erasing process is finished, so that the integrity and effectiveness of the erasing operation at this time are recorded, the problem that the user needs to perform full-chip erasing when the user cannot locate the power failure block is solved, and the user can know the occurrence of power failure; only the specific content of the power failure detection unit needs to be detected to judge whether over-erasing repair needs to be executed or not, and the system does not need to traverse the units on all bit lines, so that the erasing flow time is greatly saved.
Description
Technical Field
The invention relates to the technical field of semiconductor storage, in particular to a method, a device, a storage medium and a terminal for recording whether power failure occurs during erasing.
Background
NOR FLASH loses power during the erase of block a, if the internal algorithm flow is in the erase step (as shown in fig. 1) and there is no repair "over-erased" cell step, then reading this block after power-up may cause data loss in this block, the data read is a random value (depending on the number and distribution of the a block "over-erased" cells, as shown in fig. 2). This causes the following problems:
(1) for the user: existing NOR Flash does not have an instruction to feed back whether a power down has occurred for a user-specified block. The block with power failure can only be re-erased again, but if the user system cannot locate the block with power failure, the risk is caused to the system application, and then the whole chip must be re-erased and reprogrammed.
(2) NOR Flash does not have a flag bit inside to give the user knowledge of which block has an over-erase occurred: for the NOR Flash internal erase algorithm, the NOR Flash can only repair the over-erased block in the next erase step, and the internal algorithm needs to detect the leakage condition of all bit lines of the block to determine whether the block needs to be repaired by "over-erase", and it is time-consuming to traverse all bit lines.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a method, a device, a storage medium and a terminal for recording whether power failure occurs when erasing exists, and aims to solve the problem that the existing NOR Flash does not have an instruction to feed back whether power failure occurs in a block specified by a user.
The technical scheme of the invention is as follows: a method for recording whether power failure occurs during erasing or not specifically comprises the following steps:
carrying out erasing processing on a block needing to be erased;
performing over-erasing repair on the block subjected to the erasing treatment;
and programming the power failure mark unit in the block subjected to the over-erasure repair.
The method for recording whether the power is lost when erasing exists, wherein the power-loss mark unit is a unit on a bit line added in a block needing to be erased.
The method for recording whether the power is lost when the erase exists or not is characterized in that the power-down mark unit is a unit on at least one bit line added in a block needing to be erased.
The method for recording whether the power failure occurs during erasing, wherein the step of outputting the programming result of the power failure mark unit comprises the following steps: and reading and outputting the data of the corresponding flag bit of the status register in the block needing to be erased.
The method for recording whether the power failure occurs during erasing, wherein the step of outputting the programming result of the power failure mark unit comprises the following steps: and reading and outputting data at any position in the block needing to be erased.
An apparatus using the method for recording whether there is power failure during erasing as described in any one of the above, wherein the method comprises:
the erasing module is used for erasing a block needing to be erased;
an over-erase repair module for performing over-erase repair on the block subjected to the erase processing;
and the power failure mark programming module is used for programming the power failure mark units in the blocks subjected to the over-erasure repair.
The device also comprises a status register reading module for reading the data of the corresponding zone bit of the status register in the block needing to be erased.
The device also comprises a block data reading module for reading data at any position in the block needing to be erased.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform any of the methods described above.
A terminal device comprising a processor and a memory, the memory having stored therein a computer program, the processor being configured to execute the method of any one of the preceding claims by calling the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a method, a device, a storage medium and a terminal for recording whether power failure occurs during erasing, wherein the detection of a power failure flag unit is added after the conventional erasing process is finished so as to record the integrity and effectiveness of the erasing operation, thereby solving the problem that a user needs to perform full-chip erasing when the user cannot locate a power failure block and enabling the user to know the occurrence of power failure; only the specific content of the power failure detection unit needs to be detected to judge whether over-erasing repair needs to be executed or not, and the system does not need to traverse the units on all bit lines, so that the erasing flow time is greatly saved.
Drawings
Fig. 1 is a flowchart of the steps of erasing in the prior art.
Fig. 2 is a diagram illustrating the number and distribution of a-block over-erased cells in the prior art.
Fig. 3 is a schematic diagram of a power down flag cell in the present invention.
Fig. 4 shows the steps of the method of the present invention for recording whether there is power loss upon erasure.
Fig. 5 is a schematic view of the apparatus of the present invention.
Fig. 6 is a schematic diagram of a terminal in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 4, a method for recording whether there is power failure during erasing includes the following steps:
s1: and carrying out erasing processing on the block needing to be erased.
S2: and performing over-erasing repair on the block subjected to the erasing treatment.
S3: and programming the power failure mark unit in the block subjected to the over-erasure repair.
When a user sends a Read instruction, reading the programming result of the power-down mark unit together with other word lines; or when the user sends the erasing instruction again, the internal algorithm reads the programming result of the power-down mark unit.
The power-down mark unit is formed by adding at least one bit line in a block needing to be erased, and a nonvolatile unit on the bit line is the power-down mark unit.
By adding a bit line (or several bit lines) of NOR flash to a block to be erased, a power-down flag cell on the bit line is used to record whether power-down over-erase occurs to the block, as shown in fig. 3. In the original erasing algorithm process, the power down detection unit and other normal units are erased simultaneously, and the programming operation is performed on the unit (or units) on the bit line in the last stage of the erasing process (after the "over-erase" repair), if the unit on the bit line is programmed, the normal end of the erasing process is represented, as shown in fig. 4; otherwise, the block needing to be erased has the condition of power failure during erasing.
The number of the increased bit lines is set according to actual needs, and the more the number of the increased bit lines is, the more accurately the block can be detected whether the power-down condition exists during erasing (as long as a unit on any bit line cannot be programmed, the power-down condition exists during erasing), but the corresponding physical unit structure and algorithm flow of the whole block are correspondingly complicated.
The outputting of the programming result of the power-down flag unit can be realized by the following method: (1) whether the block is erased and powered down is judged by reading a corresponding zone bit of a state register (because the state register stores various state information (condition codes) which represent the execution result of the current instruction) in the block which needs to be erased, the zone bit corresponds to the state of a power down zone unit, data of the zone bit corresponding to the state register is output, a user can know whether the block is erased and powered down according to the data, if the situation that the block is erased and powered down is obtained, the block does not normally execute the erasing operation, and the block is defaulted to have an over-erasing unit. (2) Reading the data of the block and outputting: if the power failure detection unit is not successfully programmed, namely the power failure detection unit is in an erasing state, the system automatically sets the data in the block to be 0 (indicating that the body-to-body block is in the programming state and representing that the erasing is not successful after the power failure is erased), so that any position in the block is read, the read data is output, a user can know whether the block is in the power failure during the erasing according to the data, if the situation that the block is in the power failure during the erasing is obtained, the block does not normally execute the erasing operation, and the block is defaulted to have the over-erasing unit. Therefore, whether the block has the over-erased unit or not can be known through detecting the power failure when the block is erased, if the block has the power failure when the block is erased, the system can automatically execute over-erased repair when executing the next erasing command, the over-erased judgment is not needed to be carried out by traversing all bit lines, and the erasing time is greatly saved.
As shown in fig. 5, an apparatus adopting the method for recording whether there is power loss during erasing as described above: the method comprises the following steps:
an erasing module 101 for erasing a block to be erased;
an over-erase repair module 102 for performing over-erase repair on the block subjected to the erase process;
and a power down flag programming module 103 for programming the power down flag cells in the blocks subjected to the erase repair.
In some embodiments, the apparatus further comprises a status register read module 104 for reading data of corresponding flag bits of a status register in the block that needs to be erased.
In some embodiments, the apparatus further includes a block data reading module 105 for reading the block data requiring the erase power failure detection.
Referring to fig. 6, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: carrying out erasing processing on a block needing to be erased; performing over-erasing repair on the block subjected to the erasing treatment; and programming the power failure mark unit in the block subjected to the over-erasure repair.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: carrying out erasing processing on a block needing to be erased; performing over-erasing repair on the block subjected to the erasing treatment; and programming the power failure mark unit in the block subjected to the over-erasure repair. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for recording whether power failure occurs when erasing is carried out is characterized by comprising the following steps:
carrying out erasing processing on a block needing to be erased;
performing over-erasing repair on the block subjected to the erasing treatment;
and programming the power failure mark unit in the block subjected to the over-erasure repair.
2. The method of claim 1, wherein the power down flag cell is a cell on an added bit line in a block that needs to be erased.
3. The method for recording whether there is power-down during erasing as claimed in claim 2, wherein the power-down flag cell is a cell on at least one bit line added in a block that needs to be erased.
4. The method for recording whether there is power-down during erasing according to claim 1, wherein said outputting the programming result of the power-down flag unit comprises the following processes: and reading and outputting the data of the corresponding flag bit of the status register in the block needing to be erased.
5. The method for recording whether there is power-down during erasing according to claim 1, wherein said outputting the programming result of the power-down flag unit comprises the following processes: and reading and outputting data at any position in the block needing to be erased.
6. An apparatus for using the method for recording power loss upon erasure of any of claims 1 to 5, comprising:
the erasing module is used for erasing a block needing to be erased;
an over-erase repair module for performing over-erase repair on the block subjected to the erase processing;
and the power failure mark programming module is used for programming the power failure mark units in the blocks subjected to the over-erasure repair.
7. The apparatus of claim 6, further comprising a status register reading module for reading data of corresponding flag bits of the status register in the block that needs to be erased.
8. The apparatus of claim 6, further comprising a block data reading module to read data anywhere within the block that needs to be erased.
9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 5.
10. A terminal device, characterized in that it comprises a processor and a memory, in which a computer program is stored, said processor being adapted to execute the method of any one of claims 1 to 5 by calling said computer program stored in said memory.
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| CN115312108A (en) * | 2022-09-30 | 2022-11-08 | 芯天下技术股份有限公司 | Read-write method of memory chip, electronic device and storage medium |
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