CN112331252A - Method and device for automatically marking bad blocks of Nand flash memory, storage medium and terminal - Google Patents
Method and device for automatically marking bad blocks of Nand flash memory, storage medium and terminal Download PDFInfo
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- CN112331252A CN112331252A CN202011466653.0A CN202011466653A CN112331252A CN 112331252 A CN112331252 A CN 112331252A CN 202011466653 A CN202011466653 A CN 202011466653A CN 112331252 A CN112331252 A CN 112331252A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5606—Error catch memory
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Abstract
The invention discloses a method, a device, a storage medium and a terminal for automatically marking bad blocks of a Nand flash, wherein the whole process is realized in a single chip microcomputer, all blocks in the Nand flash are searched for the bad blocks in all required data modes, if a certain block has data reading errors in a certain data mode, the block is marked as the bad block, and finally, marking of all the bad blocks in the Nand flash is completed; according to the technical scheme, the time consumption for completing one bad block marking in the single chip microcomputer is far shorter than that of a machine, particularly when data is verified, ECC (error correction code) correction digits can be configured in the single chip microcomputer program at will, the time consumption for judging the same condition by the machine is very long, and one bad block marking can be completed within five minutes by the single chip microcomputer program; and the cost of the single chip microcomputer is much cheaper than that of a machine table, a plurality of nand flash parallel tests can be realized by purchasing a plurality of single chip microcomputers at lower price, and bad block marks of a large number of nand flash can be completed in a short time.
Description
Technical Field
The invention relates to the field of semiconductor packaging and testing, in particular to a method and a device for automatically marking bad blocks of a Nand flash memory, a storage medium and a terminal.
Background
The Nand flash is one of flash memories, has the advantages of large capacity and high erasing speed, is suitable for storing a large amount of data, and is widely applied in the industry. However, Nand technology allows for the presence of bad blocks, which reduces the Nand manufacturing process requirements and also accounts for the lower price per unit capacity of Nand compared to NOR flash. For Nand, a page is considered normal if the page data is not in error or the number of bits in error can be corrected by an ECC (error correction) code, whereas the block in which the page is located is considered as a bad block. Bad blocks can be divided into factory bad blocks and dynamic bad blocks. The factory bad block is marked during factory test and has the following characteristics: the readback data is all 0, and can not be erased by using erase command; and a dynamic bad block refers to a bad block that is dynamically generated during the application process. Bad block marking is to mark a known bad block, and if the first byte of the spare area (spare area) of the 1 st, 2 nd or last page is not FF, the block is usually considered to have been marked as a bad block. In the Nand application process, whether the blcok is good or bad is judged by identifying whether a bad block mark exists or not, so that the bad block is prevented from being used. It can be seen that finding bad blocks in Nand and marking and managing the found bad blocks are very important for the subsequent Nand flash application.
The traditional method is to use a machine to mark the Nand bad block: taking a chroma machine as an example, bad block marking is carried out on one Nand flash, at least 30 minutes are needed, only one Nand flash can be allowed to be tested at one time, the consumed time is long, the occupancy rate of the machine is high, and the efficiency is low; and the price of the machine is high, which increases the marking cost of the bad block.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a method, a device, a storage medium and a terminal for automatically marking bad blocks of a Nand flash memory, and aims to solve the problems that the existing machine table for marking bad blocks is long in time consumption, low in efficiency and high in marking cost.
The technical scheme of the invention is as follows: a Nand flash automatic bad block marking method is disclosed, wherein a Nand flash is loaded into a PCB board card of a singlechip, the whole process is realized in the singlechip, and the method specifically comprises the following steps:
reading the ID of the Nand flash;
all blocks in the Nand flash are subjected to bad block searching in all required data modes;
if a certain block has data reading errors in a certain data mode, marking the block as a bad block, and finally finishing the marking of all the bad blocks in the Nand flash.
The automatic bad block marking method of the Nand flash memory comprises the following steps:
s01: reading the ID of the Nand flash;
s02: selecting a certain data mode;
s03: all blocks in the Nand flash are subjected to bad block judgment in the data mode;
s04: judging whether the Nand flash finishes the bad block judgment under all the data modes, if so, skipping to S05, otherwise, skipping to S02;
s05: and marking all bad blocks in the Nand flash, thereby completing the marking of all bad blocks in the Nand flash.
The automatic bad block marking method of the Nand flash memory comprises the following steps of:
s 31: carrying out full erase on the Nand flash and then carrying out full write-in data;
s 32: reading data written in one block in the Nand flash, judging whether the read data has errors or not, if so, jumping to s33, otherwise, jumping to s 34;
s 33: recording the bad block condition of the block, and jumping to s 34;
s 34: and judging whether all the blocks in the Nand flash finish the bad block judgment, if so, jumping to S04, and otherwise, jumping to S32.
In the method for automatically marking the bad block of the Nand flash memory, in the s33, the bad block condition of the block is recorded by adding 1 to the number of times of the bad block of the block.
In the method for automatically marking bad blocks of the Nand flash, in the step S05, all the bad blocks in the Nand flash are marked by marking the blocks with the number of times that all the bad blocks in the Nand flash are greater than 0.
The utility model provides an automatic bad piece mark device of Nand flash memory, wherein, the automatic bad piece mark device of Nand flash memory sets up in the PCB board of singlechip, packs the Nand flash into the PCB integrated circuit board of singlechip, includes:
the ID reading module is used for reading the ID of the Nand flash;
the searching module is used for searching all the blocks in the Nand flash for bad blocks in all the required data modes;
and the marking module marks a certain block as a bad block if the data reading error occurs in the certain data mode.
The automatic bad block marking device of Nand flash memory, wherein, the automatic bad block marking device of Nand flash memory sets up in the PCB board of STM32 singlechip.
The automatic bad block marking device of the Nand flash memory is characterized in that the marking module writes the address of a bad block into a Nand flash BBT.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform any of the methods described above.
A terminal device comprising a processor and a memory, the memory having stored therein a computer program, the processor being configured to execute the method of any one of the preceding claims by calling the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a method, a device, a storage medium and a terminal for automatically marking bad blocks of a Nand flash, wherein the whole bad block marking process is realized in a single chip microcomputer, the time consumption for marking the bad blocks of a Nand flash is far shorter than that of a machine, particularly when data is checked, ECC error correction digits can be randomly configured in a single chip microcomputer program (the bad blocks are marked if the error is determined if the error exceeds 8 bits/544 bytes), the machine can judge the same condition, the time consumption is very long, and the single chip microcomputer program can mark the bad blocks of the Nand flash within five minutes; and the cost of the single chip microcomputer is much cheaper than that of a machine table, and the parallel test of a large amount of nand flash can be realized by purchasing a plurality of single chip microcomputers at a lower price, so that the bad block marking of the large amount of nand flash can be completed in a short time.
Drawings
FIG. 1 is a flow chart of the steps of the automatic bad block marking method of the Nand flash memory in the invention.
FIG. 2 is a schematic diagram of the confirmation of read to flash id before testing in the present invention.
FIG. 3 is a schematic diagram of writing bad block address information into nand flash BBT in the present invention.
FIG. 4 is a diagram of the present invention for querying bad blocks.
FIG. 5 is a schematic diagram of an automatic bad block marking device of the Nand flash memory in the present invention.
Fig. 6 is a schematic diagram of a terminal in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, the whole process of the automatic bad block marking method for the Nand flash memory is realized in a single chip microcomputer, and the method specifically comprises the following steps:
s1: selecting a certain data mode;
s2: carrying out full erase on the Nand flash and then carrying out full write-in data;
s3: reading data written in one block in the Nand flash, judging whether the read data has errors or not, if so, jumping to S4, otherwise, jumping to S5;
s4: adding 1 to the bad block times of the block, and jumping to S5;
s5: judging whether all the blocks in the Nand flash finish bad block judgment, if so, jumping to S6, otherwise, jumping to S3;
s6: judging whether the Nand flash finishes the bad block judgment under all the data modes, if so, skipping to S7, otherwise, skipping to S1;
s7: and marking all the blocks with the bad block frequency more than 0 in the Nand flash, thereby completing the marking of all the bad blocks in the Nand flash.
In the bad block mark of the Nand flash, all blocks are required to have no data reading errors in all possible data modes, and if a certain block has a data reading error in a certain data mode, the block is judged to be a bad block.
According to the technical scheme, the bad block mark of the nand flash is realized in the single chip microcomputer, the nand flash is controlled through the PCB of the STM32 single chip microcomputer, a control program is stored in the single chip microcomputer, the single chip microcomputer is controlled to send a command, an address and data to the nand flash, so that the bad block in the nand flash is found, the address of the bad block is written into a BBT of the nand flash, the bad block mark is completed, the process of operating the nand flash is written through codes, and the bad block in the nand flash is found and marked.
The method for automatically marking bad blocks in Nand flash memory described above is described by referring to the following embodiments:
1. preparing a Bad block searching and marking program, and loading into an STM32 singlechip PCB card.
2. Before testing, it is confirmed that flash id is read, and at this time, bad block marking is not performed, and no bad block in the IC can be identified, as shown in fig. 2.
3. And sending an instruction, and starting bad block searching and marking, namely obtaining the relevant information of the bad block address and writing the information into the nand flash BBT to finish bad block marking, as shown in fig. 3.
4. Based on identifying the bad block flag, the bad block can be queried as shown in FIG. 4.
As shown in fig. 5, an automatic bad block marking device of Nand flash memory, which is arranged in a PCB board of a single chip microcomputer and loads Nand flash into a PCB board card of the single chip microcomputer, includes:
the ID reading module 103 is used for reading the ID of the Nand flash;
the searching module 101 is used for searching all the blocks in the Nand flash for bad blocks in all the required data modes;
the marking module 102 marks a block as a bad block if a data read error occurs in the block in a certain data mode.
Referring to fig. 6, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: loading the Nand flash into a PCB board card of the singlechip, wherein the whole process is realized in the singlechip; reading the ID of the Nand flash; all blocks in the Nand flash are subjected to bad block searching in all required data modes; if a certain block has data reading errors in a certain data mode, marking the block as a bad block, and finally finishing the marking of all the bad blocks in the Nand flash.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: loading the Nand flash into a PCB board card of the singlechip, wherein the whole process is realized in the singlechip; reading the ID of the Nand flash; all blocks in the Nand flash are subjected to bad block searching in all required data modes; if a certain block has data reading errors in a certain data mode, marking the block as a bad block, and finally finishing the marking of all the bad blocks in the Nand flash. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A Nand flash automatic bad block marking method is characterized in that a Nand flash is installed in a PCB board card of a single chip microcomputer, the whole process is realized in the single chip microcomputer, and the method specifically comprises the following steps:
reading the ID of the Nand flash;
all blocks in the Nand flash are subjected to bad block searching in all required data modes;
if a certain block has data reading errors in a certain data mode, marking the block as a bad block, and finally finishing the marking of all the bad blocks in the Nand flash.
2. The method for automatically marking the bad blocks of the Nand flash memory as claimed in claim 1, comprising the following steps:
s01: reading the ID of the Nand flash;
s02: selecting a certain data mode;
s03: all blocks in the Nand flash are subjected to bad block judgment in the data mode;
s04: judging whether the Nand flash finishes the bad block judgment under all the data modes, if so, skipping to S05, otherwise, skipping to S02;
s05: and marking all bad blocks in the Nand flash, thereby completing the marking of all bad blocks in the Nand flash.
3. The Nand flash automatic bad block marking method as claimed in claim 2, wherein said S03 specifically comprises the following steps:
s 31: carrying out full erase on the Nand flash and then carrying out full write-in data;
s 32: reading data written in one block in the Nand flash, judging whether the read data has errors or not, if so, jumping to s33, otherwise, jumping to s 34;
s 33: recording the bad block condition of the block, and jumping to s 34;
s 34: and judging whether all the blocks in the Nand flash finish the bad block judgment, if so, jumping to S04, and otherwise, jumping to S32.
4. The Nand flash automatic bad block marking method as claimed in claim 3, wherein in said s33, the bad block condition of said block is recorded by adding 1 to the bad block times of said block.
5. The method as claimed in claim 4, wherein in the S05, the marking of all bad blocks in the Nand flash is realized by marking all blocks with the bad block number greater than 0 in the Nand flash.
6. The utility model provides an automatic bad piece mark device of Nand flash memory, its characterized in that, the automatic bad piece mark device of Nand flash memory sets up in the PCB board of singlechip, packs the Nand flash into the PCB integrated circuit board of singlechip, includes:
the ID reading module is used for reading the ID of the Nand flash;
the searching module is used for searching all the blocks in the Nand flash for bad blocks in all the required data modes;
and the marking module marks a certain block as a bad block if the data reading error occurs in the certain data mode.
7. The Nand flash automatic bad block marking device of claim 6, wherein the Nand flash automatic bad block marking device is arranged in a PCB (printed Circuit Board) of an STM32 single chip microcomputer.
8. The Nand flash automatic bad block marking device as claimed in claim 6, wherein the marking module writes the address of the bad block into a Nand flash BBT.
9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 5.
10. A terminal device, characterized in that it comprises a processor and a memory, in which a computer program is stored, said processor being adapted to execute the method of any one of claims 1 to 5 by calling said computer program stored in said memory.
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| CN202011466653.0A CN112331252A (en) | 2020-12-14 | 2020-12-14 | Method and device for automatically marking bad blocks of Nand flash memory, storage medium and terminal |
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| CN202011466653.0A CN112331252A (en) | 2020-12-14 | 2020-12-14 | Method and device for automatically marking bad blocks of Nand flash memory, storage medium and terminal |
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Application publication date: 20210205 |