CN112542199B - Method, circuit, storage medium and terminal for detecting flash memory error - Google Patents
Method, circuit, storage medium and terminal for detecting flash memory error Download PDFInfo
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- CN112542199B CN112542199B CN202011614403.7A CN202011614403A CN112542199B CN 112542199 B CN112542199 B CN 112542199B CN 202011614403 A CN202011614403 A CN 202011614403A CN 112542199 B CN112542199 B CN 112542199B
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- 238000001514 detection method Methods 0.000 claims abstract description 30
- 238000012360 testing method Methods 0.000 claims abstract description 24
- 239000013256 coordination polymer Substances 0.000 claims abstract description 10
- 238000004590 computer program Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a method, a circuit, a storage medium and a terminal for detecting flash memory errors, wherein a special configuration signal is adopted in a CP test mode, so that a flash to be tested can write fixed data by using a normal write instruction in the test mode, then the read instruction in the test mode reads the data while comparing the data, a mark signal of a comparison result is output, and meanwhile, an error address is stored, and a damaged area can be replaced by a redundant storage area when the flash to be tested is powered on next time; the flash to be tested is not required to be written into and read out from the whole chip, and the storage area incapable of being erased and written in the chip can be determined while testing in the test process, so that the detection efficiency of flash storage errors is greatly improved, and redundancy replacement is realized; by adopting the scheme, the flash yield can be effectively improved, the production cost is reduced, and the chip which cannot be erased and the storage area which cannot be erased in the chip can be rapidly detected in the CP test stage.
Description
Technical Field
The invention relates to the technical field of flash detection, in particular to a method, a circuit, a storage medium and a terminal for detecting flash storage errors.
Background
Because domestic flash technology is not perfect, when the flash leaves the factory, a part of memory area circuits with partial probability flash cannot be successfully erased, and in order to improve the yield and reliability of the flash, a redundant memory area (redundancy) of the flash is generally used for replacing the area which cannot be successfully erased.
However, before replacement, the position of the area where the flash cannot be erased is required to be detected, the whole flash is erased, then the data of the whole flash is read, then the data is compared, so that the address of the area where the error data is located is determined, then the position of the area where the flash cannot be erased is known, and then the redundant storage area (redundancy) of the flash is used for replacing the area, but the operation efficiency is too low, and the method is not suitable for large-scale test and is not suitable for CP test (wafer test).
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
The invention aims to provide a method, a circuit, a storage medium and a terminal for detecting flash storage errors, and aims to solve the problems that the operation efficiency is low and the method is not suitable for CP test due to the fact that the whole piece of written data is needed and the whole piece of read data is compared when the existing flash is subjected to redundancy replacement.
The technical scheme of the invention is as follows: a method for detecting flash memory errors specifically comprises the following steps:
configuration detection enabling, configuration selection information and setting contrast data;
opening detection enabling;
receiving a write instruction, and writing setting data into corresponding storage units of the flash to be tested according to configuration selection information;
receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to configuration selection information;
comparing whether the read data is consistent with the comparison data, if so, ending the flash detection,
if the comparison result is inconsistent, storing the comparison result, and outputting a storage unit error mark;
and receiving a write configuration instruction, and writing the comparison result into a corresponding storage unit of the flash to be tested.
The method for detecting the flash memory error comprises the steps of enabling a write instruction, enabling a read instruction and enabling a write configuration instruction.
The method for detecting the flash memory error comprises the steps of writing command configuration selection information, reading command configuration selection information and writing command configuration selection information.
According to the method for detecting the flash memory errors, the set data written into the corresponding memory cells of the flash to be detected are all 0 or all F data.
A circuit for detecting flash memory errors, comprising:
the configuration module is used for configuring detection enabling, configuration selection information and setting comparison data, storing the comparison result and opening the detection enabling;
the write instruction module writes the setting data into the corresponding storage unit of the flash to be tested according to the configuration selection information;
the read instruction module reads data written in a corresponding storage unit of the flash to be tested according to the configuration selection information;
a comparison module for comparing whether the read data is consistent with the comparison data and outputting a storage unit error mark;
and the write configuration instruction module writes the comparison result into a corresponding storage unit of the flash to be tested.
The circuit for detecting flash memory errors is characterized in that the configuration module adopts a circuit composed of LATCH.
The circuit for detecting the flash memory error further comprises a receiving and outputting module, wherein the receiving and outputting module is used for receiving a writing instruction, a reading instruction, a writing configuration instruction and outputting a memory unit error mark.
The circuit for detecting flash memory errors is characterized in that the receiving and outputting module is realized by an IO interface.
A storage medium having a computer program stored therein, which when run on a computer causes the computer to perform the method of any of the preceding claims.
A terminal comprising a processor and a memory, the memory having stored therein a computer program for executing the method of any of the above by invoking the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a method, a circuit, a storage medium and a terminal for detecting the storage error of a flash, wherein a special configuration signal is adopted in a CP test mode, so that the flash to be tested can write fixed data by using a normal write instruction in the test mode, then the read instruction in the test mode reads the data while comparing the data, a mark signal of a comparison result is output, and meanwhile, an error address is stored, and a damaged area can be replaced by a redundant storage area when the flash to be tested is powered on next time; the flash to be tested is not required to be written into and read out from the whole chip, and the storage area incapable of being erased and written in the chip can be determined while testing during testing, so that the detection efficiency of flash storage errors is greatly improved, and redundant replacement is realized; by adopting the technical scheme, the flash yield can be effectively improved, the production cost is reduced, and the chip which cannot be erased and the storage area which cannot be erased in the chip can be rapidly detected in the CP test stage.
Drawings
Fig. 1 is a flowchart of the steps of a method for detecting a flash memory error in the present invention.
Fig. 2 is a schematic diagram of a circuit for detecting flash memory errors in the present invention.
Fig. 3 is a schematic diagram of a terminal in the present invention.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
As shown in FIG. 1, the method for detecting the flash memory error specifically comprises the following steps:
s1: configuration detection enabling, configuration selection information and setting contrast data;
s2: opening detection enabling;
s3: receiving a write instruction, and writing setting data into corresponding storage units of the flash to be tested according to configuration selection information;
s4: receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to configuration selection information;
s5: comparing whether the read data is consistent with the comparison data, if not, jumping to S6, and if so, jumping to S8;
s6: storing the comparison result and outputting a storage unit error mark;
s7: receiving a write configuration instruction, and writing the comparison result into a corresponding storage unit of the flash to be tested;
s8: and (5) finishing flash detection.
And writing the comparison result into the corresponding storage unit of the flash to be tested, and reading the replacement information when the flash chip reads the configuration information (namely the comparison result) in the corresponding storage unit when the flash is powered on next time, so that the redundant storage unit can be used for replacing the wrong storage unit.
By adopting the method, a special configuration signal is adopted in a CP test mode, so that the flash to be tested can write fixed data by using a normal write instruction in the test mode, then the read instruction in the test mode reads the data and compares the data, a mark signal of a comparison result is output, and meanwhile, an error address is stored, and a damaged area can be replaced by a redundant storage area (redundancy) when the flash to be tested is powered on next time; the flash to be tested is not required to be written into and read out from the whole chip, and the storage area incapable of being erased and written in the chip can be determined while testing during testing, so that the detection efficiency of flash storage errors is greatly improved, and redundant replacement is realized; by adopting the technical scheme, the flash yield can be effectively improved, the production cost is reduced, and the chip which cannot be erased and the storage area which cannot be erased in the chip can be rapidly detected in the CP test stage.
In some embodiments, the detection enables include write instruction enable, read instruction enable, and write configuration instruction enable.
In some embodiments, the configuration selection information includes write command configuration selection information, read command configuration selection information, and write command configuration selection information.
In some embodiments, in order to facilitate comparison, the setting data written into the corresponding storage unit of the flash to be tested may be all 0 or all F data.
As shown in fig. 2, a circuit for detecting a flash memory error includes:
the configuration module 101 is used for configuring detection enabling, configuration selection information and setting comparison data, storing the comparison result and opening the detection enabling;
the write instruction module 102 writes the setting data into the corresponding storage unit of the flash to be tested according to the configuration selection information;
the read instruction module 103 reads data written in a corresponding storage unit of the flash to be tested according to the configuration selection information;
a comparison module 104 for comparing whether the read data is consistent with the comparison data and outputting a memory cell error flag;
and the write configuration instruction module 105 writes the comparison result into a corresponding storage unit of the flash to be tested.
In some embodiments, the configuration module 101 employs a circuit consisting of LATCH.
In some embodiments, the circuit for detecting a flash memory error further includes a receiving and outputting module 106, configured to receive a write command, a read command, a write configuration command, and output a memory cell error flag.
In some embodiments, the receiving output module 106 is implemented using an IO interface.
The specific action process of the circuit for detecting flash memory errors is as follows: the configuration module 101 is a circuit composed of LATCH, which performs parameter configuration and enable configuration on the write command module 102 and the read command module 103, and also performs enable configuration on the write configuration command module 105. When the detection is enabled to be opened and a write instruction is sent through the IO interface, the write instruction module 102 sends configuration selection information provided by the configuration module 101 to select whether the data written into the storage unit is all 0 or all F, after the operation of writing the flash to be tested is completed, a read instruction is sent through the IO interface, the read instruction module 103 sends configuration selection information provided by the configuration module 101 to read out the data written into the corresponding storage unit of the flash to be tested, meanwhile, the comparison module 104 is enabled, the data read out by the flash to be tested is compared with the comparison data to find out error data, meanwhile, the detection result (error information/replacement data) is written into the corresponding LATCH through the configuration module 101, the IO interface is waited to send the write configuration instruction, and meanwhile, the error mark is output to the IO interface by the comparison module 104, so that a tester can know whether an error occurs or not; sending a write configuration instruction through the IO interface, and writing a detection result (error information/replacement data) in the configuration module 101 into a corresponding storage unit of the flash to be tested by the write configuration instruction module 105; when the flash to be tested is powered on next time, the chip reads the configuration information of the memory cell, reads the replacement information, and replaces the wrong memory cell with the redundant memory cell.
Referring to fig. 3, the embodiment of the invention further provides a terminal. As shown, terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling computer programs stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to the processes of one or more computer programs into the memory 302 according to the following steps, and the processor 301 executes the computer programs stored in the memory 302, so as to implement various functions: configuration detection enabling, configuration selection information and setting contrast data; opening detection enabling; receiving a write instruction, and writing setting data into corresponding storage units of the flash to be tested according to configuration selection information; receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to configuration selection information; comparing whether the read data is consistent with the comparison data, if so, ending the flash detection, and if not, storing the comparison result and outputting a storage unit error mark; and receiving a write configuration instruction, and writing the comparison result into a corresponding storage unit of the flash to be tested.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs that include instructions that are executable in a processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
The present application provides a storage medium, which when executed by a processor, performs the method in any of the alternative implementations of the above embodiments to implement the following functions: configuration detection enabling, configuration selection information and setting contrast data; opening detection enabling; receiving a write instruction, and writing setting data into corresponding storage units of the flash to be tested according to configuration selection information; receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to configuration selection information; comparing whether the read data is consistent with the comparison data, if so, ending the flash detection, and if not, storing the comparison result and outputting a storage unit error mark; and receiving a write configuration instruction, and writing the comparison result into a corresponding storage unit of the flash to be tested. The storage medium may be implemented by any type of volatile or nonvolatile Memory device or combination thereof, such as static random access Memory (Static Random Access Memory, SRAM), electrically erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), erasable Programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), programmable Read-Only Memory (PROM), read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic disk, or optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (10)
1. The method for detecting the flash memory error is characterized by comprising the following steps:
in the CP test mode, configuring detection enabling, configuring selection information and setting contrast data;
opening detection enabling;
receiving a write instruction, and writing setting data into corresponding storage units of the flash to be tested according to configuration selection information;
receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to configuration selection information;
comparing whether the read data is consistent with the comparison data, if so, ending the flash detection,
if the comparison result is inconsistent, storing the comparison result, and outputting a storage unit error mark;
receiving a configuration writing instruction, and writing a comparison result into a corresponding storage unit of the flash to be tested, wherein the comparison result is configuration information in the corresponding storage unit of the flash to be tested;
when the flash is powered on next time, the flash chip reads the comparison result in the corresponding storage unit, reads out the replacement information, and replaces the wrong storage unit with the redundant storage unit.
2. The method of detecting a flash memory error of claim 1, wherein the detection enabling comprises write command enabling, read command enabling, and write configuration command enabling.
3. The method for detecting a flash memory error according to claim 1, wherein the configuration selection information includes write command configuration selection information, read command configuration selection information, and write command configuration selection information.
4. The method for detecting a flash memory error according to claim 1, wherein the setting data written into the corresponding memory cell of the flash to be detected is data of all 0 or all F.
5. A circuit for detecting flash memory errors, comprising:
the configuration module is used for configuring detection enabling, configuring selection information and setting comparison data in a CP test mode, storing the comparison result and opening the detection enabling;
the write instruction module writes the setting data into the corresponding storage unit of the flash to be tested according to the configuration selection information;
the read instruction module reads data written in a corresponding storage unit of the flash to be tested according to the configuration selection information;
a comparison module for comparing whether the read data is consistent with the comparison data and outputting a storage unit error mark;
the configuration instruction writing module writes the comparison result into the corresponding storage unit of the flash to be tested, wherein the comparison result is configuration information in the corresponding storage unit of the flash to be tested;
when the flash is powered on next time, the flash chip reads the comparison result in the corresponding storage unit, reads out the replacement information, and replaces the wrong storage unit with the redundant storage unit.
6. The circuit for detecting flash memory errors according to claim 5, wherein the configuration module employs a circuit consisting of LATCH.
7. The circuit for detecting a flash memory error as in claim 5, further comprising a receive output module for receiving a write command, a read command, a write configuration command, and outputting a memory cell error flag.
8. The circuit for detecting flash memory errors according to claim 7, wherein the receiving output module is implemented by an IO interface.
9. A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform the method of any of claims 1 to 4.
10. A terminal comprising a processor and a memory, said memory having stored therein a computer program for executing the method of any of claims 1 to 4 by invoking said computer program stored in said memory.
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| CN114267402B (en) * | 2021-11-22 | 2022-11-18 | 上海芯存天下电子科技有限公司 | Bad storage unit testing method, device, equipment and storage medium of flash memory |
| CN116504296A (en) * | 2022-01-19 | 2023-07-28 | 长鑫存储技术有限公司 | Method and device for testing memory chip |
| CN116504293B (en) * | 2023-06-27 | 2023-10-13 | 芯天下技术股份有限公司 | Method and device for reading non flash, memory chip and equipment |
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