CN111221693A - Verification method, system, device and storage medium for NOR flash configuration module - Google Patents
Verification method, system, device and storage medium for NOR flash configuration module Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
Abstract
The invention relates to the field of semiconductor testing, in particular to a verification method for a NOR flash configuration module, which comprises the steps of generating a config sequence and a flash sequence, extracting a config excitation data packet from the config sequence based on an instruction, and extracting a flash excitation data packet from the flash sequence; firstly, performing first simulation operation by using the config excitation data packet and the flash excitation data packet to output a first simulation result; injecting the comparison model, and performing a second simulation operation to output a second simulation result; and finally comparing the first simulation result with the second simulation result, if the comparison is correct, ending the simulation, and if the comparison is wrong, ending the error counting simulation. By designing the config sequence, configuration values meeting requirements can be randomly generated according to different algorithm stages and simulation modes, the verification space is enlarged, and the completeness of verification is improved; based on the comparison model, the second simulation result serving as the comparison reference can be accurately output, the first simulation result and the second simulation result are automatically compared, and the verification accuracy and the verification efficiency are improved.
Description
Technical Field
The invention relates to the field of semiconductor testing, in particular to a verification method, a verification system, a verification device and a verification storage medium for a NOR flash configuration module.
Background
The NOR flash configuration module has independent storage space in the flash chip, and the configuration values are different according to different flash capacities and functions. The module is responsible for chip power-on configuration, read-write algorithm mode selection, mode configuration, analog circuit voltage and current selection and the like, is used as a basic functional module of the flash chip, runs through the whole chip verification period, and plays a vital role in the chip verification period.
At present, the verification of the NOR flash configuration module mainly adopts the mode of manually setting a single configuration value, manually checking a verification result or semi-automatically comparing the verification result. However, the application scenario and the configuration module are increasingly complex in function, the verification method needs to occupy a large amount of project time, the completeness of verification is difficult to ensure, and the problems of low verification speed and low verification reliability occur.
Disclosure of Invention
In view of the above shortcomings in the prior art, the present invention is directed to provide a method, a system, a device and a storage medium for verifying a NOR flash configuration module, and aims to solve the problems of slow verification speed and low verification reliability of the existing NOR flash configuration module verification scheme.
The technical scheme adopted by the invention for solving the technical problems is as follows: the first aspect provides a verification method for a NOR flash configuration module, comprising the following steps:
the method comprises the following steps: generating a config sequence and a flash sequence based on the instruction, extracting a config excitation data packet from the config sequence, and extracting a flash excitation data packet from the flash sequence; performing first simulation operation by using the config excitation data packet and the flash excitation data packet to output a first simulation result; injecting a comparison model, and performing second simulation operation by using the config excitation data packet and the flash excitation data packet to output a second simulation result; and comparing the first simulation result with the second simulation result, if the comparison is correct, ending the simulation, and if the comparison is wrong, ending the error counting simulation.
Further, the alignment model is a System Verilog reference model.
Further, error statistics are performed using Perl scripts.
Further, a spi protocol is adopted to extract a flash excitation data packet from the flash sequence.
Further, the second simulation operation realizes the Nor flash internal algorithm function.
Further, the config excitation data packet comprises power-on configuration, read-write algorithm flow selection, mode configuration, voltage and current.
Further, the flash incentive data packet comprises a user instruction and a user operation mode.
In a second aspect, the present invention further provides a verification system for a NOR flash configuration module, comprising:
the method comprises the following steps: the data acquisition module is used for generating a config sequence and a flash sequence based on the instruction, extracting a config excitation data packet from the config sequence and extracting a flash excitation data packet from the flash sequence; the first simulation module is used for carrying out first simulation operation by utilizing the config excitation data packet and the flash excitation data packet so as to output a first simulation result; the second simulation module is used for injecting a comparison model, and performing second simulation operation by using the config excitation data packet and the flash excitation data packet to output a second simulation result; and the comparison module is used for comparing the first simulation result with the second simulation result, if the comparison is correct, the simulation is finished, and if the comparison is wrong, the error statistics simulation is finished.
In a third aspect, the present invention provides a computer apparatus, comprising a processor, wherein the processor is configured to execute a computer program stored in a memory to implement the NOR flash configuration module verification method according to any of the first aspect.
In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, wherein a processor is configured to execute the computer program stored in the storage medium to implement the NOR flash configuration module verification method according to any of the first aspect.
Has the advantages that: the invention provides a verification method for a NOR flash configuration module, which comprises the steps of generating a config sequence and a flash sequence, extracting a config excitation data packet from the config sequence based on an instruction, and extracting a flash excitation data packet from the flash sequence; performing first simulation operation by using the config excitation data packet and the flash excitation data packet to output a first simulation result; injecting a comparison model, and performing second simulation operation by using the config excitation data packet and the flash excitation data packet to output a second simulation result; and comparing the first simulation result with the second simulation result, if the comparison is correct, ending the simulation, and if the comparison is wrong, ending the error counting simulation. The verification method is developed based on a UVM verification methodology, and is convenient to transplant and redevelop; by designing the config sequence, configuration values meeting requirements can be randomly generated according to different algorithm stages and simulation modes, the verification space is enlarged, and the completeness of verification is improved; based on the comparison model, a second simulation result serving as a comparison reference can be accurately output, and the first simulation result and the second simulation result output through the first simulation operation are automatically compared, so that the verification accuracy and the verification efficiency are improved.
Description of the drawings
FIG. 1 is a flow chart of a method for verifying a NOR flash configuration module according to the present invention;
FIG. 2 is a schematic diagram of a NOR flash configuration module verification system according to the present invention;
FIG. 3 is a schematic diagram of an exemplary verification system for a NOR flash configuration module according to the present invention.
Detailed Description
The invention provides a verification method for a NOR flash configuration module, which is further detailed below in order to make the purpose, technical scheme and effect of the invention clearer and clearer. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that config is a module of a memory chip, and is a configuration, and belongs to a single storage area (different from a user data storage area) of an analog circuit part of the memory chip, data cannot be lost (non-volatile characteristic) after power failure, and the config data is read out first and sent to a digital part of the chip (because the digital circuit has a volatile characteristic, data is lost after power failure, and the config is read every time power is turned on) when the chip is powered on, and the digital circuit configures a digital code threshold value by using the read config data configuration information, configures a read-write-erase algorithm realized by digital, and the like. The flash sequence mainly refers to user instructions, data writing and data reading of a user and the like, and before a flash excitation data packet is sent and received, a chip must complete a power-on process, namely a config sequence is read from an analog circuit to a digital circuit.
From the verification point of view, a config excitation data packet needs to be sent to a tested code, and actually, a chip analog circuit part receives and stores the config excitation data packet. And then sending a flash excitation data packet, for example, writing operation including a writing instruction, a writing address, writing data and the like, starting a writing algorithm after the digital circuit identifies the instruction, writing the data into a storage area appointed by the analog circuit, and finishing the operation.
In a first aspect, please refer to fig. 1, which is a flowchart of a verification method for a NOR flash configuration module disclosed in this embodiment, including the steps of:
s100, generating a config sequence and a flash sequence, extracting a config excitation data packet from the config sequence based on the instruction, and extracting a flash excitation data packet from the flash sequence.
In this embodiment, a config sequence and a flash sequence are generated first, where the two sequences correspond to two data pools; and then, a config excitation data packet and a flash excitation data packet are respectively extracted according to the instruction, namely the constraint condition of the user, and the data is transmitted in a packet form, so that the simulation efficiency and the portability are high.
The constraint condition is that a specific or specific range configuration value is set according to the purpose of the test case, and is respectively called directional verification and random verification, and after the constraint condition is added, a config data packet is generated according to new constraint. For example, if the H8btel4byte random range is 0 or 1, the configuration value for configuring the amount of write-once data in the config packet is constrained, and each time the emulation randomly selects to write 8 bytes of data at a time or to write 4 bytes of data at a time, the configuration is valid before the config packet is re-read.
S200, performing first simulation operation by using the config excitation data packet and the flash excitation data packet to output a first simulation result.
In this embodiment, the length of the config excitation data packet is fixed, and includes configuration information such as power-on configuration, read-write-erase algorithm mode selection, mode configuration, voltage and current, and the format of the config excitation data packet for performing the first simulation operation is specific, it should be noted that the config excitation data packet is in units of bytes, and each byte, each bit or a plurality of bits have specific meanings, which are specifically determined by a project chip developer. Generally, the config excitation packet is divided into a header, a trailer, and an inter-packet. The packet head comprises complementary bit information (used for correcting errors of digital part config data, and re-reading the config data if errors occur), analog voltage, current and the like used for setting power-on reading config, the packet tail is memory chip ID (fixed data), and the size of data among packets is variable and used for configuring read-write-erase algorithms, operation modes and the like. And if the head and the tail of the packet are checked to be correct, the digital current receives the config data packet, otherwise, the config data packet is obtained again until the success. The format of the flash excitation data packet is fixed, the flash excitation data packet comprises user instructions such as reading, writing and erasing, user operation modes such as a user mode and a test mode, and the flash excitation data packet for performing the first simulation operation is extracted through an spi protocol.
The first simulation operation completes the power-on process, the digital circuit obtains config configuration data from the analog circuit part, and after the digital circuit completes the configuration operation, the digital circuit analyzes a user instruction and starts a corresponding algorithm to read, write or erase the analog storage circuit area. The first simulation result is usually read data of the memory circuit region, and the first simulation result is transmitted in a packet form to be compared. In real time, the simulation process is recorded in a log file.
S300, injecting a comparison model, and performing second simulation operation by using the config excitation data packet and the flash excitation data packet to output a second simulation result.
In this embodiment, an alignment model is injected, and the alignment model is preferably a System Verilog reference model. And the comparison model receives the config excitation data packet and the flash excitation data packet, realizes the Nor flash internal algorithm function, simulates the Norflash internal read, write, erase algorithm, read-write state register and other functions, and further outputs a second simulation result serving as the comparison standard.
The comparison model automatically completes the corresponding calculation process according to the configuration condition and the user instruction, obtains an accurate calculation result, and remarkably improves the verification and error checking efficiency.
S400, comparing the first simulation result with the second simulation result, if the comparison is correct, ending the simulation, and if the comparison is wrong, ending the error counting simulation.
In this embodiment, the first simulation result is compared byte by byte with the second simulation result as a comparison standard, and error information is accurately positioned and output for developers to debug problem codes. The error statistics uses Perl script to automatically search all case simulation log files, and statistics and collection of error information improve automation level.
The invention is applied to RTL (register transfer level) simulation verification, whether the digital code design function meets the design specification is verified in the chip design stage, the NORflash configuration module and the data module are independently designed, the function verification of the configuration module is enhanced, and the verification technology designed by the patent has more obvious effects on the aspects of verification completeness, verification efficiency and the like of the function point of the configuration module when the configuration function of the NOR flash chip is more complicated. The configuration module test excitation (generated by a config sequence) and the data module test excitation (generated by a flash sequence) have strong flexibility, and support various verification scenes such as random and directional tests. The System Verilog comparison model completes simulation modeling of the NOR flash configuration module and the data module, can accurately calculate a simulation result aiming at input excitation data, reflects algorithm flow information in a chip, compares the simulation result with a digital design code, and can effectively save time cost, labor cost and errors caused by artificial inspection in the aspects of simulation instantaneity, accuracy and the like.
In a second aspect, there is provided a NOR flash configuration module authentication apparatus, the apparatus including:
the data acquisition module 10 is configured to generate a config sequence and a flash sequence based on the instruction, extract a config excitation data packet from the config sequence, and extract a flash excitation data packet from the flash sequence;
the first simulation module 20, which utilizes the config excitation data packet and the flash excitation data packet to perform a first simulation operation to output a first simulation result;
the second simulation module 30 is configured to inject a comparison model, and perform a second simulation operation by using the config excitation data packet and the flash excitation data packet to output a second simulation result;
and the comparison module 40 is used for comparing the first simulation result with the second simulation result, if the comparison is correct, the simulation is finished, and if the comparison is wrong, the error statistics simulation is finished.
Referring to fig. 3, an example of the NOR flash configuration module verification apparatus includes a config sequence, a flash sequence, a code block to be tested, a first input unit, a second input unit, an alignment model, and an alignment unit.
The first input unit comprises a config sequence generator and a config driving unit, wherein the config sequence is connected with the config sequence generator, and the config driving unit is connected with the code block to be tested; the second input unit comprises a flash sequence generator, a flash driving unit and an input monitoring unit, wherein the flash sequence generator is connected with the flash sequence generator, the flash sequence generator is connected with the flash driving unit, the flash driving unit is connected with the code block to be tested, and the input monitoring unit is connected with the comparison model; the output unit comprises an output monitoring unit, the output monitoring unit is connected with the tested code block, and the output monitoring unit is connected with the comparison unit.
The code block under test comprises logic codes simulating circuit functions and digital codes under test. The logic code of the analog circuit function comprises a storage circuit control logic and a storage area function, is compiled based on System Verilog, is used for simulating the behavior of the analog circuit, and is matched with the simulation of the digital code, and the simulation of the digital code to be tested is carried out; the digital code to be tested is a verified object, and the digital code mainly comprises functions of instruction analysis of a memory chip, algorithm implementation, function scheduling and the like.
The automatic verification system of the NOR flash configuration module has the following specific working process:
the config sequence generator extracts a corresponding config excitation data packet (fixed packet length) from the generated config sequence based on the instruction, and sends the corresponding config excitation data packet to the first driving unit, wherein the config excitation data packet with the fixed packet length comprises configuration information such as power-on configuration, read-write algorithm mode selection, mode configuration, voltage, current and the like. According to the time sequence requirement of the code block to be tested, the first driving unit sends the data packet to the code block to be tested according to the specific format, and the first monitoring unit acquires the config data packet sent to the config driving unit, detects the data packet and sends the data packet to the comparison unit.
The flash sequence generator extracts a corresponding flash excitation data packet (with a fixed format) from a generated flash sequence based on an instruction and sends the flash excitation data packet to the second driving unit, the flash excitation data packet with the fixed format comprises user instructions such as reading, writing and erasing, user operation modes such as a user mode and a test mode, and the flash driving unit sends the flash data packet to a code block to be tested according to the spi time sequence requirement of the code block to be tested (and sends the flash excitation data after the config excitation data is sent). Meanwhile, the input monitoring unit acquires a config excitation data packet and a flash excitation data packet from the input interface of the tested code and sends the config excitation data packet and the flash excitation data packet to the comparison model for processing.
And the output monitoring unit is used for acquiring an output result from the tested code output interface, finishing data extraction according to the spi protocol requirement, and packaging and sending the data to the comparison unit.
The comparison model simulates the functions of an Nor flash internal read, write, erase algorithm, a read-write state register and the like, receives config and flash excitation data packets, completes corresponding operation processing, outputs results, packs and sends the results to the comparison unit. The comparison model automatically completes the corresponding calculation process according to the configuration condition and the user instruction, obtains an accurate calculation result, and has the advantages of obviously improving the verification and error checking efficiency.
The comparison unit is used for collecting comparison tested code output results A and comparison model calculation results B, comparing the data packets A and B one by one in byte mode, accurately positioning and outputting error information for developers to debug problem codes. The script program for statistics automatically retrieves all case simulation log files, and statistics and collection of error information improve the automation level.
In a third aspect, there is provided a computer apparatus comprising a processor for executing a computer program stored in a memory, thereby implementing the method of:
generating a config sequence and a flash sequence, extracting a config excitation data packet from the config sequence based on the instruction, and extracting a flash excitation data packet from the flash sequence; performing first simulation operation by using the config excitation data packet and the flash excitation data packet to output a first simulation result; injecting a comparison model, and performing second simulation operation by using the config excitation data packet and the flash excitation data packet to output a second simulation result; and comparing the first simulation result with the second simulation result, if the comparison is correct, ending the simulation, and if the comparison is wrong, ending the error counting simulation.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. The computer processor is used to execute a computer program stored in a storage medium to implement the following method:
generating a config sequence and a flash sequence, extracting a config excitation data packet from the config sequence based on the instruction, and extracting a flash excitation data packet from the flash sequence; performing first simulation operation by using the config excitation data packet and the flash excitation data packet to output a first simulation result; injecting a comparison model, and performing second simulation operation by using the config excitation data packet and the flash excitation data packet to output a second simulation result; and comparing the first simulation result with the second simulation result, if the comparison is correct, ending the simulation, and if the comparison is wrong, ending the error counting simulation.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A verification method for a NOR flash configuration module is characterized by comprising the following steps:
generating a config sequence and a flash sequence, extracting a config excitation data packet from the config sequence based on the instruction, and extracting a flash excitation data packet from the flash sequence;
performing first simulation operation by using the config excitation data packet and the flash excitation data packet to output a first simulation result;
injecting a comparison model, and performing second simulation operation by using the config excitation data packet and the flash excitation data packet to output a second simulation result;
and comparing the first simulation result with the second simulation result, if the comparison is correct, ending the simulation, and if the comparison is wrong, ending the error counting simulation.
2. The method for validating a NOR flash configuration module as claimed in claim 1, wherein the comparison model is a System Verilog reference model.
3. The NOR flash configuration module authentication method of claim 1, wherein the error statistics are performed using a Perl script.
4. The method for validating a NOR flash configuration module of claim 1 wherein the spi protocol is used to extract the flash stimulus packets from the flash sequence.
5. The NOR flash configuration module verification method of claim 1, wherein the second emulation operation implements NOR flash internal algorithm functions.
6. The method of claim 1, wherein the config excitation packet comprises a power-on configuration, a read-write-erase algorithm flow selection, a mode configuration, a voltage and a current.
7. The NOR flash configuration module authentication method of claim 1, wherein the flash stimulus packet comprises a user command and a user operation mode.
8. A NOR flash configuration module verification system, comprising:
the data acquisition module is used for generating a config sequence and a flash sequence based on the instruction, extracting a config excitation data packet from the config sequence and extracting a flash excitation data packet from the flash sequence;
the first simulation module is used for carrying out first simulation operation by utilizing the config excitation data packet and the flash excitation data packet so as to output a first simulation result;
the second simulation module is used for injecting a comparison model, and performing second simulation operation by using the config excitation data packet and the flash excitation data packet to output a second simulation result;
and the comparison module is used for comparing the first simulation result with the second simulation result, if the comparison is correct, the simulation is finished, and if the comparison is wrong, the error statistics simulation is finished.
9. A computer arrangement comprising a processor for executing a computer program stored in a memory to implement the NOR flash configuration module authentication method of any of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that a processor is configured to execute the computer program stored in the storage medium to implement the NOR flash configuration module authentication method according to any one of claims 1 to 7.
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| CN112560378A (en) * | 2020-12-23 | 2021-03-26 | 苏州易行电子科技有限公司 | Be applied to automation platform of integrating complete chip development flow |
| CN112560378B (en) * | 2020-12-23 | 2023-03-24 | 苏州易行电子科技有限公司 | Be applied to automation platform of integrating complete chip development flow |
| CN112464502A (en) * | 2020-12-28 | 2021-03-09 | 深圳市芯天下技术有限公司 | Optimization and acceleration memory simulation verification method and device, storage medium and terminal |
| CN112464502B (en) * | 2020-12-28 | 2022-02-01 | 芯天下技术股份有限公司 | Optimization and acceleration memory simulation verification method and device, storage medium and terminal |
| CN112542199A (en) * | 2020-12-30 | 2021-03-23 | 深圳市芯天下技术有限公司 | Method, circuit, storage medium and terminal for detecting flash storage error |
| CN112542199B (en) * | 2020-12-30 | 2024-04-12 | 芯天下技术股份有限公司 | Method, circuit, storage medium and terminal for detecting flash memory error |
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