CN112542199A - Method, circuit, storage medium and terminal for detecting flash storage error - Google Patents
Method, circuit, storage medium and terminal for detecting flash storage error Download PDFInfo
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- CN112542199A CN112542199A CN202011614403.7A CN202011614403A CN112542199A CN 112542199 A CN112542199 A CN 112542199A CN 202011614403 A CN202011614403 A CN 202011614403A CN 112542199 A CN112542199 A CN 112542199A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000001514 detection method Methods 0.000 claims abstract description 31
- 238000004590 computer program Methods 0.000 claims description 14
- 238000012360 testing method Methods 0.000 abstract description 19
- 239000013256 coordination polymer Substances 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000009471 action Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
Abstract
The invention discloses a method, a circuit, a storage medium and a terminal for detecting flash storage errors.A special configuration signal is adopted in a CP test mode, so that a flash to be detected can write fixed data by using a normal write instruction in the test mode, then the data is read and compared by using a read instruction in the test mode, a mark signal of a comparison result is output, an error address is stored at the same time, and a damaged area can be replaced by a redundant storage area when the flash to be detected is electrified for the next time; the flash to be tested is not required to be written in a whole piece and read out in a whole piece, the memory area which cannot be erased and written in the chip can be determined while testing, the detection efficiency of flash memory errors is greatly improved, and redundancy replacement is realized; by adopting the scheme, the flash yield can be effectively improved, the production cost is reduced, and the chip which cannot be erased and written and the storage area which cannot be erased and written in the chip can be quickly detected in the CP test stage.
Description
Technical Field
The invention relates to the technical field of flash detection, in particular to a method, a circuit, a storage medium and a terminal for detecting flash storage errors.
Background
Because the domestic flash technology is not perfect, when the flash leaves a factory, a part of storage area circuits of the flash with partial probability cannot be successfully erased and written, and in order to improve the yield and reliability of the flash, a redundant storage area (redundancy) of the flash is generally used for replacing an area which cannot be successfully erased and written.
However, before replacement, the position of the area where the flash cannot be erased needs to be detected, the conventional method is to erase the whole flash, then read the data of the whole flash, and then compare the data, so as to determine the address where the wrong data is located, then know the position of the area where the flash cannot be erased, and then replace the part of the area by using a redundant storage area (redundancy) of the flash, but the operation efficiency is too low, and the method is not suitable for large-scale testing and is not suitable for CP testing (wafer testing).
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a method, a circuit, a storage medium and a terminal for detecting flash storage errors, and aims to solve the problems that the operation efficiency is low and the method is not suitable for CP test due to the fact that data needs to be written in a whole piece and then read out and compared in a whole piece when the existing flash carries out redundancy replacement.
The technical scheme of the invention is as follows: a method for detecting flash memory errors specifically comprises the following steps:
configuring detection enable, configuration selection information and setting comparison data;
turning on a detection enable;
receiving a write instruction, and writing the set data into a corresponding storage unit of the flash to be tested according to the configuration selection information;
receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to the configuration selection information;
comparing the read data with the comparison data to determine whether they are consistent, if so, ending the flash detection,
if the comparison result is inconsistent with the error flag, storing the comparison result and outputting the error flag of the storage unit;
and receiving a write configuration instruction, and writing the comparison result into a corresponding storage unit of the flash to be tested.
The method for detecting the flash memory error comprises the following steps of enabling a write instruction, enabling a read instruction and enabling a write configuration instruction.
The method for detecting the flash memory error comprises the steps that configuration selection information comprises write instruction configuration selection information, read instruction configuration selection information and write configuration instruction configuration selection information.
The method for detecting the flash storage error comprises the step of writing set data in a corresponding storage unit of the flash to be detected into all 0 or all F data.
A circuit for detecting flash memory errors, comprising:
the configuration module is used for configuring detection enable, configuration selection information and setting comparison data, storing a comparison result and opening the detection enable;
the write instruction module writes the set data into a corresponding storage unit of the flash to be tested according to the configuration selection information;
the read instruction module reads data written in a corresponding storage unit of the flash to be tested according to the configuration selection information;
the comparison module compares whether the read data is consistent with the comparison data or not and outputs a storage unit error mark;
and the write configuration instruction module writes the comparison result into a corresponding storage unit of the flash to be tested.
The circuit for detecting flash memory errors is characterized in that the configuration module adopts a circuit composed of LATCHs.
The circuit for detecting the flash memory error further comprises a receiving and outputting module, wherein the receiving and outputting module is used for receiving a writing instruction, a reading instruction, a writing configuration instruction and outputting a storage unit error mark.
The circuit for detecting the flash memory error is characterized in that the receiving and outputting module is realized by adopting an IO interface.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform any of the methods described above.
A terminal comprising a processor and a memory, the memory having stored therein a computer program, the processor being adapted to perform the method of any preceding claim by invoking the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a method, a circuit, a storage medium and a terminal for detecting flash storage errors, wherein a special configuration signal is adopted in a CP test mode, so that a flash to be detected can write fixed data by using a normal write instruction in the test mode, then the data is read and compared by using a read instruction in the test mode, a mark signal of a comparison result is output, an error address is stored at the same time, and a damaged area can be replaced by a redundant storage area when the flash to be detected is electrified next time; the flash to be tested is not required to be written in a whole piece and read out in a whole piece, the memory area which cannot be erased and written in the chip can be determined while testing, the detection efficiency of flash memory errors is greatly improved, and redundancy replacement is realized; by adopting the technical scheme, the yield of the flash can be effectively improved, the production cost is reduced, and the erasable chips and the erasable storage areas in the chips can be quickly detected in the CP test stage.
Drawings
FIG. 1 is a flow chart of steps of a method for detecting flash memory errors in the present invention.
FIG. 2 is a schematic diagram of a circuit for detecting flash memory errors in the present invention.
Fig. 3 is a schematic diagram of a terminal in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, a method for detecting a flash memory error specifically includes the following steps:
s1: configuring detection enable, configuration selection information and setting comparison data;
s2: turning on a detection enable;
s3: receiving a write instruction, and writing the set data into a corresponding storage unit of the flash to be tested according to the configuration selection information;
s4: receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to the configuration selection information;
s5: comparing whether the read data is consistent with the comparison data, if not, jumping to S6, and if so, jumping to S8;
s6: storing the comparison result and outputting a storage unit error mark at the same time;
s7: receiving a write configuration instruction, and writing a comparison result into a corresponding storage unit of the flash to be tested;
s8: and finishing the flash detection.
By writing the comparison result into the corresponding storage unit of the flash to be tested, when the flash is powered on next time and the flash chip reads the configuration information (namely the comparison result) in the corresponding storage unit, the replacement information is read out, and the redundant storage unit can be used for replacing the wrong storage unit.
By adopting the method, a special configuration signal is adopted in a CP test mode, so that the flash to be tested can write fixed data by using a normal write instruction in the test mode, then the read instruction in the test mode reads the data and compares the data, a mark signal of a comparison result is output, an error address is stored at the same time, and a damaged area can be replaced by a redundant storage area (redundancy) when the flash to be tested is powered on next time; the flash to be tested is not required to be written in a whole piece and read out in a whole piece, the memory area which cannot be erased and written in the chip can be determined while testing, the detection efficiency of flash memory errors is greatly improved, and redundancy replacement is realized; by adopting the technical scheme, the yield of the flash can be effectively improved, the production cost is reduced, and the erasable chips and the erasable storage areas in the chips can be quickly detected in the CP test stage.
In some embodiments, the detection enable includes a write command enable, a read command enable, and a write configuration command enable.
In some embodiments, the configuration selection information includes write command configuration selection information, read command configuration selection information, and write configuration command configuration selection information.
In some embodiments, for the convenience of comparison, the setting data written into the corresponding storage unit of the flash to be tested may adopt data of all 0 s or all F s.
As shown in fig. 2, a circuit for detecting a flash memory error includes:
the configuration module 101 is used for configuring detection enable, configuration selection information and setting comparison data, storing a comparison result and opening the detection enable;
the write instruction module 102 writes the set data into a corresponding storage unit of the flash to be tested according to the configuration selection information;
the read instruction module 103 reads data written in a corresponding storage unit of the flash to be tested according to the configuration selection information;
a comparison module 104 for comparing the read data with the comparison data and outputting a storage unit error flag;
and the configuration writing instruction module 105 writes the comparison result into a corresponding storage unit of the flash to be tested.
In some embodiments, the configuration module 101 employs a circuit consisting of LATCH.
In some embodiments, the circuitry for detecting flash memory errors further comprises a receive output module 106 for receiving a write command, a read command, a write configure command, and outputting a memory cell error flag.
In some embodiments, the receiving and outputting module 106 is implemented by an IO interface.
The specific action process of the circuit for detecting the flash memory error is as follows: the configuration module 101 is a circuit composed of LATCH, and performs parameter configuration and enable configuration on the write command module 102 and the read command module 103, and also performs enable configuration on the write configuration command module 105. When the detection enable is turned on and a write instruction is sent through the IO interface, the write instruction module 102 sends a read instruction through the IO interface according to the configuration selection information provided by the configuration module 101, after the write operation of the flash to be detected is completed, the read instruction module 103 reads data written in the corresponding memory cell of the flash to be detected according to the configuration selection information provided by the configuration module 101, and simultaneously enables the comparison module 104 to compare the data read out by the flash to be detected with the comparison data, find out error data, and simultaneously write a detection result (error information/replacement data) into the corresponding LATCH through the configuration module 101, wait for the IO interface to send the write configuration instruction, and simultaneously output an error flag to the IO interface through the comparison module 104, enabling the tester to know whether an error has occurred; sending a write configuration instruction through the IO interface, and writing a detection result (error information/replacement data) in the configuration module 101 into a corresponding storage unit of the flash to be detected by the write configuration instruction module 105; and reading the replacement information when the chip reads the configuration information of the storage unit when the flash to be tested is powered on next time, and replacing the wrong storage unit by using the redundant storage unit.
Referring to fig. 3, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: configuring detection enable, configuration selection information and setting comparison data; turning on a detection enable; receiving a write instruction, and writing the set data into a corresponding storage unit of the flash to be tested according to the configuration selection information; receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to the configuration selection information; comparing whether the read data is consistent with the comparison data, if so, ending the flash detection, and if not, storing the comparison result and outputting a storage unit error mark; and receiving a write configuration instruction, and writing the comparison result into a corresponding storage unit of the flash to be tested.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: configuring detection enable, configuration selection information and setting comparison data; turning on a detection enable; receiving a write instruction, and writing the set data into a corresponding storage unit of the flash to be tested according to the configuration selection information; receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to the configuration selection information; comparing whether the read data is consistent with the comparison data, if so, ending the flash detection, and if not, storing the comparison result and outputting a storage unit error mark; and receiving a write configuration instruction, and writing the comparison result into a corresponding storage unit of the flash to be tested. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for detecting flash storage errors is characterized by comprising the following steps:
configuring detection enable, configuration selection information and setting comparison data;
turning on a detection enable;
receiving a write instruction, and writing the set data into a corresponding storage unit of the flash to be tested according to the configuration selection information;
receiving a reading instruction, and reading data written in a corresponding storage unit of the flash to be tested according to the configuration selection information;
comparing the read data with the comparison data to determine whether they are consistent, if so, ending the flash detection,
if the comparison result is inconsistent with the error flag, storing the comparison result and outputting the error flag of the storage unit;
and receiving a write configuration instruction, and writing the comparison result into a corresponding storage unit of the flash to be tested.
2. The method of claim 1, wherein the detection enable comprises a write instruction enable, a read instruction enable, and a write configuration instruction enable.
3. The method of claim 1, wherein the configuration selection information comprises write instruction configuration selection information, read instruction configuration selection information, and write configuration instruction configuration selection information.
4. The method according to claim 1, wherein the setting data written into the corresponding memory cell of the flash to be tested is data of all 0 s or all F s.
5. A circuit for detecting flash memory errors, comprising:
the configuration module is used for configuring detection enable, configuration selection information and setting comparison data, storing a comparison result and opening the detection enable;
the write instruction module writes the set data into a corresponding storage unit of the flash to be tested according to the configuration selection information;
the read instruction module reads data written in a corresponding storage unit of the flash to be tested according to the configuration selection information;
the comparison module compares whether the read data is consistent with the comparison data or not and outputs a storage unit error mark;
and the write configuration instruction module writes the comparison result into a corresponding storage unit of the flash to be tested.
6. The circuit for detecting flash memory errors of claim 5, wherein the configuration module employs a circuit consisting of LATCH.
7. The flash memory corruption detection circuit of claim 5, further comprising a receive output module to receive a write instruction, a read instruction, a write configuration instruction, and to output a memory cell error flag.
8. The circuit of claim 7, wherein the receive output module is implemented using an IO interface.
9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 4.
10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 4 by calling the computer program stored in the memory.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114267402A (en) * | 2021-11-22 | 2022-04-01 | 上海芯存天下电子科技有限公司 | Bad storage unit testing method, device, equipment and storage medium of flash memory |
| WO2023137855A1 (en) * | 2022-01-19 | 2023-07-27 | 长鑫存储技术有限公司 | Test method for memory chip and device |
| CN116504293A (en) * | 2023-06-27 | 2023-07-28 | 芯天下技术股份有限公司 | Method and device for reading non flash, memory chip and equipment |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW385449B (en) * | 1997-06-17 | 2000-03-21 | Siemens Ag | Arrangement with memory-cells and method to check the function of said memory-cells |
| KR20010046174A (en) * | 1999-11-11 | 2001-06-05 | 박종섭 | Internal test circuit for non-volatile memory |
| US6297997B1 (en) * | 1999-06-30 | 2001-10-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device capable of reducing cost of analysis for finding replacement address in memory array |
| US20010056557A1 (en) * | 2000-06-14 | 2001-12-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device including semiconductor memory with tester circuit capable of analyzing redundancy repair |
| JP2009026285A (en) * | 2007-06-21 | 2009-02-05 | Mega Chips Corp | Memory controller |
| JP2009199640A (en) * | 2008-02-20 | 2009-09-03 | Nec Electronics Corp | Memory test circuit and semiconductor memory device |
| CN101777013A (en) * | 2009-01-12 | 2010-07-14 | 成都市华为赛门铁克科技有限公司 | Solid state disk and data read-write method |
| JP2012033222A (en) * | 2010-07-29 | 2012-02-16 | Toshiba Corp | Semiconductor memory device and its control method |
| KR101527690B1 (en) * | 2014-10-10 | 2015-06-11 | (주) 에이블리 | NAND flash memory test interface apparatus and operating method thereof |
| CN111221693A (en) * | 2019-12-31 | 2020-06-02 | 深圳市芯天下技术有限公司 | Verification method, system, device and storage medium for NOR flash configuration module |
-
2020
- 2020-12-30 CN CN202011614403.7A patent/CN112542199B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW385449B (en) * | 1997-06-17 | 2000-03-21 | Siemens Ag | Arrangement with memory-cells and method to check the function of said memory-cells |
| US6297997B1 (en) * | 1999-06-30 | 2001-10-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device capable of reducing cost of analysis for finding replacement address in memory array |
| KR20010046174A (en) * | 1999-11-11 | 2001-06-05 | 박종섭 | Internal test circuit for non-volatile memory |
| US20010056557A1 (en) * | 2000-06-14 | 2001-12-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device including semiconductor memory with tester circuit capable of analyzing redundancy repair |
| JP2009026285A (en) * | 2007-06-21 | 2009-02-05 | Mega Chips Corp | Memory controller |
| JP2009199640A (en) * | 2008-02-20 | 2009-09-03 | Nec Electronics Corp | Memory test circuit and semiconductor memory device |
| CN101777013A (en) * | 2009-01-12 | 2010-07-14 | 成都市华为赛门铁克科技有限公司 | Solid state disk and data read-write method |
| JP2012033222A (en) * | 2010-07-29 | 2012-02-16 | Toshiba Corp | Semiconductor memory device and its control method |
| KR101527690B1 (en) * | 2014-10-10 | 2015-06-11 | (주) 에이블리 | NAND flash memory test interface apparatus and operating method thereof |
| CN111221693A (en) * | 2019-12-31 | 2020-06-02 | 深圳市芯天下技术有限公司 | Verification method, system, device and storage medium for NOR flash configuration module |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114267402A (en) * | 2021-11-22 | 2022-04-01 | 上海芯存天下电子科技有限公司 | Bad storage unit testing method, device, equipment and storage medium of flash memory |
| CN114267402B (en) * | 2021-11-22 | 2022-11-18 | 上海芯存天下电子科技有限公司 | Bad storage unit testing method, device, equipment and storage medium of flash memory |
| WO2023137855A1 (en) * | 2022-01-19 | 2023-07-27 | 长鑫存储技术有限公司 | Test method for memory chip and device |
| CN116504293A (en) * | 2023-06-27 | 2023-07-28 | 芯天下技术股份有限公司 | Method and device for reading non flash, memory chip and equipment |
| CN116504293B (en) * | 2023-06-27 | 2023-10-13 | 芯天下技术股份有限公司 | Method and device for reading non flash, memory chip and equipment |
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| CN112542199B (en) | 2024-04-12 |
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