CN106777729A - A kind of algorithms library simulation and verification platform implementation method based on FPGA - Google Patents
A kind of algorithms library simulation and verification platform implementation method based on FPGA Download PDFInfo
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- CN106777729A CN106777729A CN201611217349.6A CN201611217349A CN106777729A CN 106777729 A CN106777729 A CN 106777729A CN 201611217349 A CN201611217349 A CN 201611217349A CN 106777729 A CN106777729 A CN 106777729A
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- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The present invention provides a kind of algorithms library simulation and verification platform implementation method based on FPGA.Its step is as follows：The first step：According to the requirement of nuclear power station security level control system, the basic FPGA of all of algorithmic block is realized, all algorithmic blocks in algorithms library are set into unified interface；Second step：Produce the simulation excitation vector of each algorithmic block；3rd step：If necessary to addition algorithmic block, it is only necessary to increase algorithmic block content and corresponding artificial vector on the verification platform, then change configuration file；4th step：The simulation result that emulation tool is exported compares with emulator generation result.The unification of each algorithmic block is identical interface by the present invention, once need to increase algorithmic block or increase artificial vector, it is only necessary to configuration file is changed, it is possible to call the algorithmic block automatically, so as to reach the purpose of automatic simulation.
Description
Technical field
The present invention relates to the nuclear power control system of big data quantity computing, and in particular to a kind of algorithms library emulation based on FPGA
Verification platform implementation method.
Background technology
With the high speed development of nuclear industry, various algorithms are widely used in safe level nuclear power station, and by
It is more and more extensively and complicated in its applied environment, also cause that the function that safe level nuclear power station algorithm place is included becomes increasingly complex,
Algorithm is more and more, and the emulation difficulty of algorithms library is also being stepped up.Very polyalgorithm is generally included in one algorithms library, if
The software emulation mode provided using prior art, is provided separately test and excitation signal, in algorithms library for each module
Module carries out simulating, verifying one by one, and this will cause testing time and error probability sharp increase, therefore, how rapidly and efficiently
Simple to carry out simulating, verifying, the cycle for shortening checking just turns into the important topic that we face at present.
The content of the invention
It is an object of the invention to provide a kind of algorithms library simulation and verification platform implementation method based on FPGA, it can be carried
Simulation efficiency high, shortens the research and development of products cycle.
Realize the technical scheme of the object of the invention：A kind of nuclear safe level algorithms library intelligent simulation verification platform based on FPGA
Implementation method, described algorithms library is nuclear power control system algorithms library, and it comprises the following steps：
The first step：According to the requirement of nuclear power station security level control system, the basic FPGA of all of algorithmic block is realized,
All algorithmic blocks in algorithms library are set to unified interface；
Second step：Produce the simulation excitation vector of each algorithmic block；
3rd step：If necessary to addition algorithmic block, it is only necessary to increase algorithmic block content and corresponding on the verification platform
Artificial vector, then changes configuration file；
4th step：The simulation result that emulation tool is exported compares with emulator generation result.
A kind of algorithms library simulation and verification platform implementation method based on FPGA as described above, it comprises the following steps：
The first step：All algorithmic blocks in algorithms library are set to unified interface, including each algorithmic block input number
According to interface；
Second step：The simulation excitation vector of each algorithmic block, excitation vector is produced to be deposited with floating number IEEE754 forms；
3rd step：According to test request, if necessary to addition algorithmic block, it is only necessary to increase algorithmic block content on the platform
With corresponding artificial vector, configuration file is then changed, then increase algorithmic block newly and be added automatically, export simulation result；
4th step：The simulation result that emulation tool is exported compares with emulator generation result.
A kind of algorithms library simulation and verification platform implementation method based on FPGA as described above, its method specifically include as
Lower step：
The first step：All algorithmic block interfaces in algorithms library are unified, and input data and output data register are long
Spend according to specific algorithmic block automatic adjustment, so that suitable for different algorithmic blocks；And use unified control signal, the control
Signal processed is applied to all of algorithmic block；
Second step：The input artificial vector of testing algorithm block needed for input is metric, with emulator MATLAB, by this
Input vector is stored with IEEE754 forms；
3rd step：According to test request, the artificial vector needed for producing simulation and verification platform；By all of algorithmic block and imitative
Very vector is included into algorithms library simulation and verification platform, afterwards, it is only necessary to modification configuration excitation file, it becomes possible to different
Algorithmic block is emulated, once need the new algorithmic block of addition, it is only necessary to algorithmic block and input vector are added, no
Docking port is needed to do any change；
4th step：Emulate each step results to be printed in the script file of FPGA emulation tools modelsim, most
Fruit is exported termination with document form, is compared with simulator results.
Effect of the invention is that：
The present invention proposes a kind of new algorithms library simulation and verification platform implementation method, is identical by the unification of each algorithmic block
Interface, once need increase algorithmic block or increase artificial vector, it is only necessary to change configuration file, it is possible to call this automatically
Algorithmic block, so as to reach the purpose of automatic simulation.The simulation and verification platform realized using the present invention, each algorithmic block has system
One interface, it is only necessary to which a simulation excitation file can just call each algorithmic block and test vector.
Existing nuclear power field algorithmic block is individually emulated using algorithmic block one by one, and each algorithmic block is required for corresponding sharp
File is encouraged, proving period is long.By comparison, algorithms library simulation and verification platform interface proposed by the invention is simply unified
Change, emulation is more automated, rapidly and efficiently simply realize simulating, verifying, shorten the simulating, verifying cycle.
Brief description of the drawings
Fig. 1 is a kind of algorithms library simulation and verification platform flow chart based on FPGA of the present invention.
Specific embodiment
It is flat to a kind of algorithms library simulating, verifying based on FPGA of the present invention with specific embodiment below in conjunction with the accompanying drawings
Platform implementation method is further described.
Embodiment 1
As shown in figure 1, by taking a newly-increased four input summer algorithmic blocks as an example, being described in detail to the present invention, its implementation
Step is as follows：
The first step：The input of four input summers is added in unified input data interface.Input data and output
Data register length accordingly makes appropriate adjustment.Using unified control signal.
Second step：Some groups of test vectors are produced according to test request, with matlab emulators by all decimal additions
Device input is deposited with floating number IEEE754 forms；
3rd step：Adder source file and test vector are included into algorithms library verification platform, are changed in the platform
The once configuration file of adder, the then adder algorithm block for newly increasing just now is added automatically, it is not necessary to which docking port is appointed
What is changed, and exports simulation result；
4th step：The script file of FPGA emulation tools modelsim will progressively show each step operation knot of adder
Really, and final result is deposited with document format, it is convenient to be compared with emulator.
Embodiment 2
As shown in figure 1, by taking a newly-increased divider algorithmic block as an example, to a kind of algorithm based on FPGA of the present invention
Storehouse simulation and verification platform implementation method is been described by, and implementation step is as follows：
The first step：The input of four input dividers is added in unified input data interface.Input data and output
Data register length accordingly makes appropriate adjustment.Using unified control signal.
Second step：Some groups of test vectors are produced according to test request, with matlab emulators by all decimal divisions
Device input vector is deposited with floating number IEEE754 forms；
3rd step：Divider source file and test vector are included into algorithms library verification platform, are changed in the platform
The once configuration file of divider, the then divider algorithmic block for newly increasing just now is added automatically, it is not necessary to which docking port is appointed
What is changed, and exports simulation result；
4th step：The script file of FPGA emulation tools modelsim will progressively show each step operation knot of adder
Really, and final result is deposited with document format, it is convenient to be compared with emulator.
Need to emulate algorithmic block one by one during existing general algorithmic block simulating, verifying, computational efficiency is than relatively low
And using in algorithmic block simulating, verifying implementation method proposed by the present invention, all of algorithmic block all has unified interface, and
Algorithms library content also can constantly be extended, and increase new algorithmic block, and extra time overhead is not increased but.
Embodiment 3
A kind of nuclear safe level algorithms library intelligent simulation verification platform implementation method based on FPGA of the present invention, it is described
Algorithms library be nuclear power control system algorithms library, it comprises the following steps：
The first step：According to the requirement of nuclear power station security level control system, the basic FPGA of all of algorithmic block is realized,
All algorithmic blocks in algorithms library are set to unified interface；
Second step：Produce the simulation excitation vector of each algorithmic block；
3rd step：If necessary to addition algorithmic block, it is only necessary to increase algorithmic block content and corresponding on the verification platform
Artificial vector, then changes configuration file；
4th step：The simulation result that emulation tool is exported compares with emulator generation result.
Embodiment 4
A kind of algorithms library simulation and verification platform implementation method based on FPGA of the present invention, described algorithms library is core
Electric control system application algorithms library, it comprises the following steps：
The first step：According to the requirement of nuclear power station security level control system, all algorithmic blocks in algorithms library are set
Be unified interface, including each algorithmic block input data interface.
Second step：The simulation excitation vector of each algorithmic block, excitation vector is produced to be deposited with floating number IEEE754 forms；
3rd step：According to test request, if necessary to addition algorithmic block, it is only necessary to increase algorithmic block content on the platform
With corresponding artificial vector, configuration file is then changed, then increase algorithmic block newly and be added automatically, export simulation result；
4th step：The simulation result that emulation tool is exported compares with emulator generation result.
Embodiment 5
A kind of algorithms library simulation and verification platform implementation method based on FPGA of the present invention, described algorithms library is core
Electric control system application algorithms library, it comprises the following steps：
The first step：All algorithmic block interfaces in algorithms library are unified, and input data and output data register are long
Spend according to specific algorithmic block automatic adjustment, so that suitable for different algorithmic blocks；And use unified control signal, the control
Signal processed is applied to all of algorithmic block；
Second step：The input artificial vector of testing algorithm block needed for input is metric, with emulator MATLAB, by this
Input vector is stored with IEEE754 forms；
3rd step：According to test request, the artificial vector needed for producing simulation and verification platform；By all of algorithmic block and imitative
Very vector is included into algorithms library simulation and verification platform, afterwards, it is only necessary to modification configuration excitation file, it becomes possible to different
Algorithmic block is emulated, once need the new algorithmic block of addition, it is only necessary to algorithmic block and input vector are added, no
Docking port is needed to do any change；
4th step：Emulate each step results to be printed in the script file of FPGA emulation tools modelsim, most
Fruit is exported termination with document form, is compared with simulator results.
Claims (3)
1. a kind of nuclear safe level algorithms library intelligent simulation verification platform implementation method based on FPGA, described algorithms library is nuclear power
Control system algorithms library, it is characterised in that the method comprises the following steps：
The first step：According to the requirement of nuclear power station security level control system, the basic FPGA of all of algorithmic block is realized, will be calculated
All algorithmic blocks in Faku County are set to unified interface；
Second step：Produce the simulation excitation vector of each algorithmic block；
3rd step：If necessary to addition algorithmic block, it is only necessary to increase algorithmic block content and corresponding emulation on the verification platform
Vector, then changes configuration file；
4th step：The simulation result that emulation tool is exported compares with emulator generation result.
2. a kind of algorithms library simulation and verification platform implementation method based on FPGA according to claim 1, it is characterised in that
The method specifically includes following steps：
The first step：All algorithmic blocks in algorithms library are set to unified interface, including the input data of each algorithmic block connects
Mouthful.
Second step：The simulation excitation vector of each algorithmic block, excitation vector is produced to be deposited with floating number IEEE754 forms；
3rd step：According to test request, if necessary to addition algorithmic block, it is only necessary to increase algorithmic block content and right on the platform
The artificial vector answered, then changes configuration file, then increase algorithmic block newly and be added automatically, exports simulation result；
4th step：The simulation result that emulation tool is exported compares with emulator generation result.
3. a kind of algorithms library simulation and verification platform implementation method based on FPGA according to claim 2, it is characterised in that
The method specifically includes following steps：
The first step：All algorithmic block interfaces in algorithms library are unified, input data and output data register capacity root
According to specific algorithmic block automatic adjustment, so that suitable for different algorithmic blocks；And use unified control signal, control letter
Number be applied to all of algorithmic block；
Second step：The input artificial vector of testing algorithm block, with emulator MATLAB, this is input into needed for input is metric
Vector is stored with IEEE754 forms；
3rd step：According to test request, the artificial vector needed for producing simulation and verification platform；By all of algorithmic block and emulate to
Amount is included into algorithms library simulation and verification platform, afterwards, it is only necessary to modification configuration excitation file, it becomes possible to different algorithms
Block is emulated, once need the new algorithmic block of addition, it is only necessary to algorithmic block and input vector are added, it is not necessary to
Docking port does any change；
4th step：Emulate each step results to be printed in the script file of FPGA emulation tools modelsim, most terminate
Fruit is exported with document form, is compared with simulator results.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107992009A (en) * | 2017-12-13 | 2018-05-04 | 中核控制系统工程有限公司 | A kind of safe level DCS emulators based on FPGA |
| CN109407638A (en) * | 2018-12-07 | 2019-03-01 | 南京核新数码科技有限公司 | Industrial control system information security implementation method based on the virtual DCS of FPGA |
| CN111143208A (en) * | 2019-12-23 | 2020-05-12 | 江苏亨通太赫兹技术有限公司 | Verification method for assisting FPGA to realize AI algorithm based on processor technology |
| CN111221693A (en) * | 2019-12-31 | 2020-06-02 | 深圳市芯天下技术有限公司 | Verification method, system, device and storage medium for NOR flash configuration module |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1577274A (en) * | 2003-07-01 | 2005-02-09 | 华为技术有限公司 | Automation emulation method and system |
| CN101183406A (en) * | 2007-12-25 | 2008-05-21 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| CN101793941A (en) * | 2009-12-24 | 2010-08-04 | 上海华岭集成电路技术有限责任公司 | Creation method of FPGA (Field Programmable Gate Array ) configuration file |
| CN103399758A (en) * | 2011-12-31 | 2013-11-20 | 华为数字技术（成都）有限公司 | Hardware accelerating method, device and system |
| US20140236527A1 (en) * | 2013-02-21 | 2014-08-21 | Advantest Corporation | Cloud based infrastructure for supporting protocol reconfigurations in protocol independent device testing systems |
| CN106126854A (en) * | 2016-07-01 | 2016-11-16 | 合肥海本蓝科技有限公司 | A kind of software and hardware cooperating simulation trade device and analogue system |
| CN106156424A (en) * | 2016-07-01 | 2016-11-23 | 合肥海本蓝科技有限公司 | A kind of analogue system |
-
2016
- 2016-12-26 CN CN201611217349.6A patent/CN106777729A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1577274A (en) * | 2003-07-01 | 2005-02-09 | 华为技术有限公司 | Automation emulation method and system |
| CN101183406A (en) * | 2007-12-25 | 2008-05-21 | 盛科网络（苏州）有限公司 | Method for establishing network chip module level function checking testing platform |
| CN101793941A (en) * | 2009-12-24 | 2010-08-04 | 上海华岭集成电路技术有限责任公司 | Creation method of FPGA (Field Programmable Gate Array ) configuration file |
| CN103399758A (en) * | 2011-12-31 | 2013-11-20 | 华为数字技术（成都）有限公司 | Hardware accelerating method, device and system |
| US20140236527A1 (en) * | 2013-02-21 | 2014-08-21 | Advantest Corporation | Cloud based infrastructure for supporting protocol reconfigurations in protocol independent device testing systems |
| CN106126854A (en) * | 2016-07-01 | 2016-11-16 | 合肥海本蓝科技有限公司 | A kind of software and hardware cooperating simulation trade device and analogue system |
| CN106156424A (en) * | 2016-07-01 | 2016-11-23 | 合肥海本蓝科技有限公司 | A kind of analogue system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107992009A (en) * | 2017-12-13 | 2018-05-04 | 中核控制系统工程有限公司 | A kind of safe level DCS emulators based on FPGA |
| CN109407638A (en) * | 2018-12-07 | 2019-03-01 | 南京核新数码科技有限公司 | Industrial control system information security implementation method based on the virtual DCS of FPGA |
| CN111143208A (en) * | 2019-12-23 | 2020-05-12 | 江苏亨通太赫兹技术有限公司 | Verification method for assisting FPGA to realize AI algorithm based on processor technology |
| CN111221693A (en) * | 2019-12-31 | 2020-06-02 | 深圳市芯天下技术有限公司 | Verification method, system, device and storage medium for NOR flash configuration module |
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