CN105302950A - Software and hardware cooperation based cross-linking simulation test method for programmable logic device - Google Patents
Software and hardware cooperation based cross-linking simulation test method for programmable logic device Download PDFInfo
- Publication number
- CN105302950A CN105302950A CN201510680633.6A CN201510680633A CN105302950A CN 105302950 A CN105302950 A CN 105302950A CN 201510680633 A CN201510680633 A CN 201510680633A CN 105302950 A CN105302950 A CN 105302950A
- Authority
- CN
- China
- Prior art keywords
- programmable logic
- logic device
- pld
- simulation
- hardware
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a software and hardware cooperation based cross-linking simulation test method for a programmable logic device. The method comprises: establishing a software simulation verification environment and a hardware simulation verification environment by utilizing a thought of combining black and white box tests, providing soft excitation for a tested design model through the means of device modeling, fault modeling, Matlab simulation and the like, and performing functional simulation and time sequence simulation on the tested design model by utilizing a ModelSim compiling simulator; and applying hard excitation to the programmable logic device in a DSP chip programming mode, observing and recording features and waveforms of physical response signals of the programmable logic device and a peripheral circuit by utilizing a digital logic analyzer, finishing functions and time sequence simulation of the programmable logic device in a hardware entity, and continuously correcting the design model through comparative analysis of test results in the two simulation verification environments to gradually approximate practical parameters of the whole control circuit, so that the test results finally reach convergence states, the parameter optimization of circuit design is realized, and the test precision and reliability are improved.
Description
Technical field
The programmable logic device (PLD) that the present invention relates to a kind of soft and hardware collaborative is cross-linked emulation test method, the checking of the function to programmable logic device (PLD), sequential can be realized in different checking ranks and verification environment, mainly use on the hardware structure of DSP high speed digital signal processor+programmable logic device (PLD) coprocessor.
Background technology
Along with the needs of technical development and improving constantly of control system performance requirement, traditional analog control technique fades away, then adopting high-speed figure control technology, control technology progressively presents the development trend of informationization, networking, intellectuality and precision.In the development of Novel servo system, the function that servo-drive system realizes is more and more, performance requirement is more and more higher, control structure becomes increasingly complex, make the core processor hardware framework of traditional servo controller cannot meet control overflow, more and more servo-drive system is introduced programmable logic device (PLD) and is participated in controlling, adopt the hardware structure of DSP high speed digital signal processor+programmable logic device (PLD) coprocessor, utilize programmable logic device (PLD) to carry out logic planning to digital display circuit, realize a large amount of control of A/D, D/A ALT-CH alternate channel and the control of bus timing.
In addition, along with miniaturization, integrated, the development of lighting, the introducing of scale programmable logic device will certainly be caused, by writing the mode autonomous configuration hardware resource of hardware description language, design hardware capability circuit module, replace circuit chip various at present and peripheral circuit thereof, this improves constantly with regard to making the importance of programmable logic device (PLD) software, once programmable logic device (PLD) existing defects, programmable logic device (PLD) will be caused normally cannot to realize expectation function, directly have influence on global reliability, therefore the testing requirement of programmable logic device (PLD) is become particularly urgent, carry out comprehensively to programmable logic device (PLD), accurately, efficient Testing Technology Study seems particularly important.
With CPLD, FPGA is that the application of programmable logic device (PLD) in engineering of representative is more late, it is the technology that last decade has just risen, because it has low in energy consumption, integrated level is high, advantages such as dirigibility is strong and receive much concern and be progressively applied, development language is hardware description language (HDL), the testing standard that the domestic and international testing authentication for this language is still ununified at present, do not have a set of general yet, effective method of testing and testing process, the emulation tool carried in the Integrated Development Environment that traditional programmable logic device (PLD) software verification mainly provides by means of chip maker carries out, first system description is carried out, under system-based condition, with hardware description language by the behavior description of system out, next carries out functional emulation to program, whether inspection describes correct, then carry out comprehensive, comprehensive post-simulation is carried out to the gate level circuit comprehensively obtained, whether look facility is consistent with requirement, finally the Delay reactionary slogan, anti-communist poster of placement-and-routing is noted in design netlist, carry out placement-and-routing's post-simulation, check that whether design sequential is consistent with programmable logic device (PLD) practical operation situation, unit with good conditionsi also will test by means of ATE (automatic test equipment) ATE (AutomaticTestEquipment) logical resource to programmable logic device (PLD) chip internal.Not only testing procedure is loaded down with trivial details for this traditional test mode, test period is long, and input in testing tool, testing apparatus is huge, can not the actual working environment of programmable analog logical device completely, more can not carry out testing to programmable logic device (PLD) comprehensively, accurately.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provide a kind of soft, the programmable logic device (PLD) that hardware is worked in coordination with is cross-linked emulation test method, utilize the thought that black white-box testing combines, set up software emulation verification environment and simulation hardware verification environment respectively, function to programmable logic device (PLD) in different checking ranks and verification environment, sequential to be carried out comprehensively, accurate checking, and by the comparative analysis to two kinds of simulating, verifying environmental testing results, continuous amendment design model, the actual parameter of the whole control circuit of Step wise approximation, test result is made finally to reach convergence state, achieve the parameter optimization of circuit design, improve the accuracy and confidence of test.
Technical solution of the present invention is:
The programmable logic device (PLD) that soft and hardware is worked in coordination with is cross-linked an emulation test method, and step is as follows:
(1) circuit structure of the control circuit to be measured comprising programmable logic device (PLD) is determined;
(2) according to the circuit structure of described control circuit to be measured, adopt hardware description language to carry out simulation modeling to the device in control circuit, form simulation model library;
(3) according to the fault type that described control circuit to be measured may occur, corresponding fault model is set up by hardware description language;
(4) according to the simulation model library in the circuit structure in step (1) and step (2), modeling is carried out to described control circuit entirety to be measured, for simulating the mutual and time-delay characteristics of signal between tested programmable logic device (PLD) and peripheral chip;
According to the circuit structure in step (1), build entity control circuit;
(5) software emulation verification environment and simulation hardware verification environment is built; Software emulation verification environment comprises software emulation authenticating computer, Matlab software and ModelSim and compiles emulator; Simulation hardware verification environment comprises simulation hardware authenticating computer, Digital Logic Analyzer and DSP emulator; CCS is had to compile debugging software in simulation hardware authenticating computer;
(6) in described software emulation verification environment, according to the principle of white-box testing, write test and excitation Testbench, in the test and excitation the Testbench simultaneously fault model in step (3) is injected into together with the excited data designed in advance in Matlab software, test and excitation Testbench is injected in the control circuit model to be measured set up in step (4), utilize ModelSim to compile emulator and carry out functional simulation, and wave recording file and coverage rate;
(7) in simulation hardware verification environment, according to the principle of Black-box Testing, compile debugging software by CCS to programme to dsp chip according to fault model, dsp chip is made to export normal or abnormal control signal, control signal in simulation actual motion environment and the abnormal control signal that may occur, hardware excitation is applied in tested programmable logic device (PLD), and utilizes Digital Logic Analyzer to observe and record feature and the waveform of programmable logic device (PLD) and peripheral circuit physical responses signal;
(8) in software emulation verification environment, application Matlab software carries out functional simulation to programmable logic device (PLD), software emulation result in simulation result and step (6) is compared, in simulation hardware verification environment, the acquiescence sequential of each chip in the hardware simulation results in step (7) and control circuit is compared; If software emulation comparative result is consistent with simulation hardware comparative result, then enters step (9), otherwise again revise the design of programmable logic device (PLD), return step (6);
(9) in ModelSim compiling emulator, add net meter file, standard time sequence delayer, design constraint and test vector library file and time stimulatiom is carried out to programmable logic device (PLD), generate and record performance Study document;
(10) in simulation hardware verification environment, time sequence information is added in the mode of dsp program in hardware excitation, the characteristic of the control signal that dsp chip is exported changes or reaches critical conditions, utilizes Digital Logic Analyzer to observe and records feature and the waveform of programmable logic device (PLD) and peripheral circuit physical responses signal;
(11) simulation result in the simulation result of step (9) and step (6) is compared, the acquiescence sequential of each chip in the simulation result of step (10) and control circuit is compared, if comparative result is unanimously, then complete the crosslinked emulation testing of the programmable logic device (PLD) of described software-hardware synergism, otherwise again revise the design of programmable logic device (PLD), return step (6).
Described control circuit to be measured comprises dsp chip, programmable logic device (PLD), power reset chip, the first clock circuit, second clock circuit, a JTEG circuit, the 2nd JTEG circuit, bus driver, 1553B Bus Interface Chip, analog to digital converter ADC and digital to analog converter DAC;
First clock circuit provides clock signal for dsp chip, second clock circuit provides clock signal for 1553B bus protocol chip, power reset chip provides power supply for whole control circuit to be measured, and for programmable logic device (PLD) provides reset signal, this reset signal is distributed to dsp chip after programmable logic device (PLD) filtering process, 1553B Bus Interface Chip and digital to analog converter ADC, DSP address bus and programmable logic device (PLD), 1553B bus protocol chip is direct-connected, data bus through bus driver isolation after with 1553B bus protocol chip, digital to analog converter DAC, analog to digital converter ADC connects, dsp chip exports control signal to programmable logic device (PLD), 1553B bus protocol chip is exported to after programmable logic device (PLD) logical process, digital to analog converter DAC, analog to digital converter ADC and bus driver chip, carry out the sequential control of data transmission, one JTEG circuit is connected to dsp chip, and the 2nd JTEG circuit is connected to programmable logic device (PLD).
Described programmable logic device (PLD) is CPLD chip or fpga chip.
Described hardware description language is VerilogHDL, VHDL or SystemC.
The fault type that described control circuit to be measured may occur comprises:
Exist periodically or randomness undesired signal in the control signal that a, programmable logic device (PLD) export;
Exist periodically or randomness undesired signal in the control signal that b, dsp chip export;
The control signal that c, programmable logic device (PLD) export is lost or was lost efficacy;
The control signal retention time that d, programmable logic device (PLD) export is too short, cannot reach the response demand of peripheral components;
The change frequency of the control signal that e, programmable logic device (PLD) export is too high, exceeds the processing power of peripheral components;
The change frequency of the control signal that f, dsp chip export is too high, exceeds the processing power of programmable logic device (PLD).
In described step (10), the characteristic of control signal comprises retention time and change frequency.
The present invention's beneficial effect is compared with prior art:
(1) the present invention utilizes the peripheral circuit such as DSP high speed digital signal processor, 1553B Bus Interface Chip, power reset chip, AD converter, D/A converter of device Modeling pair and programmable logic device (PLD) interface and device to carry out modeling, composition simulation model library, as a kind of means providing the tested test and excitation that designs a model, in software emulation verification environment, build one with this and be similar to real, virtual hardware running environment.
(2) off-line closed loop test system is constituted by software emulation verification environment, realize the simulating, verifying to the tested function that designs a model, sequential in the ideal situation, comprehensive inspection has been carried out to the design constraint of tested design a model (programmable logic device (PLD)).
(3) build online dynamic test platform by simulation hardware verification environment, realize, to the simulating, verifying of the tested function that designs a model, sequential, hardware view being verified the steering logic of whole circuit and interface under actual motion environment.
(4) for hardware structure feature, the programmable logic device (PLD) constructing soft and hardware collaborative is cross-linked Simulation Test Environment, by the analyses and comparison to the test result under software and hardware verification environment, under theory and practice condition, continuous amendment design model, make the parameter designing of circuit achieve optimization, improve the global reliability of servo controller hardware circuit.
(5) traditional Design for Programmable Logic checking flow process is replaced, the programmable logic device (PLD) proposing soft and hardware collaborative is cross-linked emulation testing flow process, the emphasis of testing authentication is only placed in function and sequential, and do not consider other pilot process, thus decrease verification step, simplify testing process, improve the efficiency of test, ensure that programmable logic device (PLD) function, timing sequence test are verified comprehensive simultaneously.
(6) utilize software approach, by Matlab software to the tested applying random series that designs a model, realize the collaborative simulation to programmable logic device (PLD) fault and analysis, in the fault-tolerant ability of software view inspection programmable logic device (PLD).
(7) hardware means is utilized, input illegal logic realization to the dynamic simulation of programmable logic device (PLD) fault and analysis by DSP high speed digital signal processor to programmable logic device (PLD), fully check the reliability of programmable logic device (PLD), the ability resisting fault and antijamming capability.
(8) by the function of programmable logic device (PLD), the checking authenticate reverse of sequential based on function, the performance of the servo control software of DSP high speed digital signal processor, for the read-write sequence between DSP and 1553B bus communication chip provide the most truly, the most direct data, and become the foundation instructing DSP, 1553B bus chip related register to configure.
Accompanying drawing explanation
The crosslinked emulation testing process flow diagram that Fig. 1 soft and hardware is collaborative
Fig. 2 control circuit structural drawing to be measured
Fig. 3 simulation model library structural drawing
The crosslinked Simulation Test Environment block diagram that Fig. 4 soft and hardware is collaborative
Fig. 5 is based on the hardware fault simulation analysis schematic diagram of DSP
Fig. 6 is based on the software fault simulation analysis schematic diagram of Matlab
Fig. 7 servo controller control circuit structural drawing
Functional simulation oscillogram under Fig. 8 software emulation verification environment
Functional simulation oscillogram under Fig. 9 simulation hardware verification environment
Time stimulatiom oscillogram under Figure 10 software emulation verification environment
Time stimulatiom oscillogram under Figure 11 simulation hardware verification environment
Embodiment
The programmable logic device (PLD) that the invention provides a kind of soft and hardware collaborative is cross-linked emulation test method, utilize the thought that black white-box testing combines, set up software emulation verification environment and simulation hardware verification environment respectively, be that tested design a model (programmable logic device (PLD)) provides soft excitation by means such as organs weight, fault modeling, Matlab emulation in software emulation verification environment, and utilize ModelSim to compile emulator to carry out functional simulation and time stimulatiom to tested designing a model, by applying hard excitation to the mode of dsp program to programmable logic device (PLD), steering logic in simulation actual motion environment, utilize Digital Logic Analyzer to observe and record feature and the waveform of programmable logic device (PLD) and peripheral circuit physical responses signal, complete the function of programmable logic device (PLD) on hardware material object, time stimulatiom, thus realize in difference checking rank and verification environment programmable logic device (PLD) function, the collaborative test of sequential, and by the comparative analysis to test result under two kinds of simulating, verifying environment, continuous amendment design model, the actual parameter of the whole control circuit of Step wise approximation, test result is made finally to reach convergence state, the parameter optimization of realizing circuit design, improve the accuracy and confidence of test.
As shown in Figure 1, the programmable logic device (PLD) that soft and hardware provided by the invention is worked in coordination with is cross-linked emulation test method, and step is as follows:
(1) circuit structure of the control circuit to be measured comprising programmable logic device (PLD) is determined;
As shown in Figure 2, described control circuit to be measured comprises dsp chip, programmable logic device (PLD), power reset chip, the first clock circuit, second clock circuit, a JTEG circuit, the 2nd JTEG circuit, bus driver, 1553B Bus Interface Chip, analog to digital converter ADC and digital to analog converter DAC; Described programmable logic device (PLD) is CPLD chip or fpga chip.
First clock circuit provides clock signal for dsp chip, second clock circuit provides clock signal for 1553B bus protocol chip, power reset chip provides power supply for whole control circuit to be measured, and for programmable logic device (PLD) provides reset signal, this reset signal is distributed to dsp chip after programmable logic device (PLD) filtering process, 1553B Bus Interface Chip and digital to analog converter ADC, DSP address bus and programmable logic device (PLD), 1553B bus protocol chip is direct-connected, data bus through bus driver isolation after with 1553B bus protocol chip, digital to analog converter DAC, analog to digital converter ADC connects, dsp chip exports control signal to programmable logic device (PLD), 1553B bus protocol chip is exported to after programmable logic device (PLD) logical process, digital to analog converter DAC, analog to digital converter ADC and bus driver chip, carry out the sequential control of data transmission, one JTEG circuit is connected to dsp chip, and the 2nd JTEG circuit is connected to programmable logic device (PLD).
(2) according to the circuit structure of described control circuit to be measured, principle of work according to device adopts hardware description language to carry out simulation modeling to the device in control circuit, functional analysis is carried out to the peripheral components with programmable logic device (PLD) interface, combined with hardware circuit structure extracts control signal (the such as bus signals needing modeling, enable signal, chip selection signal etc.), by hardware description language, according to control overflow, logical description is carried out to control signal, comprise foundation and the retention time of signal level, the amplitude etc. of signal level, realize the circuit operation of regulation, time series modeling is carried out again according to the electrology characteristic of device and temporal characteristics, according to the timing requirements specified in device layout handbook exemplary timing diagram, delayed data is added in logical description, the time-delay characteristics of analog device, device model is compiled in emulator at ModelSim and carries out compiling emulation, form simulation model library.As shown in Figure 3, by compiling by after device model precompile in simulation model library, to tested design a model simulating, verifying time directly extract from simulation model library, and as the tested test and excitation designed a model.Described hardware description language is VerilogHDL, VHDL or SystemC.
(3) according to the fault type that described control circuit to be measured may occur, corresponding fault model is set up by hardware description language;
The fault type that described control circuit to be measured may occur comprises:
Exist periodically or randomness undesired signal in the control signal that a, programmable logic device (PLD) export;
Exist periodically or randomness undesired signal in the control signal that b, dsp chip export;
The control signal that c, programmable logic device (PLD) export is lost or was lost efficacy;
The control signal retention time that d, programmable logic device (PLD) export is too short, cannot reach the response demand of peripheral components;
The change frequency of the control signal that e, programmable logic device (PLD) export is too high, exceeds the processing power of peripheral components;
The change frequency of the control signal that f, dsp chip export is too high, exceeds the processing power of programmable logic device (PLD).
(4) according to the simulation model library in the circuit structure in step (1) and step (2), modeling is carried out to described control circuit entirety to be measured, utilize hardware description language that each device model in control circuit to be measured is carried out interface and behavior description, simulate the mutual and time-delay characteristics of signal between tested programmable logic device (PLD) and peripheral chip, thus construct one and be similar to real, virtual hardware running environment;
According to the circuit structure in step (1), build entity control circuit;
(5) software emulation verification environment and simulation hardware verification environment is built, as shown in Figure 4, software emulation verification environment comprises software emulation authenticating computer, Matlab software and ModelSim compile emulator, wherein software emulation authenticating computer runs Matlab software and ModelSim compiling emulator, storage emulation model bank, Matlab excited data, simulation result, write test and excitation Testbench, Matlab software compiles emulator by interfacing expansion module (LinkforModelSim) with ModelSim and is connected, associative simulation is carried out with hardware description language interactive mode or batch mode under Matlab environment, debugging, test and checking work, random series or fault model are embedded in tested designing a model, compiling emulator by ModelSim completes the tested hardware simulation designed a model, ModelSim compiles emulator and is used for the tested functional simulation that designs a model and time stimulatiom, Output simulation result, comprise performance evaluation, waveform comparison, coverage rate is added up, data file derives, and the interface command with Matlab is provided, realize the collaborative simulation with Matlab,
Simulation hardware verification environment comprises simulation hardware authenticating computer, Digital Logic Analyzer and DSP emulator, DSP is wherein had to compile debugging software in simulation hardware authenticating computer, realize writing of the test and excitation under simulation hardware verification environment, simulation hardware authenticating computer is for consulting the typical sequential of each chip in control circuit simultaneously, Digital Logic Analyzer is for observing and recording feature and the waveform of programmable logic device (PLD) and peripheral circuit physical responses signal, DSP emulator is connected with simulation hardware authenticating computer by USB interface, for the compiling of test and excitation under simulation hardware verification environment, upload or download,
(6) in described software emulation verification environment, according to the principle of white-box testing, write test and excitation Testbench, in the test and excitation the Testbench simultaneously fault model in step (3) is embedded into together with the excited data designed in advance in Matlab software, test and excitation Testbench is embedded in the control circuit model to be measured set up in step (4), the process realizing specific function is described by different task schedulings (Task), utilize ModelSim to compile emulator and carry out functional simulation, and wave recording file and coverage rate, thus realize in the ideal situation to the tested collaborative simulation that designs a model and analysis, design constraint is checked comprehensively, and the fault-tolerant ability of programmable logic device (PLD) is checked at software view,
(7) in simulation hardware verification environment, as shown in Figure 5, according to the principle of Black-box Testing, compile debugging software by DSP to programme to dsp chip according to fault model, dsp chip is made to export normal or abnormal control signal, control signal in simulation actual motion environment and the abnormal control signal that may occur, hardware testing excitation is applied in tested programmable logic device (PLD), and utilize Digital Logic Analyzer to observe and record feature and the waveform of programmable logic device (PLD) and peripheral circuit physical responses signal, judge that whether each Implement of Function Module of programmable logic device (PLD) is correct according to response condition, check whether each functional circuit produces misoperation due to exception control logic, realize the dynamic simulation to programmable logic device (PLD) fault and analysis, the reliability of programmable logic device (PLD) is checked with this, resist ability and the antijamming capability of fault,
(8) in software emulation verification environment, application Matlab software carries out functional simulation to programmable logic device (PLD), as shown in Figure 6, utilize the interfacing expansion module in Matlab software (LinkforModelSim) and ModelSim to compile emulator to be connected, random series and fault model are embedded in tested designing a model, compiling emulator by ModelSim completes the tested hardware simulation designed a model, recycling Matlab realistic model emulates the analog hardware in ModelSim, Output simulation result, software emulation result in simulation result and step (6) is compared, in simulation hardware verification environment, the typical sequential of each chip in hardware simulation results in step (7) and control circuit is compared, if software emulation comparative result is consistent with simulation hardware comparative result, then enters step (9), otherwise again revise the design of programmable logic device (PLD), return step (6),
(9) in ModelSim compiling emulator, add net meter file, standard time sequence delayer, design constraint and resources bank and time stimulatiom is carried out to programmable logic device (PLD), generate and record performance Study document; Described net meter file is eda tool by the transformation result of rtl description after comprehensive, and describing the structure of circuit from the angle of logic gate and interconnected relationship thereof, is in general exactly a text following certain fairly simple mark grammer; Comprising deferred message and temporal constraint that standard format writes in standard delay file, is the necessary file of time stimulatiom; Design constraint have expressed the design idea surmounting hardware description language, comprises the temporal characteristics of target devices, also comprises for the instruction of design optimization, I/O programming or physical layout etc.; ModelSim compiles in emulator two kinds of storehouse types, one is work storehouse, the library name of acquiescence is work, another kind is resources bank, all compiled files under comprising current engineering under Work storehouse, resources bank to deposit in work storehouse the resource that compiling file will call, and can be invoked directly as of a user design part.
(10) in simulation hardware verification environment, time sequence information is added in the mode of dsp program in hardware excitation, the characteristic of the control signal that dsp chip is exported changes or reaches critical conditions, utilizes Digital Logic Analyzer to observe and records feature and the waveform of programmable logic device (PLD) and peripheral circuit physical responses signal; The characteristic of control signal comprises retention time and change frequency;
(11) simulation result in the simulation result of step (9) and step (6) is compared, the typical sequential of each chip in the simulation result of step (10) and control circuit is compared, if comparative result is unanimously, then complete the crosslinked emulation testing of the programmable logic device (PLD) of described software-hardware synergism, otherwise again revise the design of programmable logic device (PLD), return step (6), by the comparative analysis to simulation result under two kinds of simulating, verifying environment, continuous amendment design model, the actual parameter of the whole control circuit of Step wise approximation, test result is made finally to reach convergence state, the parameter optimization of realizing circuit design, improve the accuracy and confidence of test.
Embodiment:
Certain model servo controller control circuit structure as shown in Figure 7, dsp chip model is the TMS320F2812 of TI company, CPLD chip model is the IspLSI1032-60LG/883 of Lattice company, bus driver model is JS164245, A/D chip model is AD7658, DA chip model is AD7274, 1553B Bus Interface Chip model is BU61580, wherein CPLD is as logic interfacing device in servo controller, mainly complete reseting logic, electrifying timing sequence controls, external interrupt logic, outside DA/AD converter chip selection logic, data bus is bi-directionally connected, the work such as 1553B bus control logic, it is the critical elements of the logic planning on responsible CPU master control borad between each digital device.This design comprises 6 totally 24 passage A/D converters, 4 totally 8 passage D/A converters, pass through CPLD, by zone0 district 0x2000 ~ 0x3fff spatial mappings of the address space of 1553B bus controller and dsp chip, by zone2 district 0xc0000 ~ 0xdbfff spatial mappings of 24 passage A/D signals and 8 passage D/A signals and dsp chip, dsp chip is read and write to 1553B bus controller, A/D, D/A converter in the mode operating memory headroom.
Reading and writing signal phase and the data latch signal as 1553B bus controller of dsp chip; Handshake makes dsp chip mate with 1553B bus controller by logical inversion; When producing bus interruption or A/D converts signal, produce look-at-me to dsp chip; When needs read-write external devices, gate bus driver, controls direction signal, realizes two-way circulating of data.
According to the requirement of servo controller control circuit 26S Proteasome Structure and Function, comprise reset logic module, electrifying timing sequence control module, AD sheet modeling block, AD interrupt logic, DA sheet modeling block, 1553B bus control logic module, data bus Read-write Catrol logic module in CPLD design, each functional module is quoted by top-level module instantiation.
Apply described soft, the programmable logic device (PLD) that hardware is worked in coordination with is cross-linked emulation test method and carries out simulating, verifying to this CPLD design, VerilogHDL language is utilized to carry out organs weight according to chip design handbook, then build software emulation verification environment, in software emulation verification environment, test and excitation Testbench is write to top-level module, different task is adopted to add excitation respectively to each functional module, and utilize Matlab software to compile emulator by interfacing expansion module (LinkforModelSim) with ModelSim to be connected, add as random disturbance pulse in tested functional module input signal, compile in emulator at ModelSim and complete function and time stimulatiom.
Simulation hardware verification environment is built by servo controller, compile in debugging software (CCS3.3) at DSP and read and write AD respectively in the mode of programming, DA, BU61580, and random interfering signal is added in address bus, the input and output pin of CPLD in control panel is drawn in the mode of lead-in wire, be connected to the input interface of Digital Logic Analyzer 16 passage, realize the monitoring to CPLD input/output signal, what run in Digital Logic Analyzer is windows operating system, and TLAapplication software is installed, run TLAapplication software, record and preserve simulation waveform, complete function and time stimulatiom.
For AD chip selection logic, input signal is respectively dsp chip memory headroom address area chip selection signal i_dsp_xzcs2_n, address bus signal iv_a18 ~ iv_a13, output signal is AD chip selection signal o_ad_cs1_n ~ o_ad_cs6_n, and signal is Low level effective.Functional simulation waveform in software emulation verification environment as shown in Figure 8, dsp chip accesses 6 A/D converters successively, within an interrupt cycle, perform 6 these operations altogether, respectively 24 passages are sampled, burr in figure is the random disturbance pulse added in tested functional module input signal by Matlab software, and the situation of misoperation does not appear in tested output signal due to the introducing of random disturbance pulse, and tested design is correct, reliable;
In simulation hardware verification environment, functional simulation waveform as shown in Figure 9, it is identical that the input/output signal waveform collected in Digital Logic Analyzer and ModelSim compile the waveform that in emulator, waveform viewer collects, and demonstrates the correctness of tested design in actual working environment.
Time stimulatiom waveform in software emulation verification environment as shown in Figure 10, be the time that input signal effectively arrives output signal output between cursor 1,2, be about 24.623ns, and the temporal constraint in this CPLD design is 30ns, therefore meets temporal constraint the time delay of tested functional module.
Time stimulatiom waveform in simulation hardware verification environment as shown in figure 11, be the time that input signal effectively arrives output signal output between cursor 1,2, be about 10ns, be better than the 24.623ns under software emulation verification environment, embody science and the correctness of hardware design on the one hand, under also embodying simulation hardware verification environment on the other hand, carry out the necessity of testing authentication.
The present invention uses in the bullet of multiple double-core hardware structure based on DSP high speed digital signal processor+programmable logic device (PLD) coprocessor, arrow model, test result shows, after applying the present invention, achieve the comprehensive simulation checking of programmable logic device (PLD) function, sequential, accurate Position Design defect, the optimized design of realizing circuit parameter, and testing process is simple, testing efficiency is high, effectively ensure the reliability and security of programmable logic device (PLD), improve the global reliability of control circuit.
The content be not described in detail in instructions of the present invention belongs to the known technology of professional and technical personnel in the field.
Claims (6)
1. the programmable logic device (PLD) that soft and hardware is collaborative is cross-linked an emulation test method, it is characterized in that step is as follows:
(1) circuit structure of the control circuit to be measured comprising programmable logic device (PLD) is determined;
(2) according to the circuit structure of described control circuit to be measured, adopt hardware description language to carry out simulation modeling to the device in control circuit, form simulation model library;
(3) according to the fault type that described control circuit to be measured may occur, corresponding fault model is set up by hardware description language;
(4) according to the simulation model library in the circuit structure in step (1) and step (2), modeling is carried out to described control circuit entirety to be measured, for simulating the mutual and time-delay characteristics of signal between tested programmable logic device (PLD) and peripheral chip;
According to the circuit structure in step (1), build entity control circuit;
(5) software emulation verification environment and simulation hardware verification environment is built; Software emulation verification environment comprises software emulation authenticating computer, Matlab software and ModelSim and compiles emulator; Simulation hardware verification environment comprises simulation hardware authenticating computer, Digital Logic Analyzer and DSP emulator; DSP is had to compile debugging software in simulation hardware authenticating computer;
(6) in described software emulation verification environment, according to the principle of white-box testing, write test and excitation Testbench, in the test and excitation the Testbench simultaneously fault model in step (3) is embedded into together with the excited data designed in advance in Matlab software, test and excitation Testbench is embedded in the control circuit model to be measured set up in step (4), utilize ModelSim to compile emulator and carry out functional simulation, and wave recording file and coverage rate;
(7) in simulation hardware verification environment, according to the principle of Black-box Testing, compile debugging software by DSP to programme to dsp chip according to fault model, dsp chip is made to export normal or abnormal control signal, control signal in simulation actual motion environment and the abnormal control signal that may occur, hardware excitation is applied in tested programmable logic device (PLD), and utilizes Digital Logic Analyzer to observe and record feature and the waveform of programmable logic device (PLD) and peripheral circuit physical responses signal;
(8) in software emulation verification environment, application Matlab software carries out functional simulation to programmable logic device (PLD), software emulation result in simulation result and step (6) is compared, in simulation hardware verification environment, the typical sequential of each chip in the hardware simulation results in step (7) and control circuit is compared; If software emulation comparative result is consistent with simulation hardware comparative result, then enters step (9), otherwise again revise the design of programmable logic device (PLD), return step (6);
(9) in ModelSim compiling emulator, add net meter file, standard time sequence delayer, design constraint and resources bank and time stimulatiom is carried out to programmable logic device (PLD), generate and record performance Study document;
(10) in simulation hardware verification environment, time sequence information is added in the mode of dsp program in hardware excitation, the characteristic of the control signal that dsp chip is exported changes or reaches critical conditions, utilizes Digital Logic Analyzer to observe and records feature and the waveform of programmable logic device (PLD) and peripheral circuit physical responses signal;
(11) simulation result in the simulation result of step (9) and step (6) is compared, the typical sequential of each chip in the simulation result of step (10) and control circuit is compared, if comparative result is unanimously, then complete the crosslinked emulation testing of the programmable logic device (PLD) of described software-hardware synergism, otherwise again revise the design of programmable logic device (PLD), return step (6).
2. the programmable logic device (PLD) that a kind of soft and hardware according to claim 1 is collaborative is cross-linked emulation test method, it is characterized in that: described control circuit to be measured comprises dsp chip, programmable logic device (PLD), power reset chip, the first clock circuit, second clock circuit, a JTEG circuit, the 2nd JTEG circuit, bus driver, 1553B Bus Interface Chip, analog to digital converter ADC and digital to analog converter DAC;
First clock circuit provides clock signal for dsp chip, second clock circuit provides clock signal for 1553B bus protocol chip, power reset chip provides power supply for whole control circuit to be measured, and for programmable logic device (PLD) provides reset signal, this reset signal is distributed to dsp chip after programmable logic device (PLD) filtering process, 1553B Bus Interface Chip and digital to analog converter ADC, DSP address bus and programmable logic device (PLD), 1553B bus protocol chip is direct-connected, data bus through bus driver isolation after with 1553B bus protocol chip, digital to analog converter DAC, analog to digital converter ADC connects, dsp chip exports control signal to programmable logic device (PLD), 1553B bus protocol chip is exported to after programmable logic device (PLD) logical process, digital to analog converter DAC, analog to digital converter ADC and bus driver chip, carry out the sequential control of data transmission, one JTEG circuit is connected to dsp chip, and the 2nd JTEG circuit is connected to programmable logic device (PLD).
3. the programmable logic device (PLD) that a kind of soft and hardware according to claim 1 and 2 is collaborative is cross-linked emulation test method, it is characterized in that: described programmable logic device (PLD) is CPLD chip or fpga chip.
4. the programmable logic device (PLD) that a kind of soft and hardware according to claim 1 is collaborative is cross-linked emulation test method, it is characterized in that: described hardware description language is VerilogHDL, VHDL or SystemC.
5. the programmable logic device (PLD) that a kind of soft and hardware according to claim 1 is collaborative is cross-linked emulation test method, it is characterized in that: the fault type that described control circuit to be measured may occur comprises:
Exist periodically or randomness undesired signal in the control signal that a, programmable logic device (PLD) export;
Exist periodically or randomness undesired signal in the control signal that b, dsp chip export;
The control signal that c, programmable logic device (PLD) export is lost or was lost efficacy;
The control signal retention time that d, programmable logic device (PLD) export is too short, cannot reach the response demand of peripheral components;
The change frequency of the control signal that e, programmable logic device (PLD) export is too high, exceeds the processing power of peripheral components;
The change frequency of the control signal that f, dsp chip export is too high, exceeds the processing power of programmable logic device (PLD).
6. the programmable logic device (PLD) that a kind of soft and hardware according to claim 1 is collaborative is cross-linked emulation test method, it is characterized in that: in described step (10), the characteristic of control signal comprises retention time and change frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510680633.6A CN105302950B (en) | 2015-10-19 | 2015-10-19 | A kind of programmable logic device crosslinking emulation test method of soft and hardware collaboration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510680633.6A CN105302950B (en) | 2015-10-19 | 2015-10-19 | A kind of programmable logic device crosslinking emulation test method of soft and hardware collaboration |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105302950A true CN105302950A (en) | 2016-02-03 |
| CN105302950B CN105302950B (en) | 2018-07-24 |
Family
ID=55200218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510680633.6A Active CN105302950B (en) | 2015-10-19 | 2015-10-19 | A kind of programmable logic device crosslinking emulation test method of soft and hardware collaboration |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105302950B (en) |
Cited By (54)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105807631A (en) * | 2016-03-08 | 2016-07-27 | 北京工业大学 | PLC simulation-based industrial control intrusion detection method and intrusion detection system |
| CN106095691A (en) * | 2016-06-28 | 2016-11-09 | 国营芜湖机械厂 | A kind of software replacement method of testing being applied to airborne processor module |
| CN106528911A (en) * | 2016-09-14 | 2017-03-22 | 西安电子科技大学 | Apparatus for building VHDL-AMS simulation model of power supply |
| CN106682370A (en) * | 2017-02-28 | 2017-05-17 | 郑州云海信息技术有限公司 | Simulation verification system |
| CN106682374A (en) * | 2017-03-17 | 2017-05-17 | 北京润科通用技术有限公司 | Analog simulation method and system of working time sequence |
| CN106934121A (en) * | 2016-12-30 | 2017-07-07 | 北京华大九天软件有限公司 | A kind of method for testing device model emulation result correctness |
| WO2018023363A1 (en) * | 2016-08-02 | 2018-02-08 | 邹霞 | Fault simulation system |
| CN107885925A (en) * | 2017-11-03 | 2018-04-06 | 中国电子科技集团公司第五十四研究所 | A kind of register testing method of EDA Qualify Phases |
| CN108170902A (en) * | 2017-12-07 | 2018-06-15 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of hardware model detection method |
| CN108227607A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method of simplified circuit board arrangement circuit |
| CN108337142A (en) * | 2018-01-18 | 2018-07-27 | 中国科学院国家空间科学中心 | A kind of synchronous high-speed 1553B bus systems |
| CN108563545A (en) * | 2018-04-11 | 2018-09-21 | 北京计算机技术及应用研究所 | A kind of the SOPC function verification methods and system of Coverage- Driven software-hardware synergism |
| CN108959103A (en) * | 2018-07-31 | 2018-12-07 | 西安电子科技大学 | Method for testing software based on BWDSP library function |
| CN108984945A (en) * | 2018-08-03 | 2018-12-11 | 北京智芯微电子科技有限公司 | The simulation and verification platform of design is verified based on multi-core associative simulation |
| CN109189619A (en) * | 2018-08-13 | 2019-01-11 | 光梓信息科技（上海）有限公司 | I2C bus compatible test method, system, storage medium and equipment |
| CN109637312A (en) * | 2019-01-28 | 2019-04-16 | 安徽师范大学 | A kind of on piece Digital Electronics Experiment system |
| CN109669434A (en) * | 2018-11-13 | 2019-04-23 | 昆山优尼电能运动科技有限公司 | Unmanned plane automated testing method and system |
| CN109857608A (en) * | 2018-12-27 | 2019-06-07 | 深圳云天励飞技术有限公司 | Micro-processor verification method, apparatus, electronic equipment and computer readable storage medium |
| CN109977437A (en) * | 2017-12-27 | 2019-07-05 | 长鑫存储技术有限公司 | Verification method, device, equipment and the computer readable storage medium of transistor level circuitry |
| CN109992462A (en) * | 2017-12-29 | 2019-07-09 | 北京中科寒武纪科技有限公司 | Verify excitation producing method, device, chip verification method and system |
| CN110059395A (en) * | 2019-04-12 | 2019-07-26 | 云南师范大学 | A kind of infrared imaging focuses the visuable debugging method of FPGA system automatically |
| CN110471810A (en) * | 2019-08-21 | 2019-11-19 | 山东浪潮人工智能研究院有限公司 | A kind of method and system recording Logical Design Engineering Task state |
| CN110516334A (en) * | 2019-08-16 | 2019-11-29 | 浪潮电子信息产业股份有限公司 | Convolutional calculation emulation test method, device and relevant device based on hardware environment |
| CN110632857A (en) * | 2019-09-25 | 2019-12-31 | 中国工程物理研究院计算机应用研究所 | Control performance verification method for large-scale hierarchical control system |
| CN110674616A (en) * | 2019-09-19 | 2020-01-10 | 北京智联安科技有限公司 | Systemverilog and Matlab algorithm based extensible full-random full-automatic verification method |
| CN110672898A (en) * | 2019-11-08 | 2020-01-10 | 航天柏克(广东)科技有限公司 | Digital control fault waveform capturing and analyzing method |
| CN111027108A (en) * | 2019-08-13 | 2020-04-17 | 哈尔滨安天科技集团股份有限公司 | Sequential logic safety detection method and device of low-speed synchronous serial bus |
| CN111081401A (en) * | 2019-11-26 | 2020-04-28 | 中广核工程有限公司 | Nuclear power station reactor control debugging method |
| CN111176978A (en) * | 2018-11-09 | 2020-05-19 | 通用电气航空系统有限公司 | Tool verification system and method for verifying rejected parts |
| CN111273156A (en) * | 2020-02-24 | 2020-06-12 | 江苏传艺科技股份有限公司 | Online test system for GaN millimeter wave power amplifier chip |
| CN111366841A (en) * | 2020-04-07 | 2020-07-03 | 华北水利水电大学 | FPGA programmable logic unit test equipment and use method |
| CN111639470A (en) * | 2020-05-28 | 2020-09-08 | 山东云海国创云计算装备产业创新中心有限公司 | Simulation test method and system for processor cooperative chip and related components |
| CN111985179A (en) * | 2020-08-26 | 2020-11-24 | 上海磐启微电子有限公司 | Design verification system and method for wireless communication chip |
| CN112100954A (en) * | 2020-08-31 | 2020-12-18 | 北京百度网讯科技有限公司 | Method and device for verifying chip and computer storage medium |
| CN112232000A (en) * | 2020-10-23 | 2021-01-15 | 海光信息技术股份有限公司 | Authentication system, authentication method and authentication device spanning multiple authentication domains |
| CN112329366A (en) * | 2020-12-04 | 2021-02-05 | 国微集团(深圳)有限公司 | SOC (system on chip) system verification method, device and system for improving simulation efficiency |
| CN112612241A (en) * | 2020-12-15 | 2021-04-06 | 中国航空综合技术研究所 | Safety analysis method for software of field programmable logic device of aviation equipment |
| CN112945602A (en) * | 2021-03-17 | 2021-06-11 | 广东美的暖通设备有限公司 | Air conditioner self-learning software and hardware combined test system |
| CN113032203A (en) * | 2021-03-24 | 2021-06-25 | 方湘艳 | Programmable logic device accelerated testing device and method |
| CN113064819A (en) * | 2021-03-26 | 2021-07-02 | 山东英信计算机技术有限公司 | Software development testing method, system, equipment and medium |
| CN113064816A (en) * | 2021-03-16 | 2021-07-02 | 中国人民解放军32180部队 | Testing device and testing method for programmable logic device software |
| CN113392605A (en) * | 2021-03-22 | 2021-09-14 | 江苏华创微系统有限公司 | Refined physical design method suitable for high-performance DSP core time sequence convergence |
| CN113704043A (en) * | 2021-08-30 | 2021-11-26 | 地平线(上海)人工智能技术有限公司 | Chip function verification method and device, readable storage medium and electronic equipment |
| CN113807037A (en) * | 2021-10-13 | 2021-12-17 | 芯河半导体科技(无锡)有限公司 | Software and hardware collaborative simulation system supporting SOC design full-process development |
| CN113868068A (en) * | 2021-12-01 | 2021-12-31 | 统信软件技术有限公司 | Kernel performance testing method, computing device and storage medium |
| CN114330178A (en) * | 2021-12-28 | 2022-04-12 | 杭州朗迅科技有限公司 | Drive system for debugging and verifying embedded hardware circuit |
| CN114707444A (en) * | 2022-02-09 | 2022-07-05 | 芯华章科技股份有限公司 | Method for compiling verification system, electronic equipment and storage medium |
| CN114896931A (en) * | 2022-05-12 | 2022-08-12 | 北京联盛德微电子有限责任公司 | Bluetooth transceiving path verification method and system based on handshake mechanism |
| CN115114875A (en) * | 2022-08-31 | 2022-09-27 | 沐曦科技(北京)有限公司 | Universal chip verification device for simulation |
| CN115659885A (en) * | 2022-12-29 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | System and method for simulation test |
| CN115994096A (en) * | 2023-03-21 | 2023-04-21 | 安徽隼波科技有限公司 | Verification method for radar signal processing and simulation |
| CN117113890A (en) * | 2023-10-23 | 2023-11-24 | 深圳安森德半导体有限公司 | CPU chip design method and system |
| CN117436391A (en) * | 2023-12-21 | 2024-01-23 | 四川思凌科微电子有限公司 | Method for joint simulation of algorithm and hardware |
| CN118261112A (en) * | 2024-04-17 | 2024-06-28 | 山东工程职业技术大学 | Visual mathematical modeling system and method based on circuit design |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6678645B1 (en) * | 1999-10-28 | 2004-01-13 | Advantest Corp. | Method and apparatus for SoC design validation |
| CN101499937A (en) * | 2009-03-16 | 2009-08-05 | 盛科网络（苏州）有限公司 | Software and hardware collaborative simulation verification system and method based on FPGA |
| CN104346272A (en) * | 2013-07-24 | 2015-02-11 | 无锡华润微电子有限公司 | Automatic chip simulative testing system |
-
2015
- 2015-10-19 CN CN201510680633.6A patent/CN105302950B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6678645B1 (en) * | 1999-10-28 | 2004-01-13 | Advantest Corp. | Method and apparatus for SoC design validation |
| CN101499937A (en) * | 2009-03-16 | 2009-08-05 | 盛科网络（苏州）有限公司 | Software and hardware collaborative simulation verification system and method based on FPGA |
| CN104346272A (en) * | 2013-07-24 | 2015-02-11 | 无锡华润微电子有限公司 | Automatic chip simulative testing system |
Cited By (77)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105807631A (en) * | 2016-03-08 | 2016-07-27 | 北京工业大学 | PLC simulation-based industrial control intrusion detection method and intrusion detection system |
| CN106095691A (en) * | 2016-06-28 | 2016-11-09 | 国营芜湖机械厂 | A kind of software replacement method of testing being applied to airborne processor module |
| WO2018023363A1 (en) * | 2016-08-02 | 2018-02-08 | 邹霞 | Fault simulation system |
| CN106528911A (en) * | 2016-09-14 | 2017-03-22 | 西安电子科技大学 | Apparatus for building VHDL-AMS simulation model of power supply |
| CN106528911B (en) * | 2016-09-14 | 2019-10-25 | 西安电子科技大学 | A kind of device for establishing power supply VHDL-AMS simulation model |
| CN108227607A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method of simplified circuit board arrangement circuit |
| CN106934121A (en) * | 2016-12-30 | 2017-07-07 | 北京华大九天软件有限公司 | A kind of method for testing device model emulation result correctness |
| CN106934121B (en) * | 2016-12-30 | 2020-02-18 | 北京华大九天软件有限公司 | Method for testing correctness of simulation result of device model |
| CN106682370A (en) * | 2017-02-28 | 2017-05-17 | 郑州云海信息技术有限公司 | Simulation verification system |
| CN106682370B (en) * | 2017-02-28 | 2020-07-28 | 苏州浪潮智能科技有限公司 | Simulation verification system |
| CN106682374A (en) * | 2017-03-17 | 2017-05-17 | 北京润科通用技术有限公司 | Analog simulation method and system of working time sequence |
| CN107885925B (en) * | 2017-11-03 | 2021-06-29 | 中国电子科技集团公司第五十四研究所 | Register testing method in EDA (electronic design automation) verification stage |
| CN107885925A (en) * | 2017-11-03 | 2018-04-06 | 中国电子科技集团公司第五十四研究所 | A kind of register testing method of EDA Qualify Phases |
| CN108170902B (en) * | 2017-12-07 | 2021-07-16 | 中国航空工业集团公司西安航空计算技术研究所 | Hardware model detection method |
| CN108170902A (en) * | 2017-12-07 | 2018-06-15 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of hardware model detection method |
| CN109977437A (en) * | 2017-12-27 | 2019-07-05 | 长鑫存储技术有限公司 | Verification method, device, equipment and the computer readable storage medium of transistor level circuitry |
| CN109992462A (en) * | 2017-12-29 | 2019-07-09 | 北京中科寒武纪科技有限公司 | Verify excitation producing method, device, chip verification method and system |
| CN108337142A (en) * | 2018-01-18 | 2018-07-27 | 中国科学院国家空间科学中心 | A kind of synchronous high-speed 1553B bus systems |
| CN108563545A (en) * | 2018-04-11 | 2018-09-21 | 北京计算机技术及应用研究所 | A kind of the SOPC function verification methods and system of Coverage- Driven software-hardware synergism |
| CN108563545B (en) * | 2018-04-11 | 2021-06-08 | 北京计算机技术及应用研究所 | SOPC function verification method and system with coverage rate driving software and hardware in cooperation |
| CN108959103A (en) * | 2018-07-31 | 2018-12-07 | 西安电子科技大学 | Method for testing software based on BWDSP library function |
| CN108984945A (en) * | 2018-08-03 | 2018-12-11 | 北京智芯微电子科技有限公司 | The simulation and verification platform of design is verified based on multi-core associative simulation |
| CN109189619A (en) * | 2018-08-13 | 2019-01-11 | 光梓信息科技（上海）有限公司 | I2C bus compatible test method, system, storage medium and equipment |
| CN111176978B (en) * | 2018-11-09 | 2023-09-29 | 通用电气航空系统有限公司 | Tool verification system and method for verifying failed components |
| CN111176978A (en) * | 2018-11-09 | 2020-05-19 | 通用电气航空系统有限公司 | Tool verification system and method for verifying rejected parts |
| CN109669434A (en) * | 2018-11-13 | 2019-04-23 | 昆山优尼电能运动科技有限公司 | Unmanned plane automated testing method and system |
| CN109857608A (en) * | 2018-12-27 | 2019-06-07 | 深圳云天励飞技术有限公司 | Micro-processor verification method, apparatus, electronic equipment and computer readable storage medium |
| CN109637312A (en) * | 2019-01-28 | 2019-04-16 | 安徽师范大学 | A kind of on piece Digital Electronics Experiment system |
| CN110059395A (en) * | 2019-04-12 | 2019-07-26 | 云南师范大学 | A kind of infrared imaging focuses the visuable debugging method of FPGA system automatically |
| CN111027108B (en) * | 2019-08-13 | 2024-02-13 | 安天科技集团股份有限公司 | Sequential logic safety detection method and device for low-speed synchronous serial bus |
| CN111027108A (en) * | 2019-08-13 | 2020-04-17 | 哈尔滨安天科技集团股份有限公司 | Sequential logic safety detection method and device of low-speed synchronous serial bus |
| CN110516334A (en) * | 2019-08-16 | 2019-11-29 | 浪潮电子信息产业股份有限公司 | Convolutional calculation emulation test method, device and relevant device based on hardware environment |
| CN110471810A (en) * | 2019-08-21 | 2019-11-19 | 山东浪潮人工智能研究院有限公司 | A kind of method and system recording Logical Design Engineering Task state |
| CN110471810B (en) * | 2019-08-21 | 2023-08-22 | 山东浪潮科学研究院有限公司 | Method and system for recording working state of digital logic design engineering |
| CN110674616A (en) * | 2019-09-19 | 2020-01-10 | 北京智联安科技有限公司 | Systemverilog and Matlab algorithm based extensible full-random full-automatic verification method |
| CN110632857B (en) * | 2019-09-25 | 2022-05-17 | 中国工程物理研究院计算机应用研究所 | Control performance verification method for large-scale hierarchical control system |
| CN110632857A (en) * | 2019-09-25 | 2019-12-31 | 中国工程物理研究院计算机应用研究所 | Control performance verification method for large-scale hierarchical control system |
| CN110672898B (en) * | 2019-11-08 | 2022-07-08 | 航天柏克(广东)科技有限公司 | Digital control fault waveform capturing and analyzing method |
| CN110672898A (en) * | 2019-11-08 | 2020-01-10 | 航天柏克(广东)科技有限公司 | Digital control fault waveform capturing and analyzing method |
| CN111081401A (en) * | 2019-11-26 | 2020-04-28 | 中广核工程有限公司 | Nuclear power station reactor control debugging method |
| CN111081401B (en) * | 2019-11-26 | 2022-03-15 | 中广核工程有限公司 | Nuclear power station reactor control debugging method |
| CN111273156A (en) * | 2020-02-24 | 2020-06-12 | 江苏传艺科技股份有限公司 | Online test system for GaN millimeter wave power amplifier chip |
| CN111273156B (en) * | 2020-02-24 | 2022-01-11 | 江苏传艺科技股份有限公司 | Online test system for GaN millimeter wave power amplifier chip |
| CN111366841A (en) * | 2020-04-07 | 2020-07-03 | 华北水利水电大学 | FPGA programmable logic unit test equipment and use method |
| CN111639470B (en) * | 2020-05-28 | 2022-06-17 | 山东云海国创云计算装备产业创新中心有限公司 | Simulation test method and system for processor cooperative chip and related components |
| CN111639470A (en) * | 2020-05-28 | 2020-09-08 | 山东云海国创云计算装备产业创新中心有限公司 | Simulation test method and system for processor cooperative chip and related components |
| CN111985179A (en) * | 2020-08-26 | 2020-11-24 | 上海磐启微电子有限公司 | Design verification system and method for wireless communication chip |
| CN112100954A (en) * | 2020-08-31 | 2020-12-18 | 北京百度网讯科技有限公司 | Method and device for verifying chip and computer storage medium |
| CN112232000A (en) * | 2020-10-23 | 2021-01-15 | 海光信息技术股份有限公司 | Authentication system, authentication method and authentication device spanning multiple authentication domains |
| CN112329366A (en) * | 2020-12-04 | 2021-02-05 | 国微集团(深圳)有限公司 | SOC (system on chip) system verification method, device and system for improving simulation efficiency |
| CN112612241A (en) * | 2020-12-15 | 2021-04-06 | 中国航空综合技术研究所 | Safety analysis method for software of field programmable logic device of aviation equipment |
| CN112612241B (en) * | 2020-12-15 | 2021-09-28 | 中国航空综合技术研究所 | Safety analysis method for software of field programmable logic device of aviation equipment |
| CN113064816A (en) * | 2021-03-16 | 2021-07-02 | 中国人民解放军32180部队 | Testing device and testing method for programmable logic device software |
| CN113064816B (en) * | 2021-03-16 | 2022-11-04 | 中国人民解放军32180部队 | Testing device and testing method for programmable logic device software |
| CN112945602A (en) * | 2021-03-17 | 2021-06-11 | 广东美的暖通设备有限公司 | Air conditioner self-learning software and hardware combined test system |
| CN113392605B (en) * | 2021-03-22 | 2023-06-13 | 江苏华创微系统有限公司 | Fine physical design method suitable for high-performance DSP (digital Signal processor) core timing sequence convergence |
| CN113392605A (en) * | 2021-03-22 | 2021-09-14 | 江苏华创微系统有限公司 | Refined physical design method suitable for high-performance DSP core time sequence convergence |
| CN113032203A (en) * | 2021-03-24 | 2021-06-25 | 方湘艳 | Programmable logic device accelerated testing device and method |
| CN113032203B (en) * | 2021-03-24 | 2023-02-14 | 方湘艳 | Programmable logic device accelerated testing device and method |
| CN113064819A (en) * | 2021-03-26 | 2021-07-02 | 山东英信计算机技术有限公司 | Software development testing method, system, equipment and medium |
| CN113704043A (en) * | 2021-08-30 | 2021-11-26 | 地平线(上海)人工智能技术有限公司 | Chip function verification method and device, readable storage medium and electronic equipment |
| CN113807037A (en) * | 2021-10-13 | 2021-12-17 | 芯河半导体科技(无锡)有限公司 | Software and hardware collaborative simulation system supporting SOC design full-process development |
| CN113868068A (en) * | 2021-12-01 | 2021-12-31 | 统信软件技术有限公司 | Kernel performance testing method, computing device and storage medium |
| CN114330178A (en) * | 2021-12-28 | 2022-04-12 | 杭州朗迅科技有限公司 | Drive system for debugging and verifying embedded hardware circuit |
| CN114707444A (en) * | 2022-02-09 | 2022-07-05 | 芯华章科技股份有限公司 | Method for compiling verification system, electronic equipment and storage medium |
| CN114896931B (en) * | 2022-05-12 | 2023-09-01 | 北京联盛德微电子有限责任公司 | Verification method and system for Bluetooth transceiving path based on handshake mechanism |
| CN114896931A (en) * | 2022-05-12 | 2022-08-12 | 北京联盛德微电子有限责任公司 | Bluetooth transceiving path verification method and system based on handshake mechanism |
| CN115114875B (en) * | 2022-08-31 | 2022-11-04 | 沐曦科技(北京)有限公司 | Universal chip verification device for simulation |
| CN115114875A (en) * | 2022-08-31 | 2022-09-27 | 沐曦科技(北京)有限公司 | Universal chip verification device for simulation |
| CN115659885A (en) * | 2022-12-29 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | System and method for simulation test |
| CN115994096B (en) * | 2023-03-21 | 2023-06-09 | 安徽隼波科技有限公司 | Verification method for radar signal processing and simulation |
| CN115994096A (en) * | 2023-03-21 | 2023-04-21 | 安徽隼波科技有限公司 | Verification method for radar signal processing and simulation |
| CN117113890A (en) * | 2023-10-23 | 2023-11-24 | 深圳安森德半导体有限公司 | CPU chip design method and system |
| CN117113890B (en) * | 2023-10-23 | 2024-02-06 | 深圳安森德半导体有限公司 | CPU chip design method and system |
| CN117436391A (en) * | 2023-12-21 | 2024-01-23 | 四川思凌科微电子有限公司 | Method for joint simulation of algorithm and hardware |
| CN117436391B (en) * | 2023-12-21 | 2024-03-26 | 四川思凌科微电子有限公司 | Method for joint simulation of algorithm and hardware |
| CN118261112A (en) * | 2024-04-17 | 2024-06-28 | 山东工程职业技术大学 | Visual mathematical modeling system and method based on circuit design |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105302950B (en) | 2018-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105302950B (en) | A kind of programmable logic device crosslinking emulation test method of soft and hardware collaboration | |
| CN109684681B (en) | High-level verification method using UVM verification platform | |
| US12001317B2 (en) | Waveform based reconstruction for emulation | |
| US8352235B1 (en) | Emulation of power shutoff behavior for integrated circuits | |
| CN104899076B (en) | A kind of accelerated method of super large-scale integration gate level netlist emulation | |
| CN103616825B (en) | A kind of low cost semi-physical self-adaption clock virtual microgrid test platform | |
| CN102782651B (en) | The hybrid concurrent and serial logic emulation of hardware designs | |
| CN104598373B (en) | A kind of embedded software test method of multi-technical fusion | |
| CN102521444A (en) | Cooperative simulation/verification method and device for software and hardware | |
| US10521547B2 (en) | Covergroup network analysis | |
| CN108038328A (en) | Chip automatic simulation verifies system | |
| US8265918B1 (en) | Simulation and emulation of a circuit design | |
| CN107533473A (en) | Efficient wave for emulation generates | |
| US10614193B2 (en) | Power mode-based operational capability-aware code coverage | |
| Cheng et al. | A run-time RTL debugging methodology for FPGA-based co-simulation | |
| Gao et al. | Software and hardware co-verification technology based on virtual prototyping of RF SOC | |
| CN207037640U (en) | Simulating, verifying detecting and analysing system | |
| Zheng et al. | The methods of FPGA software verification | |
| US8145466B1 (en) | Clustering of electronic circuit design modules for hardware-based and software-based co-simulation platforms | |
| Bombieri et al. | Hybrid, incremental assertion-based verification for TLM design flows | |
| CN104636509A (en) | Method for verifying timing problem in gate-level simulation | |
| CN112613200A (en) | FPGA-based Petri network simulation platform | |
| US20230409788A1 (en) | Synchronizing distributed simulations of a circuit design | |
| Bhattacharya et al. | Advanced verification topics | |
| Rahmouni et al. | Design of a medium voltage protection device using system simulation approaches: a case study |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |