CN111366841A - FPGA programmable logic unit test equipment and use method - Google Patents

Abstract

The invention aims to provide FPGA programmable logic unit test equipment and a using method thereof, which are used for carrying out full coverage test on functions and performance of a CLB in an FPGA chip and realizing low cost and miniaturization of a test system, and a 3U PCIE power module is integrated in an industrial personal computer as a controllable power supply for power supply parameter test when the CLB of an FPGA to be tested is tested based on a PCIE industrial personal computer platform; the 3U PCIE oscilloscope module tests CLB alternating current-direct current simulation parameters; integrating an error code test module in an excitation FPGA on a CLB test onboard hardware platform to meet the CLB function test requirement; the variable clock is generated by exciting the clock module in the FPGA, the requirement on the reference clock during the CLB test is met, so that the full-function and full-performance test of the CLB on the FPGA is completed, and the low cost and miniaturization of the test are realized.

Description

FPGA programmable logic unit test equipment and use method

Technical Field

The invention belongs to the field of FPGA (field programmable gate array) testing, and particularly relates to FPGA programmable logic unit testing equipment and a using method thereof.

Background

More than 90% of the logic functions in an FPGA are performed by the CLB. The programmable logic unit test comprises a function test and a performance test, and the function test of the CLB comprises the following steps: LUT (16-bit register, SRLC 16) functional testing in SLICEM, distributed RAM and memory (single port 32X 1-bit RAM, dual port 16X 2-bit RAM) functional testing in SLICEM, read only memory (ROM 128X 1) functional testing, flip-flops (D flip-flops/level latches), carry chain testing, SRL cascade testing, and the like. The performance test comprises a direct current parameter test, an alternating current parameter test and a limit parameter test of all functions working normally.

Generally, after the FPGA chip is subjected to flow back, the FPGA chip needs to be subjected to full coverage testing of functions and performances, the testing of the chip is an important link in the design and production of the FPGA chip, and the testing of the chip has various schemes, such as building a circuit board to connect a special testing instrument to perform the function and performance testing in a specific aspect, using a professional automatic tester ATE to perform the testing, or using the FPGA to connect the chip to perform the testing, and the like.

The test items included in the CLB test of the FPGA are: the method comprises the steps that a shift register, a D trigger, the maximum working frequency and the module power consumption are required to be tested, each item needs to be tested on two aspects of functions and performance, except for function testing, alternating current parameters in the performance testing, such as rise time, fall time and transmission delay time, are more concerned by designers, and because the design principle of an ATE (automatic test equipment) testing alternating current and direct current parameter is that a comparator is adopted to judge testing parameters and cannot meet the requirements of CLB (clock line bus) alternating current and direct current parameter testing, ATE is a comparator, a space range is given, a judgment result is output, and a determined value is not directly measured, direct alternating current and direct current parameters of CLB cannot be directly tested. The full-function and full-performance testing of the CLB can be completely covered by adopting a separation testing instrument at the stage. But at the same time, in order to completely test the function and the performance of the CLB, the FPGA case needs to be repeatedly downloaded, different parameters need to be tested, and different test instruments need to be selected for testing. The CLB test method has the problems of overlong test time, complex wiring and overhigh test cost during the CLB test.

Disclosure of Invention

The invention aims to provide FPGA programmable logic unit test equipment and a use method thereof, which are used for carrying out full coverage test on functions and performances of a CLB in an FPGA chip and realizing low cost and miniaturization of a test system.

The technical scheme for solving the technical problems of the invention is as follows: an FPGA programmable logic unit test device comprises an NI PCIE industrial personal computer, a power module for CLB power bias test, dynamic and static power consumption test, an oscilloscope module for CLB alternating current time parameter test, a CLB test board-mounted hardware platform, a board-mounted power supply, an excitation FPGA, an active crystal oscillator, a DDR3 cache and an FPGA to be tested, wherein the output end of the NI PCIE industrial personal computer is connected with the input end of the CLB test board-mounted hardware platform, the board-mounted power supply, the excitation FPGA, the active crystal oscillator, the DDR3 cache and the FPGA to be tested are arranged on the CLB test board-mounted hardware platform and connected with the CLB test board-mounted hardware platform, the board-mounted power supply provides power for circuits on the whole CLB test board-mounted hardware platform except the FPGA to be tested, the input end of the power module is connected with the output end of the NI PCIE industrial personal computer, and the output end of the power module is, the input end of the oscilloscope module is connected with the output end of the FPGA to be tested, and the output end of the oscilloscope module is connected with the input end of the NI PCIE industrial personal computer.

In order to be not limited to the internal space of the industrial personal computer and facilitate testing, the output end of the NI PCIE industrial personal computer is connected with the input end of the CLB test board-mounted hardware platform through a PCIE extension line.

In order to test a plurality of tested FPGAs simultaneously, the output end of the NI PCIE industrial personal computer is connected with the input ends of a plurality of CLB test board-mounted hardware platforms, and at most 4 CLB test platforms are simultaneously supported.

In order to test a plurality of to-be-tested FPGAs simultaneously, the CLB test board-mounted hardware platform is connected with the plurality of to-be-tested FPGAs simultaneously, and 4 test clamps are installed on at most one test platform.

The power module is a 3U PCIE 4X power module, provides a required power supply for the FPGA to be tested on the CLB test board-mounted hardware platform, comprises 1.2V, 1.0V, 3.3V and 2.5V, controls the power supply power-up sequence of the FPGA to be tested through software configuration, adjusts the power supply deviation, performs bias test on different power supplies, and can test the normal power supply working range of the CLB module. The power supply module is connected with a power supply interface of the FPGA module to be tested through a security connecting line.

The oscilloscope module is a 3U PCIE 4X oscilloscope module, tests of alternating current parameters are achieved, and tests of characteristic parameters and the like of the CLB in time domains such as transmission delay, signal rising and falling time and the like under various logic combination functions are achieved through programming.

In order to reduce loss and facilitate impedance matching, the oscilloscope module is connected with a CLB test board-mounted hardware platform through an SMA low-loss coaxial cable.

The excitation FPGA comprises a PCIE IP core module for generating and processing a transmission layer data packet, flow control management, initialization, power management, data protection, error check and retry, serialization and deserialization, a PCIE APP module for transmitting the data of the object layer and configuring spatial information, an address bus for decoding the PCIE APP module, an address coding module for generating different address chip selection signals, a clock module for generating a frequency-adjustable excitation clock by using clock hardmac resources inside the excitation FPGA, a CLB test FPGA state machine module for analyzing a CPU control command, a DDR3 cache, a DDR3 control module for realizing the cache of a to-be-tested FPGA test case, and a DDR test module for generating and receiving error codes, wherein the error code test module comprises an error code generating module, an error code receiving module and a main string configuration controller module for saving IO pins of the excitation FPGA, And the test vector generation module is used for generating input test vectors required by the test cases.

A use method of FPGA programmable logic unit test equipment is characterized by comprising the following steps:

s1: initializing an NI PCIE industrial personal computer, initializing a power supply module, closing a power supply of an FPGA to be tested, initializing an oscilloscope module, setting the oscilloscope module to be in a direct-current coupling mode, wherein the input impedance is 1M, and an automatic test mode is adopted;

s2: setting items to be tested, and selecting a corresponding test case to download to a DDR3 chip exciting the FPGA;

s3: setting a power supply module to output 1.2V, 1.0V, 1.8V, 3.3V and 2.5V power supplies required by the FPGA to be tested, and setting a trigger level and sampling frequency of an oscilloscope module;

s4: testing the selected items of the FPGA to be tested;

s4.1: the method comprises the steps of performing function test of a selected item on an FPGA to be tested, exciting the FPGA to configure a test case in a DDR3 cache to an FPGA chip to be tested in a serial mode, then sending a control command through an NI PCIE industrial personal computer, controlling a clock module in the excited FPGA to generate a specific frequency clock according to test requirements, outputting a serial sequence after the sequence is processed in the test case of the FPGA to be tested by taking a PRBS sequence generated by an error code generation module of an error code test module as excitation input of the FPGA to be tested under the clock frequency, outputting the serial sequence to an error code receiving module of the error code test module, and determining whether the function test under the frequency is passed or not by whether the error code exists in the error code test module within a user-defined time period;

s4.2: performing performance test of the selected items on the FPGA to be tested;

s4.2.1: the method comprises the steps that performance testing of the maximum working frequency of a selected project is conducted on an FPGA to be tested, an excitation FPGA configures a test case in a DDR3 cache to the FPGA to be tested in a serial mode, then a control command is sent through an NI PCIE industrial personal computer, a clock module in the excitation FPGA is controlled to generate different clocks according to testing requirements, the clocks are halved according to maximum frequency design indexes, under the clock frequency, a PRBS sequence is generated by an error code generation module of an error code testing module and serves as excitation input of the FPGA to be tested, the sequence is output to an error code receiving module of the error code testing module after the FPGA test case to be tested is processed, and whether the function testing under the frequency is passed or not is determined through whether the error code testing module has the error code in a user;

s4.2.2, performing performance test on the output delay time, duty ratio, output rise time and output fall time of the selected items on the tested FPGA, configuring a test case in a DDR3 cache to the FPGA to be tested by the excitation FPGA in a serial mode, then sending a control command through an NIPCIE industrial personal computer, controlling a clock module in the excitation FPGA to generate a 50M clock as excitation input of the FPGA to be tested according to test requirements, sending the test case of the FPGA to be tested to an oscilloscope module through an SMA connecting line, and reading time parameters on the oscilloscope module;

s5: judging whether the test process is normal or abnormal according to the test items and the judgment standards corresponding to the test items, continuing the test when the test process is normal, and determining to quit or ignore according to the judgment standards when the test process is abnormal;

s6: and (5) storing the test record, jumping to the step 2, and continuing the next project until the test is completely finished.

The invention has the beneficial effects that: based on a PCIE industrial personal computer platform, a 3U PCIE power supply module is integrated in the industrial personal computer and used for power supply parameter testing as a controllable power supply when a CLB of an FPGA to be tested is tested; the 3U PCIE oscilloscope module tests CLB alternating current-direct current simulation parameters; integrating an error code test module in an excitation FPGA on a CLB test onboard hardware platform to meet the CLB function test requirement; the variable clock is generated by exciting the clock module in the FPGA, the requirement on the reference clock during the CLB test is met, so that the full-function and full-performance test of the CLB on the FPGA is completed, and the low cost and miniaturization of the test are realized.

Drawings

Fig. 1 is a hardware configuration diagram of the present invention.

FIG. 2 is a test flow diagram of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in FIG. 1, the invention comprises an NI PCIE industrial personal computer, a power module for CLB power bias test, dynamic and static power consumption test, an oscilloscope module for CLB alternating current time parameter test, a CLB test board-mounted hardware platform, a board-mounted power supply, an excitation FPGA, an active crystal oscillator, a DDR3 cache and an FPGA to be tested, wherein the output end of the NI PCIE industrial personal computer is connected with the input end of the CLB test board-mounted hardware platform, the board-mounted power supply, the excitation FPGA, the active crystal oscillator, the DDR3 cache and the FPGA to be tested are arranged on the CLB test board-mounted hardware platform and connected with the CLB test board-mounted hardware platform, the board-mounted power supply provides power for circuits on the whole CLB test board-mounted hardware platform except the FPGA, the input end of the power module is connected with the output end of the NI PCIE industrial personal computer, the output end of the power module is connected with the input end of the FPGA to be tested, and the output end of the oscilloscope module is connected with the input end of the NI PCIE industrial personal computer.

In order to be not limited to the internal space of the industrial personal computer and facilitate testing, the output end of the NI PCIE industrial personal computer is connected with the input end of the CLB test board-mounted hardware platform through a PCIE extension line, and the PCIE extension line is a semi-flexible high-speed cable with PCIE golden finger interfaces of which the two ends are all 1X.

In order to test a plurality of tested FPGAs simultaneously, the output end of the NI PCIE industrial personal computer is connected with the input ends of a plurality of CLB test board-mounted hardware platforms, and at most 4 CLB test board-mounted hardware platforms are supported.

In order to test a plurality of to-be-tested FPGAs simultaneously, the CLB test board-mounted hardware platform is connected with the plurality of to-be-tested FPGAs simultaneously, and at most 4 FPGA chips are supported.

The power module is a 3U PCIE 4X power module, provides a required power supply for the FPGA to be tested on the CLB test board-mounted hardware platform, comprises 1.2V, 1.0V, 3.3V and 2.5V, controls the power supply power-up sequence of the FPGA to be tested through software configuration, adjusts the power supply deviation, performs bias test on different power supplies, and can test the normal power supply working range of the CLB module. The power supply module is connected with a power supply interface of the FPGA module to be tested through a security connecting line.

The oscilloscope module is a 3U PCIE 4X oscilloscope module, tests of alternating current parameters are achieved, and tests of characteristic parameters and the like of the CLB in time domains such as transmission delay, signal rising and falling time and the like under various logic combination functions are achieved through programming.

In order to reduce loss and facilitate impedance matching, the oscilloscope module is connected with a CLB test board-mounted hardware platform through an SMA low-loss coaxial cable.

The CLB test on-board hardware platform is manufactured by adopting 16 layers of FR4 base materials to realize the on-board power supply, the excitation FPGA, the active crystal oscillator, the DDR3 cache and the wiring and the electrical connection or the electrical insulation among the to-be-tested FPGAs on a test PCB, the required electrical characteristics are provided, the on-board power supply provides various power supplies for circuits (except the to-be-tested FPGAs) on the whole CLB test on-board hardware platform, the on-board power supply provides total power supply input by a 12V power supply on a PCIE 1X bus, the power supply generates 1.0V, 1.5V and 2.5V power supplies after voltage transformation, the 12V input is provided with 1.0V power supply by TPS56121_ DQP _22 on the CLB test on-board hardware platform, the TPS54231DR provides 1.5V power supply, the TPS54620RGY provides 2.5V power supply, and the PCIE.

In practical application, the CLB test board-mounted hardware platform comprises four sets of FPGA clamps to be tested.

The FPGA power supply to be tested is provided by the external power interface circuit, is directly supplied by the 3U PCIE power module, comprises 1.2V, 1.0V, 3.3V and 2.5V, and is adjusted by level software.

The active crystal oscillator adopts a 25M active crystal oscillator and provides the active crystal oscillator for the excitation FPGA to be used as a system clock.

The excitation FPGA comprises a PCIE IP core module for generating and processing a transmission layer data packet, flow control management, initialization, power management, data protection, error check and retry, serialization and deserialization, a PCIE APP module for transmitting the data of the object layer and configuring spatial information, an address bus for decoding the PCIE APP module, an address coding module for generating different address chip selection signals, a clock module for generating a frequency-adjustable excitation clock by using clock hardmac resources inside the excitation FPGA, a CLB test FPGA state machine module for analyzing a CPU control command, a DDR3 cache, a DDR3 control module for realizing the cache of a to-be-tested FPGA test case, and a DDR test module for generating and receiving error codes, wherein the error code test module comprises an error code generating module, an error code receiving module and a main string configuration controller module for saving IO pins of the excitation FPGA, And the test vector generation module is used for generating input test vectors required by the test cases.

The PCIE IP core module is based on the design idea of a hard core, completely realizes the protocol of a physical layer and a data link layer in the PCIe based on PCIE hard core resources in XC7K325TFFG900 and a high-speed SERDES interface connected with the hard core in the excitation FPGA, and comprises the following functions: generating and processing Transport Layer Packets (TLPs), flow control management, initialization and power management, data protection, error checking and retry, serialization, deserialization, and the like. According to the PCIE protocol, a PCIE IP core includes three layers:

transport layer (processing layer, transaction layer): the transport layer is the uppermost layer of the PCIE IP, and its primary functions are to receive, buffer, and transmit transport layer packets, and take charge of the synthesis and decomposition of processing layer packets, perform flow control management, packet queue management, and provide quality of service functions for virtual channels.

Data link layer: the data link layer is like a medium connecting the transport layer and the physical layer, and its primary function is to provide reliability support for the transmission of TLPs between the two layers, and it can perform error check and recovery, and generate and parse a Data Link Layer Packet (DLLP), which is used to transmit information between the data link layers of two interconnected PCIE, thereby implementing the functions of power management, flow control, and TLP acknowledgment.

Physical layer: the physical layer is divided into a logical physical layer and an electrical physical layer, and the logical physical layer completes synthesis and decomposition, parallel-to-serial conversion and serial-to-parallel conversion of the PLPs. The electric physical layer is responsible for data differential drive transmission and reception of all channels.

The PCIE APP module is used for a user to design object layer data transmission content and configuration space information by himself, DPRAMs (Dual Port RAMs) are adopted during receiving and sending, and the two DPRAMs are respectively set as a receiving DPRAM and a sending DPRAM. When receiving, the PCIE IP core is written into the receiving DPRAM from one side in a 64-bit mode, and the internal logic of the FPGA is stimulated to read out from the other side in a 32-bit mode. During sending, the internal logic of the FPGA is excited to be written into a sending DPRAM in a 32-bit mode, and the PCIE IP core is read out from the other side in a 64-bit mode.

The address decoding module decodes according to an address bus of the PCIE APP module to generate different address chip selection signals, in the invention, the local physical space of a PCIE test board card on a CLB test board-mounted hardware platform is 1 Mbyte, and the address decoding is carried out in a four-byte mode, namely, A2 bit of the address bus is the lowest decoding bit, and a control register data unit is 32 bits.

The clock module generates a frequency-adjustable excitation clock by utilizing clock hardcore resources inside the excitation FPGA with the model of XC7K325TFFG900, and is used for a synchronous clock of a test case of the FPGA chipset to be tested.

The CLB test FPGA state machine module is used for analyzing a CPU control command, and the FPGA enters a corresponding working state according to the current FPGA state, and comprises the following steps: resetting, starting error code test, changing clock output, reading download routine, configuring download routine, reading back test result, idling and other states, and exciting the FPGA to be in an idle working state by default after power-on configuration.

The DDR3 control module is used for controlling external DDR3 cache, so that the test cases of the FPGA group to be tested are cached, the test cases are usually dozens of mega in size, next test cases are cached into the DDR3 through the PCIE interface during testing, the FPGA2 group can be configured through the parallel-serial test controller after the last test is completed, the downloading configuration time is saved, and the testing efficiency is improved.

The error code testing module comprises an error code generating module and an error code receiving module, wherein the error code generating module generates PRBS sequences with different rates, a user sets a mode and the like, an output signal of the generating module is used as excitation input of an FPGA test case to be tested, the sequence is output to the input end of the error code receiving module after the FPGA chipset test case to be tested is processed, the error code receiving module has no error code within a user-defined time period, the CLB test under the test case is considered to be passed, and when the test case is configured to be a shift register SRLC16, a D trigger and an SRL shift register cascade mode, the code type generator generates a serial test PRBS vector sequence.

The main string configuration controller module is used for saving IO pins of an excitation FPGA, a serial configuration mode is adopted, a main string configuration sequential circuit of an FPGA group to be tested is generated in the excitation FPGA1, serial configuration of 4 FPGAs to be tested is achieved by using fewer IO pins, test cases in a configuration cache area are serially downloaded into the FPGA group to be tested, and whether the configuration state is successful or not is judged.

The test vector generation module generates input test vectors required by the CLB test case, the test vectors are preset in the internal RAM space, the internal logic resources of the FPGA are saved and excited by adopting the mode, and the CLB modules provided for the FPGA to be tested are sequentially read out and used as the test input vectors.

A use method of FPGA programmable logic unit test equipment is characterized by comprising the following steps:

s1: initializing an NI PCIE industrial personal computer, initializing a power supply module, closing a power supply of an FPGA to be tested, initializing an oscilloscope module, setting the oscilloscope module to be in a direct-current coupling mode, wherein the input impedance is 1M, and an automatic test mode is adopted;

s2: setting items to be tested, and selecting a corresponding test case to download to a DDR3 chip exciting the FPGA;

s3: setting a power supply module to output 1.2V, 1.0V, 1.8V, 3.3V and 2.5V power supplies required by the FPGA to be tested, and setting a trigger level and sampling frequency of an oscilloscope module;

s4: testing the selected items of the FPGA to be tested;

s4.1: the method comprises the steps of performing function test of a selected item on an FPGA to be tested, exciting the FPGA to configure a test case in a DDR3 cache to an FPGA chip to be tested in a serial mode, then sending a control command through an NI PCIE industrial personal computer, controlling a clock module in the excited FPGA to generate a specific frequency clock according to test requirements, outputting a serial sequence after the sequence is processed in the test case of the FPGA to be tested by taking a PRBS sequence generated by an error code generation module of an error code test module as excitation input of the FPGA to be tested under the clock frequency, outputting the serial sequence to an error code receiving module of the error code test module, and determining whether the function test under the frequency is passed or not by whether the error code exists in the error code test module within a user-defined time period;

s4.2: performing performance test of the selected items on the FPGA to be tested;

s4.2.1: the method comprises the steps that performance testing of the maximum working frequency of a selected project is conducted on an FPGA to be tested, an excitation FPGA configures a test case in a DDR3 cache to the FPGA to be tested in a serial mode, then a control command is sent through an NI PCIE industrial personal computer, a clock module in the excitation FPGA is controlled to generate different clocks according to testing requirements, the clocks are halved according to maximum frequency design indexes, under the clock frequency, a PRBS sequence is generated by an error code generation module of an error code testing module and serves as excitation input of the FPGA to be tested, the sequence is output to an error code receiving module of the error code testing module after the FPGA test case to be tested is processed, and whether the function testing under the frequency is passed or not is determined through whether the error code testing module has the error code in a user;

s4.2.2, performing performance test on the output delay time, duty ratio, output rise time and output fall time of the selected items on the tested FPGA, configuring a test case in a DDR3 cache to the FPGA to be tested by the excitation FPGA in a serial mode, then sending a control command through an NIPCIE industrial personal computer, controlling a clock module in the excitation FPGA to generate a 50M clock as excitation input of the FPGA to be tested according to test requirements, sending the test case of the FPGA to be tested to an oscilloscope module through an SMA connecting line, and reading time parameters on the oscilloscope module;

s5: judging whether the test process is normal or abnormal according to the test items and the judgment standards corresponding to the test items, continuing the test when the test process is normal, and determining to quit or ignore according to the judgment standards when the test process is abnormal;

s6: and (5) storing the test record, jumping to the step 2, and continuing the next project until the test is completely finished.

The invention is based on a PCIE industrial personal computer platform, and a 3U PCIE power supply module is integrated in the industrial personal computer and used for power supply parameter test as a controllable power supply when a CLB of an FPGA to be tested is tested; the 3U PCIE oscilloscope module tests CLB alternating current-direct current simulation parameters; integrating an error code test module in an excitation FPGA on a CLB test onboard hardware platform to meet the CLB function test requirement; the variable clock is generated by exciting the clock module in the FPGA, the requirement on the reference clock during the CLB test is met, so that the full-function and full-performance test of the CLB on the FPGA is completed, and the low cost and miniaturization of the test are realized.

Claims (9)

1. An FPGA programmable logic unit test device is characterized in that: the test system comprises an NI PCIE industrial personal computer, a power module for CLB power bias test, dynamic and static power consumption test, an oscilloscope module for CLB alternating current time parameter test and a CLB test board-mounted hardware platform, wherein the output end of the NI PCIE industrial personal computer is connected with the input end of the CLB test board-mounted hardware platform, the CLB test board-mounted hardware platform comprises a test PCB, a board-mounted power supply, an excitation FPGA, an active crystal oscillator, a DDR3 cache and an FPGA clamp to be tested, the board-mounted power supply, the excitation FPGA, the active crystal oscillator, the DDR3 cache and the FPGA clamp to be tested are arranged on the test PCB and connected with the test PCB, the board-mounted power supply provides power for circuits on the whole test PCB except the FPGA to be tested, the input end of the power module is connected with the output end of the NI PCIE industrial personal computer, the output end of the power module is connected with the input end of the FPGA clamp to, and the output end of the oscilloscope module is connected with the input end of the NI PCIE industrial personal computer.

2. The FPGA PLC unit test equipment of claim 1, wherein: and the output end of the NIPCIE industrial personal computer is connected with the input end of the CLB test board-mounted hardware platform through a PCIE extension line.

3. The FPGA PLC unit test equipment of claim 1, wherein: the CLB test board carries the hardware platform and is a plurality of, 4 test platforms at most, the output of NI PCIE industrial computer is connected respectively with the input of polylith CLB test board carries the hardware platform.

4. The FPGA PLC unit test equipment of claim 1 or 3, wherein: the FPGA clamp that awaits measuring is a plurality of, 4 test fixture at most, test PCB is connected with the FPGA clamp that awaits measuring of polylith simultaneously.

5. The FPGA PLC unit test equipment of claim 1, wherein: the power module is a 3U PCIE 4X power module.

6. The FPGA PLC unit test equipment of claim 1, wherein: the oscilloscope module is a 3U PCIE 4X oscilloscope module.

7. The FPGA PLC unit test equipment of claim 1, wherein: the oscilloscope module is connected with the test PCB through the SMA low-loss coaxial cable.

8. The FPGA PLC unit test equipment of claim 1, wherein: the excitation FPGA comprises a PCIE IP core module for generating and processing a transmission layer data packet, flow control management, initialization, power management, data protection, error check and retry, serialization and deserialization, a PCIE APP module for transmitting the data of the object layer and configuring spatial information, an address bus for decoding the PCIE APP module, an address coding module for generating different address chip selection signals, a clock module for generating a frequency-adjustable excitation clock by using clock hardmac resources inside the excitation FPGA, a CLB test FPGA state machine module for analyzing a CPU control command, a DDR3 cache, a DDR3 control module for realizing the cache of a to-be-tested FPGA test case, and a DDR test module for generating and receiving error codes, wherein the error code test module comprises an error code generating module, an error code receiving module and a main string configuration controller module for saving IO pins of the excitation FPGA, And the test vector generation module is used for generating input test vectors required by the test cases.

9. A method of using the FPGA programmable logic cell test equipment of claim 1, comprising the steps of:

s1: initializing an NI PCIE industrial personal computer, initializing a power supply module, closing a power supply of an FPGA to be tested, initializing an oscilloscope module, setting the oscilloscope module to be in a direct-current coupling mode, wherein the input impedance is 1M, and an automatic test mode is adopted;

s2: setting items to be tested, and selecting a corresponding test case to download to a DDR3 chip exciting the FPGA;

s3: setting a power supply module to output 1.2V, 1.0V, 1.8V, 3.3V and 2.5V power supplies required by the FPGA to be tested, and setting a trigger level and sampling frequency of an oscilloscope module;

s4: testing the selected items of the FPGA to be tested;

s4.1: the method comprises the steps of performing function test of a selected item on an FPGA to be tested, exciting the FPGA to configure a test case in a DDR3 cache to an FPGA chip to be tested in a serial mode, then sending a control command through an NI PCIE industrial personal computer, controlling a clock module in the excited FPGA to generate a specific frequency clock according to test requirements, outputting a serial sequence after the sequence is processed in the test case of the FPGA to be tested by taking a PRBS sequence generated by an error code generation module of an error code test module as excitation input of the FPGA to be tested under the clock frequency, outputting the serial sequence to an error code receiving module of the error code test module, and determining whether the function test under the frequency is passed or not by whether the error code exists in the error code test module within a user-defined time period;

s4.2: performing performance test of the selected items on the FPGA to be tested;

s4.2.1: the method comprises the steps that performance testing of the maximum working frequency of a selected project is conducted on an FPGA to be tested, an excitation FPGA configures a test case in a DDR3 cache to the FPGA to be tested in a serial mode, then a control command is sent through an NI PCIE industrial personal computer, a clock module in the excitation FPGA is controlled to generate different clocks according to testing requirements, the clocks are halved according to maximum frequency design indexes, under the clock frequency, a PRBS sequence is generated by an error code generation module of an error code testing module and serves as excitation input of the FPGA to be tested, the sequence is output to an error code receiving module of the error code testing module after the FPGA test case to be tested is processed, and whether the function testing under the frequency is passed or not is determined through whether the error code testing module has the error code in a user;

s4.2.2, performing performance test on the output delay time, duty ratio, output rise time and output fall time of the selected items on the tested FPGA, configuring a test case in a DDR3 cache to the FPGA to be tested by the excitation FPGA in a serial mode, then sending a control command through an NIPCIE industrial personal computer, controlling a clock module in the excitation FPGA to generate a 50M clock as excitation input of the FPGA to be tested according to test requirements, sending the test case of the FPGA to be tested to an oscilloscope module through an SMA connecting line, and reading time parameters on the oscilloscope module;

s5: judging whether the test process is normal or abnormal according to the test items and the judgment standards corresponding to the test items, continuing the test when the test process is normal, and determining to quit or ignore according to the judgment standards when the test process is abnormal;

s6: and (5) storing the test record, jumping to the step 2, and continuing the next project until the test is completely finished.

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