CN111366841B - A kind of FPGA programmable logic unit testing equipment and using method - Google Patents

Abstract

The invention aims to provide FPGA programmable logic unit test equipment and a using method thereof, which are used for carrying out full coverage test on functions and performance of a CLB in an FPGA chip and realizing low cost and miniaturization of a test system, and a 3U PCIE power module is integrated in an industrial personal computer as a controllable power supply for power supply parameter test when the CLB of an FPGA to be tested is tested based on a PCIE industrial personal computer platform; the 3U PCIE oscilloscope module tests CLB alternating current-direct current simulation parameters; integrating an error code test module in an excitation FPGA on a CLB test onboard hardware platform to meet the CLB function test requirement; a variable clock is generated by exciting a clock module in the FPGA, so that the requirement on a reference clock in the CLB test is met, the full-function and full-performance test of the CLB on the FPGA is finished, and the low cost and miniaturization of the test are realized.

Description

A kind of FPGA programmable logic unit testing equipment and using method

technical field

The invention belongs to the field of FPGA testing, and in particular relates to a FPGA programmable logic unit testing device and a using method.

Background technique

More than 90% of the logic functions in FPGA are completed by CLB. Programmable logic unit test includes functional test and performance test. The functional test of CLB includes: LUT (16-bit register, SRLC16) functional test in SLICEM, distributed RAM and memory in SLICEM (single-port 32X1-bit RAM, dual-port 16X2 Bit RAM) function test, read-only memory (ROM128X1) function test, flip-flop (D flip-flop/level latch), carry chain test, SRL cascade test, etc. The performance test includes DC parameter, AC parameter test, and limit parameter test for all functions to work normally.

Usually, after the FPGA chip is taped out, it is necessary to perform a full coverage test of the function and performance of the FPGA chip. The chip test is a very important part in the design and production of the FPGA chip. There are various schemes for the chip test, such as building a special test instrument for circuit board connection. Carry out functional and performance testing of specific aspects, use professional automatic tester ATE for testing, or use FPGA to connect with chips and so on.

The test items included in the CLB test of the FPGA are: shift register, D flip-flop, maximum operating frequency, and module power consumption. Each item needs to test both functions and performance. Except for the functional test, in the performance test The AC parameters, such as rise time, fall time, transmission delay time, are more concerned by designers, because the design principle of ATE test AC and DC parameters is to use the comparator to judge the test parameters, which cannot meet the CLB AC and DC parameters. The test requirements, ATE is a comparator, given a spatial range, the output is the criterion result, not a definite value directly measured, so the direct AC and DC parameters of the CLB cannot be directly tested. The use of separate test instruments at this stage can completely cover the full-function and full-performance testing of the CLB. But at the same time, in order to completely test the function and performance of the CLB, it is necessary to repeatedly download the FPGA use case to test different parameters, and it is necessary to select different test instruments for testing. This test method leads to the problems of long test time, complicated wiring and high test cost during CLB test.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an FPGA programmable logic unit testing device and a method for using it, which are used to perform a full coverage test of the function and performance of the CLB in the FPGA chip and realize the low cost and miniaturization of the testing system.

The technical solution of the present invention to solve the technical problem is as follows: an FPGA programmable logic unit testing device, including an NI PCIE industrial computer, a power supply module for CLB power supply bias testing, dynamic and static power consumption testing, and a power supply module for CLB AC time Oscilloscope module for parametric test, CLB test onboard hardware platform, onboard power supply, excitation FPGA, active crystal oscillator, DDR3 cache, FPGA to be tested, the output end of the NI PCIE industrial computer and the input end of the CLB test onboard hardware platform Connection, the on-board power supply, excitation FPGA, active crystal oscillator, DDR3 cache, and the FPGA to be tested are arranged on the CLB test on-board hardware platform to be connected to the CLB test on-board hardware platform, and the on-board power supply is to remove the FPGA to be tested. The circuit on the entire CLB test onboard hardware platform provides power, the input end of the power module is connected to the output end of the NI PCIE industrial computer, the output end of the power module is connected to the input end of the FPGA to be tested, and the oscilloscope module The input end of the oscilloscope module is connected with the output end of the FPGA to be tested, and the output end of the oscilloscope module is connected with the input end of the NI PCIE industrial computer.

In order not to be limited to the internal space of the industrial computer and to facilitate testing, the output end of the NI PCIE industrial computer is connected to the input end of the CLB test onboard hardware platform through a PCIE extension line.

In order to test multiple FPGAs under test at the same time, the output end of the NI PCIE industrial computer is connected to the input end of multiple CLB test onboard hardware platforms, and supports up to 4 CLB test platforms at the same time.

In order to test multiple FPGAs under test at the same time, the CLB test onboard hardware platform is connected with multiple FPGAs under test at the same time, and at most four test fixtures are installed on one test platform.

The power supply module is a 3U PCIE 4X power supply module, which provides the required power supply for the FPGA to be tested on the CLB test onboard hardware platform, including 1.2V, 1.0V, 3.3V, 2.5V, and controls the FPGA to be tested through software configuration. The power supply sequence, adjustment of the power supply deviation, and pull-off test for different power supplies can test the normal power supply working range of the CLB module. It can be used to test the leakage current, static and dynamic power consumption of the module circuit, and the power module is connected to the power interface of the FPGA module to be tested through a security cable.

The oscilloscope module is a 3U PCIE 4X oscilloscope module, which realizes the test of AC parameters, and realizes the test of time domain characteristic parameters such as CLB transmission delay, signal rise and fall time under various logic combination functions through programming.

In order to reduce loss and facilitate impedance matching, the oscilloscope module is connected to the CLB test onboard hardware platform through an SMA low-loss coaxial cable.

The excitation FPGA includes a PCIE IP core module for generating and processing transport layer data packets, flow control management, initialization, power management, data protection, error checking and retry, serialization, and deserialization functions. The PCIE APP module for the data transmission content of the transaction layer and the configuration space information, the address encoding module for decoding the address bus of the PCIE APP module and generating different address chip select signals, and the use of the clock hard core resources to stimulate the FPGA to generate frequency The clock module for the adjustable excitation clock, the CLB test FPGA state machine module for parsing the CPU control commands, the DDR3 control module for controlling the DDR3 cache, and the DDR3 control module for implementing the cache of the FPGA test case to be tested, for bit errors and receiving errors A code error test module, the code error test module includes a code error generation module and a code error receiving module, a main string configuration controller module for saving the IO pins of the excitation FPGA, and an input test vector for generating test cases. The test vector generation module.

A method of using FPGA programmable logic unit testing equipment, comprising the following steps:

S1: Initialize the NI PCIE industrial computer, initialize the power supply module, turn off the power supply of the FPGA to be tested, initialize the oscilloscope module, set the oscilloscope module to DC coupling, input impedance to 1M, and automatic test mode. Complete the configuration process, and interact with the industrial computer through the PCIE IP core module inside the excitation FPGA to complete the initialization process of the entire system;

S2: Set the items to be tested, select the corresponding test case and download it to the DDR3 chip that motivates the FPGA;

S3: Set the 1.2V, 1.0V, 1.8V, 3.3V, 2.5V power required by the power supply module to output the FPGA to be tested, and set the trigger level and sampling frequency of the oscilloscope module;

S4: Test the selected item on the FPGA under test;

S4.1: Perform the functional test of the selected item on the FPGA under test, stimulate the FPGA to configure the test cases in the DDR3 cache to the FPGA chip under test in serial mode, and then send control commands through the NI PCIE industrial computer to control and stimulate the FPGA chip. The clock module generates a specific frequency clock according to the test requirements. At this clock frequency, the PRBS sequence generated by the error generation module of the error test module is used as the excitation input of the FPGA to be tested. After the sequence is processed in the test case of the FPGA to be tested, The serial sequence is output, and the serial sequence is output to the error receiving module of the error test module, and whether the function test at the frequency is passed is determined by whether the error test module has errors within the user-defined time period;

S4.2: Perform the performance test of the selected item on the FPGA under test;

S4.2.1: Perform the performance test on the maximum operating frequency of the selected item on the FPGA under test, motivate the FPGA to serially configure the test cases in the DDR3 cache to the FPGA to be tested, and then send control commands through the NI PCIE industrial computer to control The clock module in the FPGA is stimulated to generate different clocks according to the test requirements, and the clock is generated in half according to the maximum frequency design index. At this clock frequency, the error generation module of the error test module generates a PRBS sequence as the excitation input of the FPGA to be tested. After the FPGA test case to be tested is processed, it is output to the bit error receiving module of the bit error test module, and whether the function test at the frequency is passed is determined by whether the bit error test module has bit errors within the user-defined time period;

S4.2.2: Perform the performance test on the output delay time, duty cycle, output rise and fall time of the selected item on the FPGA under test, motivate the FPGA to serially configure the test cases in the DDR3 cache to the FPGA under test, and then Send control commands through the NI PCIE industrial computer to control and stimulate the clock module in the FPGA to generate a 50M clock as the excitation input of the FPGA to be tested according to the test requirements, send the test case of the FPGA to be tested to the oscilloscope module through the SMA cable, and read the oscilloscope module. The time parameter on;

S5: According to the test item and the judgment standard corresponding to the test item, judge whether the test process is normal or abnormal, when it is normal, continue the test, and when it is abnormal, decide to quit or ignore it according to the judgment standard;

S6: Save the test record, jump to step 2, and continue to the next item until the test is all completed.

The beneficial effects of the invention are as follows: based on the PCIE industrial computer platform, a 3U PCIE power supply module is integrated in the industrial computer as a controllable power supply during the CLB test of the FPGA to be tested for power supply parameter testing; 3U PCIE oscilloscope module tests CLB AC and DC simulation Parameters; the error test module is integrated in the excitation FPGA on the CLB test onboard hardware platform to meet the CLB function test requirements; the clock module inside the excitation FPGA is used to generate a variable clock to meet the reference clock requirements during the CLB test to complete the test. The full-function and full-performance test of CLB on FPGA realizes the low-cost and miniaturization of the test.

Description of drawings

FIG. 1 is a hardware structure diagram of the present invention.

Fig. 2 is the test flow chart of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

As shown in FIG. 1, the present invention includes NI PCIE industrial computer, power supply module for CLB power supply bias test, dynamic and static power consumption test, oscilloscope module for CLB AC time parameter test, CLB test onboard hardware platform, On-board power supply, excitation FPGA, active crystal oscillator, DDR3 cache, FPGA to be tested, the output end of the NI PCIE industrial computer is connected to the input end of the CLB test onboard hardware platform, the on-board power supply, excitation FPGA, active The crystal oscillator, the DDR3 cache, and the FPGA to be tested are arranged on the CLB test onboard hardware platform to be connected to the CLB test onboard hardware platform, and the on-board power supply provides power for circuits on the entire CLB test onboard hardware platform except the FPGA to be tested, The input end of the power supply module is connected with the output end of the NI PCIE industrial computer, the output end of the power supply module is connected with the input end of the FPGA to be tested, and the input end of the oscilloscope module is connected to the output end of the FPGA to be tested, so the The output end of the oscilloscope module is connected to the input end of the NI PCIE industrial computer.

In order not to be limited to the internal space of the industrial computer and to facilitate testing, the output end of the NI PCIE industrial computer is connected to the input end of the CLB test onboard hardware platform through a PCIE extension cable. The PCIE extension cable is a PCIE gold finger with 1X at both ends. A semi-flexible high-speed cable with an interface.

In order to test multiple FPGAs under test at the same time, the output end of the NI PCIE industrial computer is connected to the input end of multiple CLB test onboard hardware platforms, and supports up to 4 CLB test onboard hardware platforms.

In order to test multiple FPGAs to be tested at the same time, the CLB test onboard hardware platform is connected to multiple FPGAs to be tested at the same time, and supports up to 4 FPGA chips.

The power supply module is a 3U PCIE 4X power supply module, which provides the required power supply for the FPGA to be tested on the CLB test onboard hardware platform, including 1.2V, 1.0V, 3.3V, 2.5V, and controls the FPGA to be tested through software configuration. The power supply sequence, adjustment of the power supply deviation, and pull-off test for different power supplies can test the normal power supply working range of the CLB module. It can be used to test the leakage current, static and dynamic power consumption of the module circuit, and the power module is connected to the power interface of the FPGA module to be tested through a security cable.

The oscilloscope module is a 3U PCIE 4X oscilloscope module, which realizes the test of AC parameters, and realizes the test of time domain characteristic parameters such as CLB transmission delay, signal rise and fall time under various logic combination functions through programming.

In order to reduce loss and facilitate impedance matching, the oscilloscope module is connected to the CLB test onboard hardware platform through an SMA low-loss coaxial cable.

In the present invention, the CLB test on-board hardware platform adopts 16-layer FR4 base material to manufacture the on-board power supply, excitation FPGA, active crystal oscillator, DDR3 cache, FPGA to be tested, wiring and electrical connection or electrical insulation on the test PCB, and provides The required electrical characteristics, the on-board power supply provides the various power supplies required for the circuits on the entire CLB test on-board hardware platform (excluding the FPGA to be tested), and the on-board power supply is provided by the 12V power supply on the PCIE 1X bus. The total power input , 1.0V, 1.5V, 2.5V power is generated after transformation, 12V input is provided by TPS56121_DQP_22 on the CLB test onboard hardware platform to provide 1.0V power, TPS54231DR provides 1.5V power, TPS54620RGY provides 2.5V power, and PCIE 1X bus provides 3.3 V power supply.

In practical applications, this CLB test onboard hardware platform includes four sets of FPGA fixtures to be tested.

It also includes an external power interface circuit. The external power interface circuit provides the FPGA power to be tested, which is directly supplied by the 3U PCIE power module, including 1.2V, 1.0V, 3.3V, and 2.5V, and is adjusted by level software.

The active crystal oscillator uses a 25M active crystal oscillator, which is provided to stimulate the FPGA as a system clock.

The excitation FPGA includes a PCIE IP core module for generating and processing transport layer data packets, flow control management, initialization, power management, data protection, error checking and retry, serialization, and deserialization functions. The PCIE APP module for the data transmission content of the transaction layer and the configuration space information, the address encoding module for decoding the address bus of the PCIE APP module and generating different address chip select signals, and the use of the clock hard core resources to stimulate the FPGA to generate frequency The clock module for the adjustable excitation clock, the CLB test FPGA state machine module for parsing the CPU control commands, the DDR3 control module for controlling the DDR3 cache, and the DDR3 control module for implementing the cache of the FPGA test case to be tested, for bit errors and receiving errors A code error test module, the code error test module includes a code error generation module and a code error receiving module, a main string configuration controller module for saving the IO pins of the excitation FPGA, and an input test vector for generating test cases. The test vector generation module.

PCIE IP core module, based on the design idea of hard core, inside the excitation FPGA, based on the PCIE hard core resources inside the XC7K325TFFG900, and the high-speed SERDES port connected to the hard core position, it completely realizes the physical layer and data link layer in PCIe. Protocol, PCIE IP core module contains the following functions: generation and processing of transport layer packets (TLPs), flow control management, initialization and power management, data protection, error checking and retry, serialization, deserialization and other functions. According to the PCIE protocol, the PCIE IP core includes three layers:

Transport layer (processing layer, transaction layer): The transport layer is the top layer of PCIE IP. Its primary function is to receive, buffer and transmit transport layer packets, and is responsible for the synthesis and decomposition of processing layer packets, and for flow control management. Packet queue management and use of virtual channels to provide quality of service functions.

Data link layer: The data link layer is like a medium connecting the transport layer and the physical layer. Its primary function is to provide reliability support for the transmission of TLPs between the two layers. It can perform error checking and recovery, and generate and parse data. Link Layer Packet (DLLP), DLLP is used to transmit information between the data link layers of two interconnected PCIEs, thereby realizing functions such as power management, flow control, and TLP confirmation.

Physical layer: The physical layer is divided into a logical physical layer and an electrical physical layer. The logical physical layer completes the synthesis and decomposition of PLP, parallel-to-serial conversion and serial-to-parallel conversion. The electrical physical layer is responsible for the data differential drive transmission and reception of all channels.

The PCIE APP module is a user-designed transaction layer data transmission content and configuration space information. Both receiving and sending use DPRAM (Dual Port RAM), and the two DPRAMs are respectively set to receive DPRAM and send DPRAM. When receiving, the PCIE IP core writes to the receiving DPRAM in 64bits mode from one side, and stimulates the internal logic of the FPGA to read out in 32bits mode from the other side. When sending, the internal logic of the FPGA is stimulated to write to the sending DPRAM in 32 bits mode, and the PCIE IP core reads out in 64 bits mode from the other side.

The address decoding module decodes according to the address bus of the PCIE APP module to generate different address chip select signals. In the present invention, the local physical space of the PCIE test board on the CLB test onboard hardware platform is 1M bytes in size, The address decoding is carried out in a four-byte manner, that is, the A2 bit of the address bus is the lowest bit of decoding, and the data unit of the control register is 32 bits.

The clock module uses the clock hard core resources inside the excitation FPGA with the model XC7K325TFFG900 to generate an excitation clock with adjustable frequency, which is used for the synchronization clock of the test case of the FPGA chipset to be tested.

The CLB test FPGA state machine module is used to parse the CPU control commands. According to the current FPGA state, the FPGA enters the corresponding working state, including: reset, start the error test, change the clock output, read the download routine, configure the download routine, read back Test results, idle and other states, the FPGA is in an idle working state by default after power-on configuration.

The DDR3 control module is used to control the external DDR3 cache to realize the cache of the test cases of the FPGA group to be tested. The test cases are usually tens of megabytes in size. During the test, the next test cases are cached into DDR3 through the PCIE interface. After the test is completed, the FPGA2 group can be configured through the parallel-serial test controller, which saves the download configuration time and improves the test efficiency.

Error testing module, including error generating module and error receiving module. The error generating module generates PRBS sequences of different rates, user-set modes, etc. The output signal of the generating module is used as the stimulus input of the FPGA test case to be tested, and the sequence is under test. After the FPGA chipset test case is processed, it is output to the input end of the error receiving module. If the error receiving module has no error within the user-defined time period, the CLB test under this test case is considered to pass. When the test case is configured as a shift register SRLC16 , D flip-flop and SRL shift register cascade mode, the pattern generator generates serial test PRBS vector sequence.

The main serial configuration controller module is to save the IO pins of the excitation FPGA. It adopts the serial configuration method to generate the main serial configuration sequence circuit of the FPGA group to be tested in the excitation FPGA1, and uses fewer IO pins to realize the four FPGAs to be tested. Serial configuration, serially download the test cases in the configuration buffer area to the FPGA group to be tested, and judge whether the configuration status is successful or not.

The test vector generation module generates the input test vector required for the CLB test case, and the test vector is preset to the internal RAM space. In this way, the internal logic resources of the excitation FPGA are saved, and the CLB module provided to the FPGA to be tested is sequentially read out as the test input vector.

A method of using FPGA programmable logic unit testing equipment, comprising the following steps:

S1: Initialize the NI PCIE industrial computer, initialize the power module, turn off the power of the FPGA to be tested, initialize the oscilloscope module, set the oscilloscope module to DC coupling, input impedance to 1M, automatic test mode, and to stimulate the FPGA to pass the configuration after power-on The chip completes the configuration process, and interacts with the industrial computer through the PCIE IP core module inside the excitation FPGA to complete the initialization process of the entire system;

S2: Set the items to be tested, select the corresponding test case and download it to the DDR3 chip that motivates the FPGA;

S3: Set the 1.2V, 1.0V, 1.8V, 3.3V, 2.5V power required by the power supply module to output the FPGA to be tested, and set the trigger level and sampling frequency of the oscilloscope module;

S4: Test the selected item on the FPGA under test;

S4.1: Perform the functional test of the selected item on the FPGA under test, stimulate the FPGA to configure the test cases in the DDR3 cache to the FPGA chip under test in serial mode, and then send control commands through the NI PCIE industrial computer to control and stimulate the FPGA chip. The clock module generates a specific frequency clock according to the test requirements. At this clock frequency, the PRBS sequence generated by the error generation module of the error test module is used as the excitation input of the FPGA to be tested. After the sequence is processed in the test case of the FPGA to be tested, The serial sequence is output, and the serial sequence is output to the error receiving module of the error test module, and whether the function test at the frequency is passed is determined by whether the error test module has errors within the user-defined time period;

S4.2: Perform the performance test of the selected item on the FPGA under test;

S4.2.1: Perform the performance test on the maximum operating frequency of the selected item on the FPGA under test, motivate the FPGA to serially configure the test cases in the DDR3 cache to the FPGA to be tested, and then send control commands through the NI PCIE industrial computer to control The clock module in the FPGA is stimulated to generate different clocks according to the test requirements, and the clock is generated in half according to the maximum frequency design index. At this clock frequency, the error generation module of the error test module generates a PRBS sequence as the excitation input of the FPGA to be tested. After the FPGA test case to be tested is processed, it is output to the bit error receiving module of the bit error test module, and whether the function test at the frequency is passed is determined by whether the bit error test module has bit errors within the user-defined time period;

S4.2.2: Perform the performance test on the output delay time, duty cycle, output rise and fall time of the selected item on the FPGA under test, motivate the FPGA to serially configure the test cases in the DDR3 cache to the FPGA under test, and then Send control commands through the NI PCIE industrial computer to control and stimulate the clock module in the FPGA to generate a 50M clock as the excitation input of the FPGA to be tested according to the test requirements, send the test case of the FPGA to be tested to the oscilloscope module through the SMA cable, and read the oscilloscope module. The time parameter on;

S5: According to the test item and the judgment standard corresponding to the test item, judge whether the test process is normal or abnormal, when it is normal, continue the test, and when it is abnormal, decide to quit or ignore it according to the judgment standard;

S6: Save the test record, jump to step 2, and continue to the next item until the test is all completed.

The invention is based on the PCIE industrial computer platform, and a 3U PCIE power supply module is integrated in the industrial computer as a controllable power supply during the CLB test of the FPGA to be tested for power supply parameter testing; the 3U PCIE oscilloscope module tests the CLB AC and DC analog parameters; The excitation FPGA on the on-board hardware platform integrates the error test module to meet the CLB function test requirements; the clock module inside the excitation FPGA is used to generate a variable clock to meet the reference clock requirements during CLB testing, thereby completing the full CLB test on the FPGA. Functional and full performance testing to achieve low cost and miniaturization of testing.

Claims (8)

1. a FPGA programmable logic unit test equipment, is characterized in that: comprise NI PCIE industrial computer, be used for CLB power supply bias test, the power supply module of dynamic, static power consumption test, be used for the oscilloscope module of CLB AC time parameter test , CLB test onboard hardware platform, the output end of the NI PCIE industrial computer is connected with the input end of the CLB test onboard hardware platform, and the CLB test onboard hardware platform includes a test PCB, an on-board power supply, an excitation FPGA, an active Crystal oscillator, DDR3 cache, FPGA fixture to be tested, the on-board power supply, excitation FPGA, active crystal oscillator, DDR3 cache, and FPGA fixture to be tested are arranged on the test PCB and connected to the test PCB, the on-board power supply is to remove the FPGA to be tested The circuit on the entire test PCB provides power supply, the input end of the power supply module is connected with the output end of the NI PCIE industrial computer, the output end of the power supply module is connected with the input end of the FPGA fixture to be tested, and the input end of the oscilloscope module is connected. The end is connected with the output end of the FPGA to be tested, and the output end of the oscilloscope module is connected with the input end of the NI PCIE industrial computer; The excitation FPGA includes a PCIE IP core module for generating and processing transport layer data packets, flow control management, initialization, power management, data protection, error checking and retry, serialization, and deserialization functions. The PCIE APP module of the transaction layer data transmission content and configuration space information is used to decode the address bus of the PCIE APP module and generate the address coding module of different address chip select signals. It uses the clock hard core resources inside the FPGA to generate frequency. The clock module for the adjustable excitation clock, the CLB test FPGA state machine module for parsing the CPU control commands, the DDR3 control module for controlling the DDR3 cache and implementing the cache of the FPGA test case to be tested, for the occurrence of bit errors and receiving errors A code error test module, the code error test module includes a code error generation module and a code error receiving module, a main string configuration controller module for saving the IO pins of the excitation FPGA, and an input test vector for generating test cases. The test vector generation module. 2 . The FPGA programmable logic unit testing device according to claim 1 , wherein the output end of the NIPCIE industrial computer is connected to the input end of the CLB test onboard hardware platform through a PCIE extension line. 3 . 3. a kind of FPGA programmable logic unit testing equipment according to claim 1, is characterized in that: described CLB test onboard hardware platform is multiple, at most 4 CLB test onboard hardware platforms, described NI PCIE industrial control The output end of the machine is respectively connected with the input end of the multiple CLB test onboard hardware platforms. 4. a kind of FPGA programmable logic unit testing equipment according to claim 1 or 3, is characterized in that: described FPGA fixture to be tested is a plurality of, at most 4 FPGA fixtures to be tested, and described test PCB simultaneously and multiple FPGA fixtures. The block to be tested is connected to the FPGA fixture. 5. A FPGA programmable logic unit testing device according to claim 1, wherein the power supply module is a 3U PCIE 4X power supply module. 6. A FPGA programmable logic unit testing device according to claim 1, wherein the oscilloscope module is a 3U PCIE 4X oscilloscope module. 7 . The FPGA programmable logic unit testing device according to claim 1 , wherein the oscilloscope module is connected to the testing PCB through an SMA low-loss coaxial cable. 8 . 8. a using method of FPGA programmable logic unit testing equipment as claimed in claim 1, is characterized in that, comprises the following steps: S1: Initialize the NI PCIE industrial computer, initialize the power module, turn off the power of the FPGA to be tested, initialize the oscilloscope module, set the oscilloscope module to DC coupling, the input impedance to 1M, and the automatic test mode. After the FPGA is powered on, configure the chip Complete the configuration process, and interact with the industrial computer through the PCIE IP core module inside the excitation FPGA to complete the initialization process of the entire system; S2: Set the items to be tested, select the corresponding test case and download it to the DDR3 chip that motivates the FPGA; S3: Set the 1.2V, 1.0V, 1.8V, 3.3V, 2.5V power required by the power module to output the FPGA to be tested, and set the trigger level and sampling frequency of the oscilloscope module; S4: Test the selected item on the FPGA to be tested; S4.1: Perform the functional test of the selected item on the FPGA to be tested, and motivate the FPGA to configure the test cases in the DDR3 cache to the FPGA chip to be tested in serial mode, and then send control commands through the NI PCIE industrial computer to control and motivate the clock in the FPGA The module generates a specific frequency clock according to the test requirements. Under this frequency clock, the PRBS sequence generated by the error generation module of the error test module is used as the excitation input of the FPGA to be tested. After the sequence is processed in the test case of the FPGA to be tested, the output Serial sequence, the serial sequence is output to the error receiving module of the error test module, and whether the function test at this frequency is passed is determined by whether the error test module has errors in the user-defined time period; S4.2: Perform the performance test of the selected project on the FPGA to be tested; S4.2.1: Perform a performance test on the FPGA to be tested in terms of the maximum operating frequency of the selected item, motivate the FPGA to serially configure the test cases in the DDR3 cache to the FPGA to be tested, and then send control commands through the NI PCIE industrial computer to control the stimulus The clock module in the FPGA generates different clocks according to the test requirements, and the clock is generated in half according to the maximum frequency design index. Under this clock, the error generation module of the error test module generates a PRBS sequence as the excitation input of the FPGA to be tested. After the FPGA test case is processed, it is output to the error receiving module of the error test module, and whether the function test at this frequency is passed is determined by whether the error test module has errors within the user-defined time period; S4.2.2: Perform the performance test on the output delay time, duty cycle, output rise and fall time of the selected FPGA on the FPGA to be tested, motivate the FPGA to configure the test cases in the DDR3 cache in serial mode to the FPGA to be tested, and then pass The NIPCIE industrial computer sends control commands to control and stimulate the clock module in the FPGA to generate a 50M clock as the excitation input of the FPGA to be tested according to the test requirements, send the test case of the FPGA to be tested to the oscilloscope module through the SMA cable, and read the time on the oscilloscope module parameter; S5: According to the test item and the judgment standard corresponding to the test item, judge whether the test process is normal or abnormal, when it is normal, continue the test, and when it is abnormal, decide to quit or ignore it according to the judgment standard; S6: Save the test record, jump to step S2, and continue to the next item until all the tests are completed.

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