CN108646172A - A kind of apparatus for testing chip - Google Patents
A kind of apparatus for testing chip Download PDFInfo
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- CN108646172A CN108646172A CN201810738353.XA CN201810738353A CN108646172A CN 108646172 A CN108646172 A CN 108646172A CN 201810738353 A CN201810738353 A CN 201810738353A CN 108646172 A CN108646172 A CN 108646172A
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- 238000004804 winding Methods 0.000 claims description 3
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention discloses a kind of apparatus for testing chip to include：There is JTAG link blocks jtag test tool and single JTAG connectors, jtag test tool to be mounted on single JTAG connectors；Handover module, single JTAG connectors are connected to two chip under test by handover module, and handover module switchably provides the output of jtag test tool to the input terminal of two chip under test and provides the output of two chip under test to the input terminal of jtag test tool；Control module, is connected to handover module, and control module the switching Enable Pin to handover module provides high/low level to control by way of two chip under test of jtag test tool pair test.The present invention can be directed to different chips or different types of chip and flexibly switch and test, and reduce the volume of JTAG link topology and easy to operation.
Description
Technical field
The present invention relates to integrated circuit testing fields, more specifically, particularly relating to a kind of apparatus for testing chip.
Background technology
JTAG (Joint Test Action Group, joint test working group) be a kind of international standard test protocol (with
IEEE 1149.1 is compatible with), it is mainly used for inside test chip.Most of device (such as DSP, FPGA device) of the prior art
All support JTAG protocol.The jtag interface of standard is 5 line interfaces for having TMS, TCK, TRST, TDI and TDO, corresponds to mould respectively
Formula selection, clock, reset, data input and data output.The chip that 2 same models have been used in a board design, should
There are mainly two types of the JTAG of chip is applied, first, carrying out eye pattern test to chip high speed interface；Second is that being compiled online to chip
Journey and firmware burning.When carrying out eye pattern test to chip high speed interface, jtag test tool is only supported to exist in link single
Chip.
In order to realize the JTAG functions of above-mentioned chip, the JTAG link topology of the prior art is as shown in Figure 1, each core
Piece individually corresponds to a jtag interface.The JTAG link disclosure satisfy that the high-speed interface eye pattern test function of one single chip and online
Programming and firmware burning function, but used two JTAG connectors.JTAG connector volumes are larger, occupy larger plate
Card space keeps board PCB placement-and-routings more nervous；Simultaneously because board is mounted on inside host, dismounting is complicated, in a core
Another chip is tested and board structure can only be removed after built-in testing, jtag test tool from the chip pair
The JTAG connectors answered are installed to after removing on the corresponding JTAG connectors of another chip again, and this considerably increases chip testings
Complexity.
JTAG connector volumes are larger in the JTAG link topology used for the prior art, test board is difficult to dismount
Problem, there has been no effective solution schemes at present.
Invention content
In view of this, the purpose of the embodiment of the present invention is to propose a kind of apparatus for testing chip, different chips can be directed to
Or different types of chip flexibly switch and test, and reduces the volume of JTAG link topology and easy to operation.
Based on above-mentioned purpose, the one side of the embodiment of the present invention provides a kind of apparatus for testing chip, including：
There is JTAG link blocks jtag test tool and single JTAG connectors, jtag test tool to be mounted on single
On JTAG connectors；
Handover module, single JTAG connectors are connected to two chip under test by handover module, and handover module is changeable
Ground provides the output of jtag test tool to the input terminal of two chip under test and provides two to the input terminal of jtag test tool
The output of a chip under test；
Control module, is connected to handover module, and control module provides high/low electricity by the switching Enable Pin to handover module
It puts down to control the mode that two chip under test of jtag test tool pair are tested.
In some embodiments, two chip under test are equipped with input terminal TCK, TMS, TRST, TDI and output end TDO；
JTAG link blocks are correspondingly equipped with output end TCK, TMS, TRST, TDI and input terminal TDO.
In some embodiments, handover module includes that three four-ways switch chip and a single channel switching chip,
Enable Pin TCK, TMS, TRST of two chip under test are parallel to JTAG link blocks by three four-way switching chips, and will
The data terminal TDI of JTAG link blocks is connected to the data terminal TDI of two chip under test；It is tested by two that single channel switches chip
The data terminal TDO of chip is connected to the data terminal TDO of JTAG link blocks.
In some embodiments, three four-way switching chips and a single channel switching chip are all made of QFN encapsulation；
Control module is BMC chip.
In some embodiments, two chip under test are the first chip under test and the second chip under test；Control module has
There are the first output end and second output terminal, the first output end and second output terminal to be connected to the switching Enable Pin of handover module to control
The mode of coremaking built-in testing two chip under test of device to test.
In some embodiments, in the case where the first output end and second output terminal export high level, chip is surveyed
Trial assembly, which is set, neither to be tested the first chip under test and not to test the second chip under test, and the input terminal TDO of JTAG link blocks is received
Signal it is identical as the signal that its output end TDI is sent.
In some embodiments, in the case of the first output end output low level second output terminal output high level,
Apparatus for testing chip tests the first chip under test and bypasses the second chip under test, and the input terminal TDO of JTAG link blocks is received
The signal arrived is the signal that the output end TDO of the first chip under test is sent.
In some embodiments, high level is exported in the first output end, in the case of second output terminal output is low level,
Apparatus for testing chip tests the second chip under test and bypasses the first chip under test, and the input terminal TDO of JTAG link blocks is received
The signal arrived is the signal that the output end TDO of the second chip under test is sent.
In some embodiments, low level, chip survey is exported in the first output end and second output terminal
The operated in series connection situation of the first chip under test and the second chip under test, the input terminal of JTAG link blocks are set while being tested in trial assembly
The signal that TDO is received is defeated by its after the signal that the output end TDO of the first chip under test is sent is handled by the second chip under test
The signal that outlet TDO is sent.
In some embodiments, the first output end and the level of second output terminal can at any time switch with real-time
Change the operating mode of apparatus for testing chip.
The present invention has following advantageous effects：Apparatus for testing chip provided in an embodiment of the present invention, by using list
A JTAG connectors are connected to two chip under test and under the control of control module according to work side simultaneously via handover module
The technical solution of two chip under test selectivity tests of formula pair, can be directed to different chips or different types of chip carries out flexibly
Switching and test, reduce the volume of JTAG link topology and easy to operation.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is the connection relationship diagram of the apparatus for testing chip of the prior art；
Fig. 2 is the structure diagram of apparatus for testing chip provided by the invention；
Fig. 3 is the circuit diagram of apparatus for testing chip provided by the invention；
Fig. 4 is circuit diagram of the apparatus for testing chip provided by the invention when two chip under test are not tested；
Fig. 5 is circuit diagram of the apparatus for testing chip provided by the invention when testing the first chip under test；
Fig. 6 is circuit diagram of the apparatus for testing chip provided by the invention when testing the second chip under test；
Fig. 7 is circuit theory of the apparatus for testing chip provided by the invention when series winding tests the first and second chip under test
Figure.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
The embodiment of the present invention is further described in attached drawing.
It should be noted that all statements for using " first " and " second " are for differentiation two in the embodiment of the present invention
The non-equal entity of a same names or non-equal parameter, it is seen that " first " " second " only for the convenience of statement, does not answer
It is interpreted as the restriction to the embodiment of the present invention, subsequent embodiment no longer illustrates this one by one.
Based on above-mentioned purpose, the first aspect of the embodiment of the present invention, it is proposed that a kind of to be directed to different chips or difference
The chip of type carries out the embodiment of flexibly switching and the device tested.Fig. 2 shows be chip testing provided by the invention dress
The structure diagram for the embodiment set.
The apparatus for testing chip includes：
There is JTAG link blocks 1 jtag test tool and single JTAG connectors, jtag test tool to be mounted on single
On JTAG connectors；
Handover module 2, single JTAG connectors are connected to two chip under test by handover module 2, and handover module 2 can be cut
The output of jtag test tool is provided to the input terminal of two chip under test and is provided to the input terminal of jtag test tool with changing
The output of two chip under test；
Control module 3, is connected to handover module 2, control module 3 by the switching Enable Pin to handover module 2 provide it is high/
Low level controls the mode that two chip under test of jtag test tool pair are tested.
In some embodiments, two chip under test are equipped with input terminal TCK, TMS, TRST, TDI and output end TDO；
JTAG link blocks 1 are correspondingly equipped with output end TCK, TMS, TRST, TDI and input terminal TDO.JTAG link blocks 1 with
The corresponding pin of chip under test is connected, and tests chip under test, example by sending signal to TDI, receiving feedback from TDO
Such as eye pattern or programming burning.
JTAG link blocks 1 can be realized or be held using the following component for being designed to execute function described here
Row：General processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field programmable gate array (FPGA) or
Any combinations of other programmable logic device, discrete gate or transistor logic, discrete hardware component or these components.It is logical
Can be microprocessor with processor, but alternatively, processor can be any conventional processors, controller, microcontroller
Device or state machine.Processor can also be implemented as the combination of computing device, for example, the combination of DSP and microprocessor, Duo Gewei
Processor, one or more microprocessors combination DSP and/or any other this configuration.
The function of JTAG link blocks 1 can be realized in hardware, software, firmware or its arbitrary combination.If in software
Middle realization then can may be stored on the computer-readable medium or pass through meter using the function as one or more instruction or code
Calculation machine readable medium transmits.Computer-readable medium includes computer storage media and communication media, which includes
Contribute to any medium that computer program is transmitted to another position from a position.Storage medium can be led to
With or special purpose computer access any usable medium.As an example and not restrictive, which can wrap
RAM, ROM, EEPROM, CD-ROM or other optical disc memory apparatus, disk storage equipment or other magnetic storage apparatus are included, or
Can be used for carry or storage form be instruct or data structure required program code and can be by general or specialized meter
Any other medium that calculation machine or general or specialized processor access.In addition, any connection can be properly termed as calculating
Machine readable medium.For example, if using coaxial cable, optical fiber cable, twisted-pair feeder, digital subscriber line (DSL) or such as infrared
The wireless technology of line, radio and microwave come from website, server or other remote sources send software, then above-mentioned coaxial cable,
Fiber optic cable, twisted-pair feeder, DSL or such as wireless technology of infrared ray, radio and microwave are included in the definition of medium.Such as this
In used in, disk and CD include compact disk (CD), laser disk, CD, digital versatile disc (DVD), floppy disk, blue light
Disk, wherein disk usually magnetically reproduce data, and CD using laser optics reproduce data.The combination of the above is also answered
In the range of being included in computer-readable medium.
In some embodiments, handover module 2 includes that three four-ways switch chip and a single channel switching chip,
Enable Pin TCK, TMS, TRST of two chip under test are parallel to JTAG link blocks 1 by three four-way switching chips, and
The data terminal TDI of JTAG link blocks 1 is connected to the data terminal TDI of two chip under test；Single channel switches chip by two
The data terminal TDO of chip under test is connected to the data terminal TDO of JTAG link blocks 1.
As shown in figure 3, the embodiment of the present invention is reduced on the basis of existing technology uses a JTAG connector, then make
It uses 34 channels switching chips and 1 single channel to switch chip as handover module 2, and utilizes BMC chip (i.e. control module 3)
Two GPIO (i.e. output end) realize the switching of JTAG link topology.Fig. 2 shows specific topology, wherein Switch0,
Switch1, Switch2 chip are that 4 channels switch chip, when SEL signals (switching Enable Pin) are high level, A=B1；When
When SEL signals are low level, A=B0.In addition, Switch3 chips, which are single channel, switches chip, it is similar to 4 channels switching chip
Ground, with when SEL signals be high level when, A=B1；When SEL signals are low level, A=B0.The institute of CHIP0, CHIP1 chip
There is pin to be all connected directly to the channels B0 of corresponding switching chip, i.e., chip is connected when SEL signals are low.
It should be noted that the embodiment of the present invention can also use the switching entirely different with said program and controlling party
Formula.For example, the switching chip channel that CHIP0, CHIP1 chip are connected is revised as B1 by those skilled in the art, adapt to simultaneously
Change to property the output level (phase inverter or BMC chip is added directly to export inversion signal) of GPIO, so that it may not change 34
Channel only adjusts the connection of handover module 2 and CHIP0, CHIP1 chip under the premise of switching chip and 1 single channel switching chip
Relationship, and achieve the effect that be identical with the embodiment of the present invention；On the other hand, those skilled in the art switch core using 18 channel
Piece, which substitutes arbitrary 24 channels switching chip or switches 14 channel of chip replacement using 18 channel, switches 1 single-pass of chip
Road switches chip, can also reduce the usage quantity of chip under the premise of not changing connection relation, and reaches and present invention reality
Apply the identical effect of example.Those skilled in the art also have the ability and wish selects suitably to implement according to specific application scenarios
Mode.It will be understood therefore that the specific implementation mode of the handover module 2 of the made description of the embodiment of the present invention is only numerous available
One of mode, which should not be used as the limitation of protection domain.
In some embodiments, three four-way switching chips and a single channel switching chip are all made of QFN encapsulation；
Control module 3 is BMC chip.The SEL signals of switching chip are connected to the GPIO of BMC chip, the level real-time control SEL letters of GPIO
It number switches over.QFN encapsulation can occupy less PCB arrangement spaces.
In some embodiments, two chip under test are the first chip under test and the second chip under test；Control module 3 has
Have the first output end and a second output terminal, the first output end and second output terminal be connected to the switching Enable Pin of handover module 2 with
Control the method that apparatus for testing chip tests two chip under test.
First output end and second output terminal respectively have there are two state (1 and 0), have altogether 00,01,10,11 4 it is defeated
Go out, it is corresponding respectively not test, test the first chip under test, the second chip under test of test while the first chip under test of test and the
Two operating modes of chip under test four.Specific operating mode description is seen below：
In the case where the first output end and second output terminal export high level, apparatus for testing chip neither tests first
Chip under test does not test the second chip under test again, the signal and its output end that the input terminal TDO of JTAG link blocks 1 is received
The signal that TDI is sent is identical.
This operating mode is as shown in figure 4, GPIO0 the and GPIO1 pins of BMC chip are all set to 1 so that Switch0,
Switch1, Switch2, Switch3 switch all high level of SEL signals (i.e. A=B1) of chip, at this time by jtag test
The signal that tool is sent out is switched to the channels B1 through switching chip A channel, because the JTAG without inputting CHIP0, CHIP1 chip connects
Mouthful.
In the case of the first output end output low level second output terminal output high level, apparatus for testing chip test
First chip under test and the second chip under test is bypassed, the signal that the input terminal TDO of JTAG link blocks 1 is received is the first quilt
Survey the signal that the output end TDO of chip is sent.
This operating mode is set to 1 as shown in figure 5, the GPIO0 of BMC chip is set to 0, GPIO1, therefore Switch0,
The SEL signals that Switch1 switches chip are low level (A=B0), and the SEL signals of Switch2, Switch3 switching chip are
High level (A=B1).The signal (TCK, TMS, TRST and TDI) sent out at this time by jtag test tool is via Switch0 chips
A channel be switched to the channels B0, be input to the jtag interface of CHIP0 chips.The JTAG signal exported via Switch1 chips
(TCK_1, TMS_1, TRST_1 and TDI_1) switches to the channels B1 by A channel by Switch2 chips and is bypassed, because without
The jtag interface of CHIP1 chips can be inputted.The TDO signal that CHIP0 chips are sent is switched to A channel by Switch3 chips by B1,
Jtag test tool finally is fed back to, to realize that the jtag interface of CHIP0 chips is connected to jtag test tool.
High level is exported in the first output end, in the case of second output terminal output is low level, apparatus for testing chip test
Second chip under test and the first chip under test is bypassed, the signal that the input terminal TDO of JTAG link blocks 1 is received is the second quilt
Survey the signal that the output end TDO of chip is sent.
This operating mode is set to 0 as shown in fig. 6, the GPIO0 of BMC chip is set to 1, GPIO1, therefore Switch0,
The SEL signals that Switch1 switches chip are high level (A=B1), and the SEL signals of Switch2, Switch3 switching chip are
Low level (A=B0).The signal (TCK, TMS, TRST and TDI) sent out at this time by jtag test tool is via Switch0 chips
A channel be switched to the channels B1 and be bypassed, because without input CHIP0 chips jtag interface.It is defeated via Switch1 chips
The JTAG signal (TCK_1, TMS_1, TRST_1 and TDI_1) gone out switches to the channels B0 by Switch2 chips by A channel, defeated
Enter the jtag interface to CHIP1 chips.The TDO signal that CHIP1 chips are sent is switched to A channel by Switch3 chips by B0, most
Jtag test tool is fed back to eventually, and jtag test tool is connected to realize that CHIP1 chips obtain jtag interface.
Low level, apparatus for testing chip test first simultaneously is exported in the first output end and second output terminal
The operated in series connection situation of chip under test and the second chip under test, the signal that the input terminal TDO of JTAG link blocks 1 is received are the
The signal that the signal that the output end TDO of one chip under test is sent is sent after the processing of the second chip under test by its output end TDO.
This operating mode is as shown in fig. 7, GPIO0 the and GPIO1 pins of BMC chip are all set to 0 so that Switch0,
Switch1, Switch2, Switch3 switch all low levels of SEL signals (i.e. A=B0) of chip, at this time by jtag test
The signal (TCK, TMS, TRST and TDI) that tool is sent out is switched to the channels B0 via the A channel of Switch0 chips, is input to
The jtag interface of CHIP0 chips.The JTAG signal (TCK_1, TMS_1, TRST_1 and TDI_1) exported via Switch1 chips
The channels B0 are switched to by A channel by Switch2 chips, are input to the jtag interface of CHIP1 chips.Switch3 chips will be by
The TDO signal that CHIP1 chips are sent switches to A channel by the channels B0, finally feeds back to jtag test tool, to realize simultaneously
Gate the function of CHIP0, CHIP1 chip jtag interface.Since jtag test tool only supports test one single chip, this pattern
Actually the first chip under test of series winding and the second chip under test are tested as a unified chip, the two is herein
Completely the same Enable Pin is used under state.
Four kinds of above-mentioned operating modes, various illustrative logical blocks, module, circuit can in conjunction with described in disclosure herein
To be implemented as the combination of electronic hardware, computer software or both.It can be mutual in order to clearly demonstrate this of hardware and software
It is transsexual, general description has been carried out to it with regard to the function of various exemplary components, square, module, circuit and step.This
Kind function is implemented as software and is also implemented as hardware depending on concrete application and is applied to the design of whole system about
Beam.Those skilled in the art can realize the function in various ways for each concrete application, but this realization
Decision should not be interpreted as causing a departure from range disclosed by the embodiments of the present invention.
In some embodiments, the first output end and the level of second output terminal can at any time switch with real-time
Change the operating mode of apparatus for testing chip.Electricity, which need not be descended, or ressemble chip can significantly save the testing time and carry
High working efficiency.
From above-described embodiment as can be seen that apparatus for testing chip provided in an embodiment of the present invention, by using single JTAG
Connector is connected to two chip under test and under the control of control module according to working method pair two simultaneously via handover module
The technical solution of a chip under test selectivity test, can be directed to different chips or different types of chip carry out flexibly switching with
Test reduces the volume of JTAG link topology and easy to operation.
Those of ordinary skills in the art should understand that：The discussion of any of the above embodiment is exemplary only, not
It is intended to imply that range disclosed by the embodiments of the present invention (including claim) is limited to these examples；In the think of of the embodiment of the present invention
Under road, it can also be combined between the technical characteristic in above example or different embodiments, and exist as described above
Many other variations of the different aspect of the embodiment of the present invention, for simplicity, they are not provided in details.Therefore, all at this
Within the spirit and principle of inventive embodiments, any omission, modification, equivalent replacement, improvement for being made etc. should be included in this hair
Within the protection domain of bright embodiment.
Claims (10)
1. a kind of apparatus for testing chip, which is characterized in that including：
There is JTAG link blocks jtag test tool and single JTAG connectors, the jtag test tool to be mounted on described
On single JTAG connectors；
Handover module, the single JTAG connectors are connected to two chip under test, the switching mould by the handover module
Block switchably provides the output of the jtag test tool to the input terminal of described two chip under test and is surveyed to the JTAG
The input terminal of trial work tool provides the output of described two chip under test；
Control module, is connected to the handover module, and the control module is carried by the switching Enable Pin to the handover module
The mode that the jtag test tool tests described two chip under test is controlled for high/low level.
2. the apparatus according to claim 1, which is characterized in that described two chip under test be equipped with input terminal TCK, TMS,
TRST, TDI and output end TDO；The JTAG link blocks correspondingly be equipped with output end TCK, TMS, TRST, TDI and
Input terminal TDO.
3. the apparatus according to claim 1, which is characterized in that the handover module include three four-ways switch chips and
One single channel switches chip, three four-ways switching chip by Enable Pin TCK, TMS of described two chip under test,
TRST is parallel to the JTAG link blocks, and the data terminal TDI of the JTAG link blocks is connected to described two quilts
Survey the data terminal TDI of chip；The data terminal TDO of described two chip under test is connected to described by the single channel switching chip
The data terminal TDO of JTAG link blocks.
4. device according to claim 3, which is characterized in that three four-ways switching chip and a single channel are cut
It changes chip and is all made of QFN encapsulation；The control module is BMC chip.
5. the apparatus according to claim 1, which is characterized in that described two chip under test are the first chip under test and second
Chip under test；The control module has the first output end and second output terminal, first output end and second output
The switching Enable Pin that end is connected to the handover module is tested with controlling apparatus for testing chip described in described two chip under test
Mode.
6. device according to claim 5, which is characterized in that defeated in first output end and the second output terminal
In the case of going out high level, apparatus for testing chip neither tests first chip under test and does not test the described second tested core
Piece, the signal that the input terminal TDO of the JTAG link blocks is received are identical as the signal that its output end TDI is sent.
7. device according to claim 5, which is characterized in that export low level and described the in first output end
In the case that two output ends export high level, apparatus for testing chip tests first chip under test and bypasses second quilt
Chip is surveyed, the signal that the input terminal TDO of the JTAG link blocks is received is sent out for the output end TDO of first chip under test
The signal sent.
8. device according to claim 5, which is characterized in that export high level and described the in first output end
In the case of the output of two output ends is low level, apparatus for testing chip tests second chip under test and bypasses first quilt
Chip is surveyed, the signal that the input terminal TDO of the JTAG link blocks is received is sent out for the output end TDO of second chip under test
The signal sent.
9. device according to claim 5, which is characterized in that defeated in first output end and the second output terminal
Go out it is low level in the case of, apparatus for testing chip tests the series winding of first chip under test and second chip under test simultaneously
Working condition, the signal that the input terminal TDO of the JTAG link blocks is received are the output end TDO of first chip under test
The signal that the signal of transmission is sent after second chip under test processing by its output end TDO.
10. device according to claim 5, which is characterized in that the electricity of first output end and the second output terminal
It is flat to switch at any time to change the operating mode of apparatus for testing chip in real time.
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| CN201810738353.XA CN108646172B (en) | 2018-07-06 | 2018-07-06 | Chip testing device |
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| CN201810738353.XA CN108646172B (en) | 2018-07-06 | 2018-07-06 | Chip testing device |
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| CN108646172B CN108646172B (en) | 2020-08-18 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112466381A (en) * | 2020-11-26 | 2021-03-09 | 西安微电子技术研究所 | Test chip suitable for testing DDR3 physical layer electrical function |
| CN112559418A (en) * | 2020-12-07 | 2021-03-26 | 天津津航计算技术研究所 | JTAG switching circuit |
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| CN112466381A (en) * | 2020-11-26 | 2021-03-09 | 西安微电子技术研究所 | Test chip suitable for testing DDR3 physical layer electrical function |
| CN112466381B (en) * | 2020-11-26 | 2022-09-13 | 西安微电子技术研究所 | Test chip suitable for testing DDR3 physical layer electrical function |
| CN112559418A (en) * | 2020-12-07 | 2021-03-26 | 天津津航计算技术研究所 | JTAG switching circuit |
| CN112559418B (en) * | 2020-12-07 | 2022-10-14 | 天津津航计算技术研究所 | JTAG switching circuit |
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