CN108535629B

CN108535629B - Ethernet circuit testing system and method

Info

Publication number: CN108535629B
Application number: CN201810276478.5A
Authority: CN
Inventors: 张大江
Original assignee: Xian Microelectronics Technology Institute
Current assignee: Xian Microelectronics Technology Institute
Priority date: 2018-03-30
Filing date: 2018-03-30
Publication date: 2020-12-25
Anticipated expiration: 2038-03-30
Also published as: CN108535629A

Abstract

The invention discloses an Ethernet circuit testing system and method, which comprises two Ethernet circuits, wherein each Ethernet circuit is provided with a PHY module, the PHY modules of the two Ethernet circuits are directly interconnected through a copper medium or an optical fiber medium, the other ends of the two Ethernet circuits are respectively connected with ATE monitoring, the two Ethernet circuits are simultaneously tested, and the ATE monitoring simulates I/O signals and power supplies required by the two Ethernet circuits. The invention has short development period and strong universality and can meet the test requirement of the Ethernet circuit containing the PHY module.

Description

Ethernet circuit testing system and method

Technical Field

The invention belongs to the technical field of network communication testing, and particularly relates to an Ethernet circuit testing system and method.

Background

The main idea of the current functional Test of integrated circuits is to apply a proper excitation signal to the input end of the circuit through ATE (Auto Test Equipment), and then monitor the output of the circuit through ATE to determine whether the circuit meets the functional specification, as shown in fig. 1.

The method is suitable for the integrated circuit of which the ATE can meet all the required input and output logic signals, but the limitation of the method is more and more prominent along with the more and more complex functions of the integrated circuit, the development period of a test program of the complex integrated circuit is longer and longer, and the test cost is increased; moreover, some input signals required by the integrated circuit under test often generate output signals beyond the capability range of the ATE itself, and thus the test cannot be completed.

The test program development of ethernet circuit faces two problems:

1) the 4D-PAM5 level coding ATE required by some ethernet PHY modules cannot provide (ATE can only provide three levels, 0, 1 and Z);

2) when the Ethernet circuit PHY modules are interconnected, no matter whether the interconnection medium is a copper twisted pair or an optical fiber, the PHY modules automatically start an auto-negotiation process so as to determine the communication speed, full duplex or half duplex and the like, the process is automatically initiated by the Ethernet circuit PHY modules, and the time starting point and the times of signal transmission are randomly uncertain. ATE can only address the processing of signals whose signal send and receive time starts relatively fixed.

Testing of ethernet circuits containing PHY modules cannot be achieved by relying solely on the capabilities of the generic ATE itself.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a system and a method for testing an ethernet circuit, which solve the problems of 4D-PAM5 level coding required by testing an ethernet circuit with PHY and implementing an "auto-negotiation" process of a PHY block on ATE.

The invention adopts the following technical scheme:

the Ethernet circuit testing system comprises two Ethernet circuits, each Ethernet circuit is provided with a PHY module, the PHY modules of the two Ethernet circuits are directly interconnected through a copper medium or an optical fiber medium, the other ends of the two Ethernet circuits are respectively connected with ATE monitoring, the two Ethernet circuits are simultaneously tested, and the ATE monitoring simulates I/O signals and power supplies required by the two Ethernet circuits.

Specifically, the two PHY modules are both provided with optical fiber interfaces, and the optical fiber signal line connects the two PHY modules in a differential direct-to-direct receiving and transmission cross-connection manner.

Further, the transmission rate of the optical fiber signal line is 1.25 GHz.

Specifically, the two PHY modules are respectively provided with a copper medium interface, four pairs of copper medium differential signal lines are connected with two kilomega RJ-45 integrated sockets according to the requirements of the RJ-45 sockets, and the two kilomega RJ-45 integrated sockets are interconnected through a standard 5-class twisted pair.

Specifically, the ethernet circuit to be tested includes a BGA117 package circuit.

A test method of an Ethernet circuit test system comprises the following steps:

the ATE monitors and controls the power-on and power-off processes of the two Ethernet circuits, after the power-on processes, the two Ethernet circuits to be tested are configured through the standard digital signal wire, the auto-negotiation result of the two Ethernet circuits is read after the PHY modules of the two Ethernet circuits finish auto-negotiation, and whether the auto-negotiation function is normal or not is verified;

after the auto-negotiation is completed, the ATE monitors and controls the two Ethernet circuits to respectively start sending actions according to specified contents, the sent data are received by the object Ethernet circuit through a copper medium or an optical fiber medium, and the ATE respectively reads the data received by the two circuits and compares the data with the sent data to complete the test of the data receiving and sending related functions of the two Ethernet circuits.

Compared with the prior art, the invention has at least the following beneficial effects:

the two Ethernet circuits are respectively provided with the PHY module, the PHY modules of the two Ethernet circuits are directly interconnected through a copper medium or an optical fiber medium, and the other ends of the two Ethernet circuits are respectively connected with the ATE monitoring circuit, so that the difficulty that ATE simulates the PHY side protocol of the Ethernet circuit is avoided, the difficulty of the development of the test program of the Ethernet circuit is reduced, the development period of the test program is greatly shortened, the development cost of the test is greatly saved, the limitation of solving the self test capability of the ATE is made up, and the test of the PHY-containing Ethernet circuit on the ATE is impossible.

Furthermore, the optical fiber signal wires adopt differential direct-to-direct receiving and transmitting cross-connection, and the PHY module automatically starts an auto-negotiation process so as to determine the communication speed, full duplex or half duplex.

Furthermore, the Ethernet circuit testing device has strong applicability to the Ethernet circuits of the same series or similar functions, and can be applied to the Ethernet circuit testing of various packaging forms of other models only by simple modification.

The invention also discloses a test method of the Ethernet circuit test system, which solves the problem that the ATE can not provide multi-level signals required by the test of the Ethernet circuit PHY module, solves the problems of uncertain speed, uncertain signal sending time point, uncertain self-negotiation frequency and the like in the process of self-negotiation of the Ethernet circuit PHY module which is difficult to realize and time-consuming by utilizing the ATE, avoids the complex coding format and protocol of data signals in a copper medium or optical fiber medium communication line realized by the ATE, focuses on the sending and receiving results of self-negotiation and communication regulation data, does not realize the process in detail any more, greatly reduces the difficulty of the Ethernet circuit test program, reduces the workload of developers, shortens the development period of the test program and accelerates the development speed.

In conclusion, the invention has short development period and strong universality, and can meet the test requirement of the Ethernet circuit containing the PHY module.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

FIG. 1 is a block diagram of a conventional ATE circuit testing scheme;

FIG. 2 is a block diagram of an Ethernet circuit testing scheme of the present invention;

fig. 3 is a diagram illustrating an example of a testing method for a gigabit ethernet PHY circuit.

Detailed Description

Referring to fig. 2, the present invention provides an ethernet circuit testing system, which includes two ethernet circuits, each ethernet circuit is provided with a PHY module, the PHY modules of the two ethernet circuits are directly interconnected through a copper twisted pair or an optical fiber medium, the other ends of the two ethernet circuits are respectively connected to an ATE monitoring circuit, all the remaining I/O signals and power supplies required by the two ethernet circuits are simulated by the ATE, and the two ethernet circuits are used for testing simultaneously.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to FIG. 3, an embodiment of the testing scheme of the present invention in an Ethernet circuit test is shown

The Ethernet circuit is BGA117 package, BGA is package type, 117 is circuit pin number, different circuit pin number is variable, integrated circuit package type is various, there are DIP, QFP, TQFP, PGA and so on, the corresponding frame of the circuit to be tested and the auxiliary circuit in the figure is the top view of the test fixture used by the circuit to be tested.

PHY modules of the two Ethernet circuits are directly, receiving and transmitting are crossed and interconnected by adopting differential lines through two pairs of 1.25GHz optical fiber signal lines;

the four pairs of copper medium differential signal lines of the PHY module are connected to the kilomega RJ-45 integrated sockets according to the requirements of the standard RJ-45 sockets, and the two kilomega RJ-45 integrated sockets are interconnected through standard 5-type twisted-pair lines.

The realization of the direct interconnection between the two media PHY, namely the optical fiber medium and the copper medium, perfectly solves the limitation that 4D-PAM5 level coding ATE required by a PHY module copper medium signal line test cannot provide, and the difficult problem that the PHY block 'auto-negotiation' process is difficult to realize on ATE under the two media modes, and simultaneously reasonably avoids the heavy workload of a test program developer for realizing 'complex coding format and protocol of data signals in a copper medium or optical fiber medium communication line' by utilizing simulation.

And the rest signal pins, the power supply and the like of the two Ethernet circuits with the same model are all connected to corresponding test resources of the ATE through connectors. And the ATE controls the power-on and power-off processes of the two Ethernet circuits, after the power-on processes, the two Ethernet circuits to be tested are subjected to various configurations through the standard digital signal wire, the self-negotiation result of the PHY module of the two circuits is read after the self-negotiation of the PHY module of the two circuits is finished, so that whether the self-negotiation function of the PHY module of the two circuits is normal or not is verified, if the corresponding test item of the normal ATE in the test result or the test data is marked as 'PASS (PASS'), and if not, the corresponding test item of the normal ATE in the.

After the self-negotiation is finished, the ATE controls the two Ethernet circuits to respectively start sending actions according to specified contents, the sent data are received by the object Ethernet circuit through a copper medium or an optical fiber medium according to a coding format and a protocol specified by the corresponding medium, and the ATE respectively reads the data received by the two circuits and compares the data with the sent data, so that the test of the data receiving and sending related functions of the two Ethernet circuits is realized.

The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A test method of an Ethernet circuit test system is characterized in that the Ethernet circuit test system comprises two Ethernet circuits, each Ethernet circuit is provided with a PHY module, the two PHY modules are provided with optical fiber interfaces, and an optical fiber signal line is connected with the two PHY modules in a differential line-to-line receiving and transmitting cross interconnection mode; the two PHY modules are respectively provided with a copper medium interface, four pairs of copper medium differential signal lines are connected with two kilomega RJ-45 integrated sockets according to the requirements of the RJ-45 sockets, the two kilomega RJ-45 integrated sockets are interconnected through a standard 5-class twisted pair, the PHY modules of the two Ethernet circuits are directly interconnected through a copper medium or an optical fiber medium, the transmission rate of the optical fiber signal line is 1.25GHz, the other ends of the two Ethernet circuits are respectively connected with ATE monitoring, the two Ethernet circuits are simultaneously tested, the ATE monitoring simulates I/O signals and power supplies required by the two Ethernet circuits, the Ethernet circuit to be tested comprises a BGA117 packaging circuit, and the method comprises the following steps: