CN108535629A - A kind of ethernet circuit test system and method - Google Patents
A kind of ethernet circuit test system and method Download PDFInfo
- Publication number
- CN108535629A CN108535629A CN201810276478.5A CN201810276478A CN108535629A CN 108535629 A CN108535629 A CN 108535629A CN 201810276478 A CN201810276478 A CN 201810276478A CN 108535629 A CN108535629 A CN 108535629A
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- ethernet
- circuit
- circuits
- ate
- ethernet circuit
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
Abstract
The invention discloses a kind of ethernet circuits to test system and method, including two ethernet circuits, PHY modules are both provided on every ethernet circuit, it is directly interconnected by copper medium or fiber medium between the PHY modules of two ethernet circuits, the other end of two ethernet circuits monitors with ATE connect respectively, two ethernet circuits are tested simultaneously, and I/O signals and power supply needed for two ethernet circuits of simulation are monitored by ATE.Development cycle of the invention is short, versatile, disclosure satisfy that the ethernet circuit testing requirement of module containing PHY.
Description
Technical field
The invention belongs to network communication technical field of measurement and test, and in particular to a kind of ethernet circuit test system and method.
Background technology
The functional test main thought of integrated circuit is that (test is set Auto Test Equipment automatically by ATE at present
It is standby) in the input terminal application pumping signal appropriate of circuit, then by the output of ATE observation circuits, whether decision circuit meets
Functional specification, as shown in Figure 1.
This method be suitable for ATE itself can meet fully enter needed for it, the integrated circuit of output logic signal, still
It becomes increasingly complex with the function of integrated circuit, the limitation of this method increasingly highlights, complicated integrated circuit testing
The development cycle of program is increasingly longer, increases testing cost；And certain input signals needed for to-be-measured integrated circuit generate
Output signal often the limit of power more than ATE itself and can not complete to test.
The test program exploitation of ethernet circuit just faces such two problems：
1) the required 4D-PAM5 level codings ATE of certain ethernet circuit PHY modules can not provide that (ATE can only be provided
0,1 and Z, tri- kinds of level)；
2) when being interconnected between ethernet circuit PHY modules, no matter interconnection media is copper twisted-pair feeder or optical fiber, PHY moulds
Block starts " auto-negotiation " process automatically, and to determine communication speed, full duplex or half-duplex etc., the process is by ethernet circuit
PHY modules automatically initiate, and start time, the number of signal transmission are random uncertain.And ATE can only solve signal transmission
With the processing of the relatively-stationary signal of receiving time starting point.
So relying solely on general ATE self-ability cannot achieve the ethernet circuit test containing PHY modules.
Invention content
In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is that providing a kind of Ethernet electricity
Path test system and method solve 5 level codings of 4D-PAM needed for the test of ethernet circuit containing PHY and are realized on ATE
PHY Block " auto-negotiation " process.
The present invention uses following technical scheme：
A kind of ethernet circuit tests system, including two ethernet circuits, and PHY is both provided on every ethernet circuit
Module is directly interconnected by copper medium or fiber medium between the PHY modules of two ethernet circuits, two ethernet circuits
The other end monitors with ATE connect respectively, and two ethernet circuits are tested simultaneously, and two ethernet circuit institutes of simulation are monitored by ATE
Need I/O signals and power supply.
Specifically, two PHY modules are both provided with optical fiber interface, fiber-optic signal line is handed over using the direct sending and receiving of differential pair
It pitches mutual contact mode and connects two PHY modules.
Further, the transmission rate of fiber-optic signal line is 1.25GHz.
Specifically, two PHY modules are both provided with copper Media Interface Connector, using four pairs of copper medium differential signal lines according to RJ-
45 sockets require to connect with two gigabit RJ-45 integrated sockets, and two gigabit RJ-45 integrated sockets pass through 5 class multiple twin of standard again
Line interconnects.
Specifically, ethernet circuit to be measured includes BGA117 encapsulated circuits.
A kind of test method of ethernet circuit test system, includes the following steps：
The upward and downward electric process of two ethernet circuits of ATE monitoring and controllings, after the power is turned on by two, standardized digital signal line pair
Ethernet circuit to be measured is configured, and waits for reading its auto-negotiation as a result, verification is self tuning after the completion of two circuit PHY modules auto-negotiations
Quotient's function normally whether；
Sending action is respectively started according to regulation content in two ethernet circuits of ATE monitoring and controllings after the completion of auto-negotiation, hair
The data sent are received by copper medium or fiber medium by object ethernet circuit, and ATE reads two circuits and receives respectively again
Data and compared with transmitted data, complete test to two ethernet circuit data transmit-receive correlation functions.
Compared with prior art, the present invention at least has the advantages that：
PHY modules are both provided on two ethernet circuits of the invention, are passed through between the PHY modules of two ethernet circuits
Copper medium or fiber medium directly interconnect, and the other end of two ethernet circuits is connect with ATE observation circuits respectively, is avoided
ATE simulates the problem of the sides ethernet circuit PHY agreement, reduces the difficulty of ethernet circuit test program exploitation, greatly contracts
The short development cycle of test program, the development cost of test is greatly saved, makes up the office for solving ATE selftest abilities
Limit so that ethernet circuit containing PHY is tested on ATE by being very unlikely to become possibility.
Further, fiber-optic signal line is cross interconnected using the direct sending and receiving of differential pair, and PHY modules start " self tuning automatically
Quotient " process, to determine communication speed, full duplex or half-duplex.
Further, to very strong with a series of or identity function ethernet circuit applicability, it need to only do and simply repair
Change the ethernet circuit circuit test that just can apply to the various packing forms of other models.
The invention also discloses the test methods that a kind of ethernet circuit tests system, solve the survey that ATE cannot achieve
The required multi-level signal of examination too net circuit PHY modules provides problem, solves to implement using ATE itself and be stranded very much
" rate is indefinite ", " signal sending time point is indefinite ", " oneself during difficult, very time-consuming too net circuit PHY modules " auto-negotiation "
It is indefinite to negotiate number " the problems such as, avoid and realized with ATE that " data-signal in copper medium or fiber medium communication line is answered
Miscellaneous coded format and agreement ", ATE pay close attention to the transmitting and receiving of " auto-negotiation " and " communication regulation data " as a result, no longer having
Body realizes its process, greatly reduces the difficulty of ethernet circuit test program, reduces the workload of developer, to
The development cycle for shortening test program, accelerate development rate.
In conclusion the development cycle of the invention is short, and it is versatile, it disclosure satisfy that the test of the ethernet circuit of module containing PHY needs
It asks.
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Description of the drawings
Fig. 1 is tradition ATE circuit test scheme block diagrams；
Fig. 2 is ethernet circuit testing scheme block diagram of the present invention；
Fig. 3 is certain gigabit Ethernet PHY circuit test method instance graph.
Specific implementation mode
Referring to Fig. 2, the present invention provides a kind of ethernet circuit test system, including two ethernet circuits, every
PHY modules are both provided on ethernet circuit, the PHY modules of two ethernet circuits are direct by copper twisted pair cable or fiber medium
Interconnection, the other end of two ethernet circuits are connect with ATE observation circuits respectively, are simulated needed for two ethernet circuits by ATE
Remaining whole I/O signal and power supply, tested simultaneously using two ethernet circuits.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being described and shown in usually here in attached drawing is real
Applying the component of example can be arranged and be designed by a variety of different configurations.Therefore, the present invention to providing in the accompanying drawings below
The detailed description of embodiment be not intended to limit the range of claimed invention, but be merely representative of the selected of the present invention
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without creative efforts
The every other embodiment obtained, shall fall within the protection scope of the present invention.
Referring to Fig. 3, a specific example for testing scheme proposed by the invention in the test of certain ethernet circuit
Ethernet circuit encapsulates for BGA117, and BGA is packing forms, and 117 be circuit number of pin, different circuit number of pins
It is indefinite to measure, and integrated antenna package form is varied, there is a DIP, QFP, TQFP, PGA etc., circuit under test and auxiliary circuit in figure
Corresponding box is circuit under test used test fixture top view.
The PHY modules of two ethernet circuits use the direct sending and receiving of differential pair by two pairs of 1.25GHz fiber-optic signal lines
It is cross interconnected；
Four pairs of copper medium differential signal lines of PHY modules are connected to gigabit RJ-45 according to the requirement of standard Registered Jack-45 and integrate
Socket, two gigabit RJ-45 integrated sockets are interconnected by standard category 5 twisted pair again.
PHY module copper Jie has been solved perfectly in the realization directly interconnected between two kinds of medium PHY of above-mentioned fiber medium and copper medium
PHY Block " oneself under 5 level coding ATE of 4D-PAM can not be provided needed for the test of matter signal wire limitation and two media mode
Negotiate " problem that is difficult to realize on ATE of process, while reasonably avoiding test program developer utilizes simulated implementation " copper
The hard work amount of the complicated coded format and agreement of medium or the data-signal in fiber medium communication line ".
Two are all connected to ATE phases with remaining signal pin of model ethernet circuit and power supply etc. by connector
The test resource answered.ATE controls the upward and downward electric process of two ethernet circuits, after the power is turned on by two, standardized digital signal line pair
Ethernet circuit to be measured carries out various configurations, wait for reading its " auto-negotiation " after the completion of two circuit PHY modules " auto-negotiation " as a result,
Whether to verify its " auto-negotiation " function normally, correspondence test item marks of the ATE in test result or test data if normal
Show " qualified (PASS) ", otherwise " failure (FAIL) ".
ATE controls two ethernet circuits and sending action is respectively started according to regulation content after the completion of " auto-negotiation ", sends
Data by copper medium or fiber medium according to coded format and agreement as defined in corresponding medium by object ethernet circuit
It receives, ATE reads the data that two circuits receive and respectively again compared with transmitted data, to realize to two Ethernet electricity
Circuit-switched data receives and dispatches the test of correlation function.
The above content is merely illustrative of the invention's technical idea, and protection scope of the present invention cannot be limited with this, every to press
According to technological thought proposed by the present invention, any change done on the basis of technical solution each falls within claims of the present invention
Protection domain within.
Claims (6)
1. a kind of ethernet circuit tests system, which is characterized in that equal on every ethernet circuit including two ethernet circuits
Be provided with PHY modules, directly interconnected by copper medium or fiber medium between the PHY modules of two ethernet circuits, two with
Too the other end of net circuit monitors with ATE connect respectively, and two ethernet circuits test simultaneously, by ATE monitorings simulate two with
Too I/O signals and power supply needed for net circuit.
2. a kind of ethernet circuit according to claim 1 tests system, which is characterized in that two PHY modules are respectively provided with
There are optical fiber interface, fiber-optic signal line to connect two PHY modules using the cross interconnected mode of the direct sending and receiving of differential pair.
3. a kind of ethernet circuit according to claim 2 tests system, which is characterized in that the transmission speed of fiber-optic signal line
Rate is 1.25GHz.
4. a kind of ethernet circuit according to claim 1 tests system, which is characterized in that two PHY modules are respectively provided with
There is copper Media Interface Connector, is required and two gigabit RJ-45 integrated sockets according to Registered Jack-45 using four pairs of copper medium differential signal lines
Connection, two gigabit RJ-45 integrated sockets are interconnected by standard category 5 twisted pair again.
5. a kind of ethernet circuit according to claim 1 tests system, which is characterized in that ethernet circuit to be measured includes
BGA117 encapsulated circuits.
6. a kind of test method for testing system according to any one of claim 1 to 5 ethernet circuit, feature exist
In including the following steps：
The upward and downward electric process of two ethernet circuits of ATE monitoring and controllings, it is to be measured by two, standardized digital signal line pair after the power is turned on
Ethernet circuit is configured, and waits for reading its auto-negotiation as a result, verification auto-negotiation work(after the completion of two circuit PHY modules auto-negotiations
Whether can be normally；
Sending action is respectively started according to regulation content in two ethernet circuits of ATE monitoring and controllings after the completion of auto-negotiation, transmission
Data are received by copper medium or fiber medium by object ethernet circuit, and ATE reads the number that two circuits receive respectively again
According to and with compared with transmitted data, the test to two ethernet circuit data transmit-receive correlation functions is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810276478.5A CN108535629B (en) | 2018-03-30 | 2018-03-30 | Ethernet circuit testing system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810276478.5A CN108535629B (en) | 2018-03-30 | 2018-03-30 | Ethernet circuit testing system and method |
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| Publication Number | Publication Date |
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| CN108535629A true CN108535629A (en) | 2018-09-14 |
| CN108535629B CN108535629B (en) | 2020-12-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810276478.5A Active CN108535629B (en) | 2018-03-30 | 2018-03-30 | Ethernet circuit testing system and method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111060772A (en) * | 2019-12-31 | 2020-04-24 | 瑞斯康达科技发展股份有限公司 | Test system and test method |
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| Publication number | Publication date |
|---|---|
| CN108535629B (en) | 2020-12-25 |
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