CN204069014U - Gigabit Ethernet interface device - Google Patents
Gigabit Ethernet interface device Download PDFInfo
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- CN204069014U CN204069014U CN201420518002.5U CN201420518002U CN204069014U CN 204069014 U CN204069014 U CN 204069014U CN 201420518002 U CN201420518002 U CN 201420518002U CN 204069014 U CN204069014 U CN 204069014U
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- gigabit ethernet
- transformer
- chip
- network interface
- interface device
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- 238000000034 method Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
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Abstract
The utility model discloses a kind of gigabit ethernet interface device.It comprises fpga chip, gigabit Ethernet physical chip, transformer and network interface, fpga chip, gigabit Ethernet physical chip and transformer are electrically connected successively, transformer is connected with outside network interface connector by network interface, wherein, gigabit Ethernet physical chip is connected with transformer with a pair negative differential signal line by a pair positive differential holding wire, and transformer is connected with network interface with a pair negative differential signal line by a pair positive differential holding wire.Gigabit ethernet interface device of the present utility model can be applicable to the design of gigabit ethernet interface, ensures transmission speed and the accuracy of gigabit Ethernet.
Description
Technical field
The utility model relates to data communication interface technical field, particularly a kind of gigabit ethernet interface device.
Background technology
In recent years, along with the developing rapidly of disposal ability of processor, the data processing of unit interval and handling capacity are more and more stronger, and processor is applied to high-speed data process occasion more and more, and this just requires that coffret has very high speed.Gigabit Ethernet is equipped with all to some extent on the industrial computer of current main flow and the data acquisition equipment of advanced person, and it has easy to connect, long transmission distance, and versatility is good, the advantages such as reliability is high, relative inexpensiveness.By means of above-mentioned advantage, gigabit Ethernet becomes embedded data treatment facility and one of extraneous significant data interactive interface.
Current partial data transmission bandwidth reaches more than 100,000,000, for these class methods, requires that the chip generating data provides the function of gigabit Ethernet.But there is following drawback in these class methods:
1, under single-chip or single system environment, the chip cost taking into account high-speed data process and gigabit Ethernet is expensive;
2, under multi-chip or multisystem environment, each systems-on-a-chip needs the support of gigabit Ethernet, and multiple port is not easy to data receiver on the one hand, substantially increases system cost on the other hand;
3, existing some equipment not supporting gigabit Ethernet are not suitable for.
Utility model content
Goal of the invention of the present utility model is: for above-mentioned Problems existing, provides a kind of gigabit ethernet interface device, can be applicable to the design of gigabit ethernet interface.
The technical solution adopted in the utility model is to provide a kind of gigabit ethernet interface device, comprise fpga chip, gigabit Ethernet physical chip, transformer and network interface, described fpga chip, described gigabit Ethernet physical chip and described transformer are electrically connected successively, described transformer is connected with outside network interface connector by described network interface, wherein, described gigabit Ethernet physical chip is connected with described transformer with a pair negative differential signal line by a pair positive differential holding wire, described transformer is connected with described network interface with a pair negative differential signal line by a pair positive differential holding wire.
Preferably, described fpga chip is integrated with MAC core.
Preferably, described gigabit Ethernet physical chip is single physical chip.
In sum, owing to have employed technique scheme, the beneficial effects of the utility model are: gigabit Ethernet physical chip is combined with fpga chip, only need realize MAC layer and above function on fpga chip, thus the design of gigabit ethernet interface can be applicable to, ensure transmission speed and the accuracy of gigabit Ethernet, and the design space of printed circuit board (PCB) can be saved, improve chip utilance, be conducive to the integrated of system, save system cost.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the gigabit ethernet interface device of the utility model embodiment.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in detail.
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
As shown in Figure 1, be the structured flowchart of gigabit ethernet interface device of the utility model embodiment.Gigabit ethernet interface device comprises FPGA (Field-Programmable Gate Array, field programmable gate array) chip, gigabit Ethernet physical chip, transformer and network interface, fpga chip, gigabit Ethernet physical chip and transformer are electrically connected successively, transformer is connected with outside network interface connector by network interface, wherein, gigabit Ethernet physical chip is connected with transformer with a pair negative differential signal line by a pair positive differential holding wire, transformer is connected with network interface with a pair negative differential signal line by a pair positive differential holding wire.
In the present embodiment, gigabit Ethernet physical chip is single physical chip.Model such as can be selected to be the physical chip of Marvell 88E1111.Transformer can select model to be the chip of HX5004NL.Due under normal circumstances, MAC (Media Access Control, media interviews control) layer and above function realize on fpga chip.Therefore, alternatively, fpga chip is integrated with MAC core, such as, can select 7 family chips of Xilinx company.
Gigabit ethernet interface device of the present utility model is based on the system architecture of FPGA, in conjunction with gigabit Ethernet physical chip, MAC layer and above function is realized by fpga chip, thus the design of gigabit ethernet interface can be applicable to, transmission speed and the accuracy of gigabit Ethernet can be ensured, improve chip utilance, when carrying out printed circuit board wiring, the design space of printed circuit board (PCB) can be saved, be convenient to process and the transmission of high-speed data, be conducive to the integrated of system, save system cost, improve the reliability of system.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all do within spirit of the present utility model and principle any amendment, equivalent to replace and improvement etc., all should be included within protection range of the present utility model.
Claims (3)
1. a gigabit ethernet interface device, it is characterized in that, comprise fpga chip, gigabit Ethernet physical chip, transformer and network interface, described fpga chip, described gigabit Ethernet physical chip and described transformer are electrically connected successively, described transformer is connected with outside network interface connector by described network interface, wherein, described gigabit Ethernet physical chip is connected with described transformer with a pair negative differential signal line by a pair positive differential holding wire, described transformer is connected with described network interface with a pair negative differential signal line by a pair positive differential holding wire.
2. gigabit ethernet interface device according to claim 1, is characterized in that, described fpga chip is integrated with MAC core.
3. gigabit ethernet interface device according to claim 1, is characterized in that, described gigabit Ethernet physical chip is single physical chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420518002.5U CN204069014U (en) | 2014-09-10 | 2014-09-10 | Gigabit Ethernet interface device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420518002.5U CN204069014U (en) | 2014-09-10 | 2014-09-10 | Gigabit Ethernet interface device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204069014U true CN204069014U (en) | 2014-12-31 |
Family
ID=52210453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420518002.5U Expired - Lifetime CN204069014U (en) | 2014-09-10 | 2014-09-10 | Gigabit Ethernet interface device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204069014U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108535629A (en) * | 2018-03-30 | 2018-09-14 | 西安微电子技术研究所 | A kind of ethernet circuit test system and method |
-
2014
- 2014-09-10 CN CN201420518002.5U patent/CN204069014U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108535629A (en) * | 2018-03-30 | 2018-09-14 | 西安微电子技术研究所 | A kind of ethernet circuit test system and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20141231 |