CN202748782U - Double-channel plate card - Google Patents
Double-channel plate card Download PDFInfo
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- CN202748782U CN202748782U CN 201220291027 CN201220291027U CN202748782U CN 202748782 U CN202748782 U CN 202748782U CN 201220291027 CN201220291027 CN 201220291027 CN 201220291027 U CN201220291027 U CN 201220291027U CN 202748782 U CN202748782 U CN 202748782U
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- transceiver
- memory
- integrated circuit
- circuit board
- processor
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- 230000005540 biological transmission Effects 0.000 abstract description 9
- 238000004891 communication Methods 0.000 abstract description 3
- 230000009977 dual effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000013501 data transformation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
The utility model relates to the field of data transmission control, in particular to a double-channel plate card. The plate card comprises a first transceiver, a second transceiver, a processor, a first memory, a second memory, an external connector, a PCI (programmable communication interface) and a PCI bridge chip. The first transceiver, the second transceiver, the first memory and the second memory are all connected with the processor. The external connector is connected with the first transceiver and the second transceiver, and the PCI is connected with the processor through the PCI bridge chip. An FPGA (field programmable gate array) is preferably adopted as the processor. By using the double-channel plate card, a double-channel working way is provided; each channel preferably accords with the protocol of a 1553b bus interface, and each channel has the independent transceiver and the independent memory; and the mutual working is not influenced. As the two channels can receive and send data at the same time, a data transmission speed can be effectively improved.
Description
Technical field
The utility model relates to the Data Transmission Controlling field, is specifically related to a kind of binary channels integrated circuit board, relates more specifically to a kind of 1553b bus interface transceiver.
Background technology
The 1553b bus claims again MIL STD1553B bus, is that US military aims at a kind of information transmission bus standard that equipment is formulated on the aircraft, the agreement of namely equipment room transmission.MIL STD1553b data bus has two-way output characteristics, and real-time and reliability are high, is widely used on the transporter and a considerable amount of airline carriers of passengers and military aircraft in the present age, and aerospace system is also used this bus widely.
The 1553b bus system mainly is comprised of 3 parts: bus controller BC, remote terminal RT and optional bus monitor MT.
At present known 1553b bus great majority are based on the speed of 1Mb/s, but along with the increase of transmitted data amount, and also in continuous increase, every integrated circuit board provides the single channel data-transformation facility can not satisfy the big data quantity transmission requirement to the requirement of multi transmission channel quantity.
The utility model content
Along with the increase of transmitted data amount, the requirement of channel transmission is being improved constantly.The utility model purpose is to provide a kind of binary channels integrated circuit board, and this integrated circuit board is binary channels 1553b integrated circuit board, satisfies international 1553b standard in agreement.
Particularly, the utility model can be realized by following proposal.
A kind of binary channels integrated circuit board, wherein, described integrated circuit board comprises first transceiver and second transceiver, processor and first memory and second memory.
Preferably, described first transceiver be connected second transceiver and described first memory be connected second memory and all be connected with described processor.
Preferably, described integrated circuit board also comprises aerial lug, pci interface, pci bridge chip.
Preferably, described aerial lug and described first transceiver be connected second transceiver and be connected, described pci interface is connected with described processor by described pci bridge chip.
Preferably, described processor adopting FPGA.
Preferably, described first transceiver and described second transceiver are independent of one another, and described first memory and described second memory are independent of one another.
Preferably, described first transceiver and described second transceiver configured in parallel on described integrated circuit board.
Preferably, described first memory and described second memory on described integrated circuit board with described processor configured in parallel.
Preferably, described first transceiver is connected with described first memory by described processor, and described second transceiver is connected with described second memory by described processor.
Preferably, described integrated circuit board meets the 1553b standard.
The utility model provides a kind of binary channels working method, and each passage meets the agreement of 1553b bus interface, and each passage has independently transceiver, data storage device independently, does not affect each other and works.Integrated circuit board can work in single, also can work in dual channel mode.
Because two passages are transceiving data simultaneously, can the Effective Raise data rate.
Description of drawings
Fig. 1 is planar structure synoptic diagram of the present utility model.
Embodiment
Below with reference to Fig. 1 principle of the present utility model and illustrative embodiments are described.
The below take binary channels 1553 integrated circuit boards as example illustrates binary channels integrated circuit board of the present utility model, yet the utility model is not limited to this.
As shown in Figure 1, binary channels 1553 integrated circuit boards comprise the first transceiver channel 2 and the second transceiver channel 3 (being also referred to as first transceiver and second transceiver), aerial lug 1, pci interface 5, pci bridge chip 6, processor 4 and first passage memory block 7 and second channel memory block 8 (being also referred to as first memory and second memory).
Described first passage memory block 7 and second channel memory block 8 parallel placement on integrated circuit board.
The first transceiver channel 2 and the second transceiver channel 3 on integrated circuit board with processor 4 parallel placements.
Processor 4 adopts FPGA, utilizes the concurrency of FPGA computing to realize the binary channels data transmit-receive.
These binary channels 1553 integrated circuit boards are based on the transmission channel quantity that improves the 1553b bus and develop.Its groundwork principle is to utilize 1553 transceivers that data-signal is received, and then the ability of utilizing the FPGA parallel data processing stores data binary channels 1553b data decode into SDRAM among.
The following describes the working method of integrated circuit board of the present utility model.
During receive data, data communication device is crossed connector 1 signal of each passage is passed to respectively receiving cable 2,3, after receiving cable is finished data-switching, data are passed to processor 4, processor 4 can store data into the memory block 7 or 8 of respective channel, reads away by bridge chip 6 and pci interface 5 for host computer.When sending data, the data communication device that host computer will send is crossed pci interface 5, bridge chip 6 and processor 4 and is write memory block corresponding to each passage 7 or 8, processor 4 writes sendaisle according to the data that sendaisle 2,3 idle condition will send, and connector 1 output is arranged at last.
Simple in structure, the practical function of the utility model is realized binary channels 1553b function at the veneer card, and each passage works alone.The integrated circuit board layout is carefully and neatly done, compact conformation, and each passage takies independently space.Integrated circuit board can work in single, also can work in dual channel mode, has improved range of application and the data-handling capacity of integrated circuit board.
The above still, should be appreciated that above-mentioned explanation only is exemplary with reference to the accompanying drawings of preferred implementation of the present utility model.Those skilled in the art can under the prerequisite that does not break away from spirit and scope of the present utility model, make various modifications and variations to the utility model.Protection domain of the present utility model is limited by the accompanying claims.
Claims (10)
1. a binary channels integrated circuit board is characterized in that, described integrated circuit board comprises first transceiver and second transceiver, processor and first memory and second memory.
2. binary channels integrated circuit board according to claim 1 is characterized in that, described first transceiver be connected second transceiver and described first memory be connected second memory and all be connected with described processor.
3. binary channels integrated circuit board according to claim 2 is characterized in that, described integrated circuit board also comprises aerial lug, pci interface, pci bridge chip.
4. binary channels integrated circuit board according to claim 3 is characterized in that, described aerial lug and described first transceiver be connected second transceiver and be connected, described pci interface is connected with described processor by described pci bridge chip.
5. the described binary channels integrated circuit board of each according to claim 1-4 is characterized in that described processor adopting FPGA.
6. the described binary channels integrated circuit board of each according to claim 1-4 is characterized in that described first transceiver and described second transceiver are independent of one another, and described first memory and described second memory are independent of one another.
7. binary channels integrated circuit board according to claim 6 is characterized in that, described first transceiver and described second transceiver configured in parallel on described integrated circuit board.
8. binary channels integrated circuit board according to claim 6 is characterized in that, described first memory and described second memory on described integrated circuit board with described processor configured in parallel.
9. the described binary channels integrated circuit board of each according to claim 1-4 is characterized in that, described first transceiver is connected with described first memory by described processor, and described second transceiver is connected with described second memory by described processor.
10. the described binary channels integrated circuit board of each according to claim 1-4 is characterized in that described integrated circuit board meets the 1553b standard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220291027 CN202748782U (en) | 2012-06-20 | 2012-06-20 | Double-channel plate card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220291027 CN202748782U (en) | 2012-06-20 | 2012-06-20 | Double-channel plate card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202748782U true CN202748782U (en) | 2013-02-20 |
Family
ID=47708146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220291027 Expired - Lifetime CN202748782U (en) | 2012-06-20 | 2012-06-20 | Double-channel plate card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202748782U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ES2492592R1 (en) * | 2013-03-07 | 2014-09-30 | Akrocard 2000, S.L. | DOUBLE CHIP CARD |
-
2012
- 2012-06-20 CN CN 201220291027 patent/CN202748782U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ES2492592R1 (en) * | 2013-03-07 | 2014-09-30 | Akrocard 2000, S.L. | DOUBLE CHIP CARD |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130220 |
|
| DD01 | Delivery of document by public notice | ||
| DD01 | Delivery of document by public notice |
Addressee: Mao Panpan Document name: Notice of expiration and termination of patent right |