CN113055313A - Method and device for network port expansion, electronic equipment and storage medium - Google Patents
Method and device for network port expansion, electronic equipment and storage medium Download PDFInfo
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- CN113055313A CN113055313A CN202110284883.3A CN202110284883A CN113055313A CN 113055313 A CN113055313 A CN 113055313A CN 202110284883 A CN202110284883 A CN 202110284883A CN 113055313 A CN113055313 A CN 113055313A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/45—Arrangements for providing or supporting expansion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2101/00—Indexing scheme associated with group H04L61/00
- H04L2101/60—Types of network addresses
- H04L2101/618—Details of network addresses
- H04L2101/622—Layer-2 addresses, e.g. medium access control [MAC] addresses
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Abstract
The embodiment of the invention discloses a method and a device for network port expansion, electronic equipment and a storage medium, wherein the method comprises the following steps: acquiring configuration information of the FPGA and a plurality of paths of network ports; acquiring connection information between a gigabit network card controller of a CPU and the FPGA according to the configuration information of the FPGA and a multi-path network port; acquiring information that the FPGA collects the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the connection information between the gigabit network card controller of the CPU and the FPGA; and summarizing the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the FPGA to control the CPU and the specified network ports to receive or send data. The method and the device realize a one-to-many network mode, so that one path of MAC controller uses a plurality of paths of network ports, messages transmitted from the external network ports are analyzed in the FPGA, and software only needs to establish a plurality of paths of virtual network cards.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for network port expansion based on an FPGA (field programmable gate array), electronic equipment and a storage medium.
Background
Most of the prior art is a network card controller corresponding to a RJ45(Registered Jack 45) network Port, which is in a one-to-one relationship in use, and usually, a Reduced Gigabit Media Independent Interface (RGMII) or a Reduced Media Independent Interface (RMII) is used to complete communication between a Media Access Control Address (MAC) and a Physical Layer (PHY) Port.
At present, the one-to-one method has major defects and shortcomings: firstly, the network port is strong in specificity, and under the condition of a one-to-one mode, extremely high requirements are put forward on the number of the MAC controllers of the CPUs, namely one MAC controller corresponds to one network, and most of the CPU resources on the network card controller are relatively short, so that a single network has a special use mode and scene; secondly, the function is single, under the condition of one-to-one mode, basically one MAC controller corresponds to one path of standard PHY device, the function is single, and only the data communication function is supported; thirdly, the adaptive software has complex functions, the software layer needs to perform packet packing and unpacking operations on the messages, the functions are complex, and data problems are easy to occur.
Accordingly, there is a need in the art for improvements.
Disclosure of Invention
The embodiment of the invention aims to solve the technical problem that: a method, an apparatus, an electronic device and a storage medium for network port expansion are provided to solve the problems in the prior art.
In an embodiment of the present application, the method for network port expansion includes:
acquiring configuration information of the FPGA and a plurality of paths of network ports;
acquiring connection information between a gigabit network card controller of a CPU and the FPGA according to the configuration information of the FPGA and a multi-path network port;
acquiring information that the FPGA collects the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the connection information between the gigabit network card controller of the CPU and the FPGA;
and summarizing the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the FPGA to control the CPU and the specified network ports to receive or send data.
In another embodiment, the obtaining configuration information of the FPGA and the multi-path network interface includes:
acquiring connection information of the FPGA and a plurality of paths of network ports;
acquiring initialization information of a plurality of network ports after the FPGA is electrified according to the connection information of the FPGA and the plurality of network ports;
acquiring the information that the CPU configures the MAC address to the FPGA through the SPI according to the initialization information of the multi-path network port;
and configuring the MAC address to FPGA information through an SPI interface according to the CPU, and acquiring the information of configuring the MAC address to a multi-path network port.
In another embodiment, the obtaining, according to the initialization information of the multi-path network port, that the CPU configures the MAC address to the FPGA information through the SPI interface includes:
the CPU sends MAC address information of a plurality of network ports to the FPGA through the SPI bus;
the CPU obtains the state information of the multi-path network port through the SPI bus;
the CPU is configured in a host mode of the SPI bus;
the FPGA is configured in a slave mode of the SPI bus.
In another embodiment, the obtaining the connection information between the gigabit network card controller of the CPU and the FPGA according to the configuration information between the FPGA and the multi-path network port includes:
acquiring MAC configuration information of the multi-path network port according to the configuration parameter information of the FPGA and the multi-path network port;
acquiring physical connection information between a gigabit network card controller of the CPU and the FPGA according to the MAC configuration information of the multi-path network port;
and acquiring the connection information of the road network port and the gigabit network card controller of the CPU according to the physical connection information of the gigabit network card controller of the CPU and the FPGA.
In another embodiment, the acquiring, by the FPGA, information that the FPGA aggregates the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the connection information between the gigabit network card controller of the CPU and the FPGA includes:
the FPGA acquires MAC configuration information of the multi-path network port;
and the FPGA collects the MAC configuration information of the multi-path network port to a gigabit network card controller of the CPU.
In another embodiment, the collecting the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the FPGA for information, and controlling the CPU to perform data reception or transmission with a specified network port includes:
the FPGA acquires data information sent by any one or more network ports in the multi-path network ports;
the FPGA sends the received data information to a gigabit network card controller of the CPU;
the FPGA acquires data information analyzed by the gigabit network card controller of the CPU, wherein the data information analyzed by the gigabit network card controller of the CPU comprises MAC address information of a network port;
and the FPGA acquires the MAC address information of the network port analyzed by the gigabit network card controller of the CPU.
In another embodiment, the collecting the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the FPGA for information, and controlling the CPU to perform data reception or transmission with a specified network port includes:
the FPGA acquires data information sent by a gigabit network card controller of the CPU;
the FPGA analyzes data information sent by a gigabit network card controller of the CPU, and obtains an MAC address of a target network port sent by the data information;
and the FPGA sends the data information to the corresponding target network port according to the analyzed MAC address of the target network port.
Based on another aspect of the embodiments of the present invention, a device for network port expansion is disclosed, which includes:
the acquisition module is used for acquiring the connection information between the FPGA and the multi-path network port and acquiring the connection information between the gigabit network card controller of the CPU and the FPGA according to the configuration information between the FPGA and the multi-path network port;
the address summarizing module is used for acquiring the information that the FPGA summarizes the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the connection information between the gigabit network card controller of the CPU and the FPGA;
and the data receiving and transmitting module is used for summarizing the MAC addresses of the multi-path network ports to the gigabit network card controller of the CPU according to the FPGA to control the CPU and the specified network ports to receive or transmit data.
In accordance with yet another aspect of an embodiment of the present invention, an electronic device is disclosed, the electronic device comprising one or more processors and memory, the memory for storing one or more programs; when the one or more programs are executed by the processor, the processor is enabled to implement the method for network port expansion provided by the embodiments of the invention.
Based on still another aspect of the embodiments of the present invention, a computer-readable storage medium storing a computer program is disclosed, where the computer program is executed to implement the method for network port expansion provided by the embodiments of the present invention.
Compared with the prior art, the invention has the following advantages:
according to the method, the device, the electronic equipment and the storage medium for network port expansion, the configuration information of the FPGA and the multi-path network ports and the connection information of the gigabit network card controller of the CPU and the FPGA are obtained; collecting the MAC addresses of the multiple network ports to a gigabit network card controller of the CPU for information; and controlling the CPU to receive or send data with the specified network port. The method has the advantages that a one-to-many network mode is realized, hardware obstacles are broken through, one path of MAC controller can also use multiple paths of network ports, the overall flexibility is high, messages transmitted from external network ports can be analyzed in an FPGA (field programmable gate array), corresponding control functions can be added, software only needs to establish multiple paths of virtual network cards, unpacking analysis on the messages in a driving layer is not needed, and the flow is single.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
The invention will be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
FIG. 1 is a diagram illustrating an exemplary implementation of a method for portal expansion;
FIG. 2 is a flow chart of a method for portal expansion according to an embodiment of the present invention;
FIG. 3 is a block diagram of an apparatus for port expansion according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an internal structure of an electronic device in one embodiment.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
The method for network port expansion provided by the application can be applied to the application environment shown in fig. 1. The method for network port expansion is applied to a network port expansion device. The device for internet access extension can be configured in the terminal 102 or the server 104, or partially configured in the terminal 102 and partially configured in the server 104, and the method for internet access extension is completed by the interaction of the terminal 102 and the server 104.
Wherein the terminal 102 and the server 104 can communicate through a network.
The terminal 102 may be, but not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices, the terminal 102 needs to have a function of acquiring configuration information of the FPGA and the multi-path network port and connection information of the gigabit network card controller of the CPU and the FPGA, and summarizing the MAC addresses of the multi-path network port to information on the gigabit network card controller of the CPU, and the server 104 may be implemented by an independent server or a server cluster composed of a plurality of servers.
In one embodiment, as shown in fig. 2, a method for network port expansion is provided, and this embodiment is mainly illustrated by applying the method to the terminal 102 in fig. 1.
Specifically, the FPGA manages multiple PHYs simultaneously, each PHY is connected to one port, the FPGA is connected to the PHY through RGMII (Reduced bit Media Independent Interface) or RMII (Reduced Media Independent Interface), and configuration information of the FPGA and the multiple ports includes MAC address information, electrical connection information, and the like of each port.
Specifically, in an embodiment of the present invention, the acquiring configuration information of the FPGA and the multi-path network interface includes:
and acquiring the connection information of the FPGA and the multi-path network ports.
Specifically, it is first necessary to complete the physical connection between the FPGA and the multi-path network interface, that is, to implement the electrical property connection between the FPGA and the multi-path network interface in a wired manner or a wireless manner, for example, to implement the electrical connection between the FPGA and the multi-path network interface, and the two satisfy the electrical conditions for signal exchange.
And acquiring initialization information of the multi-path network port after the FPGA is electrified according to the connection information of the FPGA and the multi-path network port.
Specifically, after the FPGA is connected to the multiple network ports, when the FPGA is powered on, the multiple network ports need to be initialized, and the FPGA acquires initialization information of the multiple network ports.
And acquiring the information that the CPU configures the MAC address to the FPGA through the SPI according to the initialization information of the multi-path network port.
Specifically, after the initialization information of the multi-path network port is acquired, the CPU sends the configured MAC address information to the FPGA, and the FPGA configures the MAC address information of the multi-path network port according to the MAC information configured by the CPU.
And configuring the MAC address to FPGA information through an SPI interface according to the CPU, and acquiring the information of configuring the MAC address to a multi-path network port.
Specifically, after the FPGA acquires configuration information of multiple network ports, the FPGA needs to be connected to a gigabit network card controller of the CPU, which is a precondition for completing connection between the FPGA and the CPU, the gigabit network card controller is a part of the CPU and is responsible for sending and receiving network data, and the gigabit network card controller controls data sending and receiving of one or more network ports according to MAC address information of the multiple network ports.
Specifically, in an embodiment of the present application, the obtaining, according to the initialization information of the multiple network ports, that the CPU configures the MAC address to the FPGA information through the SPI interface includes:
and the CPU sends MAC address information of a plurality of network ports to the FPGA through the SPI bus.
Specifically, when the CPU sets MAC address information of a plurality of network ports, the CPU distributes MAC addresses through an SPI (Serial Peripheral Interface) bus, where the MAC addresses distributed by the CPU are first stored in the FPGA and forwarded to the corresponding network ports by the FPGA.
And the CPU acquires the state information of the multi-path network port through the SPI bus.
Specifically, since the FPGA has already acquired the state information of the multiple network ports, the CPU can acquire the state information of the multiple network ports from the FPGA through the SPI bus, and the FPGA can also actively upload the state information of the multiple network ports.
The CPU is configured in a host mode of the SPI bus.
Specifically, the host mode is an active party for acquiring information, and is responsible for sending a clock signal and terminating sending at initialization.
The FPGA is configured in a slave mode of the SPI bus.
The SPI is a high-speed, fully bi-directional, synchronous, four-wire or three-wire serial peripheral interface, adopts a master-slave mode structure, supports multi-slave mode application, generally supports only a single master, and transmits data in bits under a shift clock pulse of the master, either with the higher bit being the front (MSB first) or the lower bit being the back, or with the lower bit being the front and the higher bit being the back, in that order.
Specifically, in an embodiment of the present application, the obtaining connection information between the gigabit network card controller of the CPU and the FPGA according to the configuration information between the FPGA and the multi-path network interface includes:
acquiring MAC configuration information of the multi-path network port according to the configuration parameter information of the FPGA and the multi-path network port;
acquiring physical connection information between a gigabit network card controller of the CPU and the FPGA according to the MAC configuration information of the multi-path network port;
and acquiring the connection information of the road network port and the gigabit network card controller of the CPU according to the physical connection information of the gigabit network card controller of the CPU and the FPGA.
And 203, acquiring the information that the FPGA collects the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the connection information between the gigabit network card controller of the CPU and the FPGA.
Specifically, after the FPGA is connected to the gigabit network card controller of the CPU, the FPGA uploads MAC address information of the multiple network ports to the gigabit network card controller of the CPU, the gigabit network card controller establishes an information transmission channel of the multiple network ports, and since the MAC address information of the multiple network ports is set by the CPU, if the FPGA is initialized, the MAC address information of the multiple network ports needs to be acquired first, and the FPGA uploads the MAC address information of the multiple network ports to the gigabit network card controller of the CPU, the gigabit network card controller of the CPU recognizes and establishes the information transmission channel of the multiple network ports, and if the multiple network ports are not the MAC addresses that can be recognized by the gigabit network card controller of the CPU, the CPU needs to reset the MAC addresses of the multiple network ports, and then establishes the gigabit network card controller of the CPU and the information transmission channel of the multiple network ports.
Specifically, in an embodiment of the present application, the acquiring, by the FPGA, information for summarizing the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the connection information between the gigabit network card controller of the CPU and the FPGA includes:
the FPGA acquires MAC configuration information of the multi-path network port;
and the FPGA collects the MAC configuration information of the multi-path network port to a gigabit network card controller of the CPU.
And step 204, summarizing the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the FPGA, and controlling the CPU to receive or send data with the specified network port.
Specifically, when the CPU receives data of a certain network port or transmits data to a certain network port through the gigabit network card controller, the gigabit network card controller and a designated network port in the information transmission channel of the multiple network ports are used to implement the data transmission.
Specifically, in an embodiment of the present application, the collecting, according to the FPGA, the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU for information, and controlling the CPU and the specified network port to perform data reception includes:
the FPGA acquires data information sent by any one or more network ports in the multi-path network ports;
the FPGA sends the received data information to a gigabit network card controller of the CPU;
the FPGA acquires data information analyzed by the gigabit network card controller of the CPU, wherein the data information analyzed by the gigabit network card controller of the CPU comprises MAC address information of a network port;
and the FPGA acquires the MAC address information of the network port analyzed by the gigabit network card controller of the CPU.
Specifically, in an embodiment of the present application, the collecting, according to the FPGA, the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU for information, and controlling the CPU and the specified network port to perform data transmission includes:
the FPGA acquires data information sent by a gigabit network card controller of the CPU;
the FPGA analyzes data information sent by a gigabit network card controller of the CPU, and obtains an MAC address of a target network port sent by the data information;
and the FPGA sends the data information to the corresponding target network port according to the analyzed MAC address of the target network port.
The method comprises the steps of obtaining configuration information of an FPGA and a multi-path network port and connection information of a gigabit network card controller of a CPU and the FPGA; collecting the MAC addresses of the multiple network ports to a gigabit network card controller of the CPU for information; and controlling the CPU to receive or send data with the specified network port. The method has the advantages that a one-to-many network mode is realized, hardware obstacles are broken through, one path of MAC controller can also use multiple paths of network ports, the overall flexibility is high, messages transmitted from external network ports can be analyzed in an FPGA (field programmable gate array), corresponding control functions can be added, software only needs to establish multiple paths of virtual network cards, unpacking analysis on the messages in a driving layer is not needed, and the flow is single.
It should be understood that, although the steps in the flowchart of fig. 2 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 2 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 3, there is provided an apparatus for portal expansion, including: the device comprises an acquisition module, an address summarizing module and a data transceiving module.
The acquisition module is used for acquiring the connection information between the FPGA and the multi-path network port and acquiring the connection information between the gigabit network card controller of the CPU and the FPGA according to the configuration information between the FPGA and the multi-path network port;
an address collecting module, configured to obtain, according to connection information between the gigabit network card controller of the CPU and the FPGA, information that the FPGA collects MAC addresses of the multiple network ports to the gigabit network card controller of the CPU
And the data receiving and transmitting module is used for summarizing the MAC addresses of the multi-path network ports to the gigabit network card controller of the CPU according to the FPGA to control the CPU and the specified network ports to receive or transmit data.
Specifically, in another embodiment of the present application, the obtaining module is configured to obtain connection information between the FPGA and the multiple network ports; acquiring initialization information of a plurality of network ports after the FPGA is electrified according to the connection information of the FPGA and the plurality of network ports; acquiring the information that the CPU configures the MAC address to the FPGA through the SPI according to the initialization information of the multi-path network port; and configuring the MAC address to FPGA information through an SPI interface according to the CPU, and acquiring the information of configuring the MAC address to a multi-path network port.
Specifically, in another embodiment of the present application, the obtaining module is configured to obtain MAC configuration information of a multi-path network interface according to configuration parameter information of the FPGA and the multi-path network interface; acquiring physical connection information between a gigabit network card controller of the CPU and the FPGA according to the MAC configuration information of the multi-path network port; and acquiring the connection information of the road network port and the gigabit network card controller of the CPU according to the physical connection information of the gigabit network card controller of the CPU and the FPGA.
Specifically, in another embodiment of the present application, the address aggregation module is configured to enable the FPGA to obtain MAC configuration information of the multiple network ports; and the FPGA collects the MAC configuration information of the multi-path network port to a gigabit network card controller of the CPU.
Specifically, in another embodiment of the present application, the data transceiver module is configured to acquire, by the FPGA, data information sent by any one or more network ports of the multiple network ports; the FPGA sends the received data information to a gigabit network card controller of the CPU; the FPGA acquires data information analyzed by the gigabit network card controller of the CPU, wherein the data information analyzed by the gigabit network card controller of the CPU comprises MAC address information of a network port; and the FPGA acquires the MAC address information of the network port analyzed by the gigabit network card controller of the CPU.
Specifically, in another embodiment of the present application, the data transceiver module is configured to enable the FPGA to acquire data information sent by a gigabit network card controller of the CPU; the FPGA analyzes data information sent by a gigabit network card controller of the CPU, and obtains an MAC address of a target network port sent by the data information; and the FPGA sends the data information to the corresponding target network port according to the analyzed MAC address of the target network port.
The method comprises the steps that configuration information of an FPGA and a multi-path network port and connection information of a gigabit network card controller of a CPU and the FPGA are obtained through an obtaining module; summarizing the MAC addresses of the multi-path network ports to the gigabit network card controller of the CPU through an address summarizing module; and the CPU is controlled by the data transceiver module to receive or transmit data with the specified network port. The method has the advantages that a one-to-many network mode is realized, hardware obstacles are broken through, one path of MAC controller can also use multiple paths of network ports, the overall flexibility is high, messages transmitted from external network ports can be analyzed in an FPGA (field programmable gate array), corresponding control functions can be added, software only needs to establish multiple paths of virtual network cards, unpacking analysis on the messages in a driving layer is not needed, and the flow is single.
For specific definition of the device for internet access extension, reference may be made to the above definition of the method for internet access extension, which is not described herein again. The modules in the above-mentioned network port expansion device can be wholly or partially implemented by software, hardware and their combination. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, an electronic device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 4. The electronic device comprises a processor, a memory, a communication interface, a display screen and an input device which are connected through a system bus. Wherein the processor of the electronic device is configured to provide computing and control capabilities. The memory of the electronic equipment comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the electronic device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, Near Field Communication (NFC) or other technologies. The computer program is executed by a processor to implement a method of portal expansion. The display screen of the electronic equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the electronic equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the configuration shown in fig. 4 is a block diagram of only a portion of the configuration associated with the present application, and does not constitute a limitation on the electronic device to which the present application is applied, and a particular electronic device may include more or less components than those shown in the drawings, or combine certain components, or have a different arrangement of components.
In one embodiment, the apparatus for portal expansion provided in the present application may be implemented in the form of a computer program, and the computer program may be run on an electronic device as shown in fig. 4. The memory of the electronic device may store various program modules constituting the apparatus based on internet access extension, such as the obtaining module, the address summarizing module, and the data transceiving module shown in fig. 3. The computer program constituted by the program modules causes the processor to execute the steps of the method for network port expansion of the embodiments of the present application described in the present specification.
For example, the electronic device shown in fig. 4 may obtain, through the obtaining module of the device for network port expansion shown in fig. 5, configuration information of the FPGA and the multiple network ports and connection information of the gigabit network card controller of the CPU and the FPGA; summarizing the MAC addresses of the multi-path network ports to the gigabit network card controller of the CPU through an address summarizing module; and the CPU is controlled by the data transceiver module to receive or transmit data with the specified network port.
In one embodiment, the processor, when executing the computer program, performs the steps of: acquiring connection information of the FPGA and a plurality of paths of network ports; acquiring initialization information of a plurality of network ports after the FPGA is electrified according to the connection information of the FPGA and the plurality of network ports; acquiring the information that the CPU configures the MAC address to the FPGA through the SPI according to the initialization information of the multi-path network port; and configuring the MAC address to FPGA information through an SPI interface according to the CPU, and acquiring the information of configuring the MAC address to a multi-path network port.
In one embodiment, the processor, when executing the computer program, further performs the steps of: acquiring MAC configuration information of the multi-path network port according to the configuration parameter information of the FPGA and the multi-path network port; acquiring physical connection information between a gigabit network card controller of the CPU and the FPGA according to the MAC configuration information of the multi-path network port; and acquiring the connection information of the road network port and the gigabit network card controller of the CPU according to the physical connection information of the gigabit network card controller of the CPU and the FPGA.
In one embodiment, the processor, when executing the computer program, further performs the steps of: the FPGA acquires MAC configuration information of the multi-path network port; and the FPGA collects the MAC configuration information of the multi-path network port to a gigabit network card controller of the CPU.
In one embodiment, the processor, when executing the computer program, further performs the steps of: the FPGA acquires data information sent by any one or more network ports in the multi-path network ports; the FPGA sends the received data information to a gigabit network card controller of the CPU; the FPGA acquires data information analyzed by the gigabit network card controller of the CPU, wherein the data information analyzed by the gigabit network card controller of the CPU comprises MAC address information of a network port; and the FPGA acquires the MAC address information of the network port analyzed by the gigabit network card controller of the CPU.
In one embodiment, the processor, when executing the computer program, further performs the steps of: the FPGA acquires data information sent by a gigabit network card controller of the CPU; the FPGA analyzes data information sent by a gigabit network card controller of the CPU, and obtains an MAC address of a target network port sent by the data information; and the FPGA sends the data information to the corresponding target network port according to the analyzed MAC address of the target network port.
When a computer program is executed by a processor, configuration information of an FPGA and a multi-path network port and connection information of a gigabit network card controller of a CPU and the FPGA are obtained; collecting the MAC addresses of the multiple network ports to a gigabit network card controller of the CPU for information; and controlling the CPU to receive or send data with the specified network port. The method has the advantages that a one-to-many network mode is realized, hardware obstacles are broken through, one path of MAC controller can also use multiple paths of network ports, the overall flexibility is high, messages transmitted from external network ports can be analyzed in an FPGA (field programmable gate array), corresponding control functions can be added, software only needs to establish multiple paths of virtual network cards, unpacking analysis on the messages in a driving layer is not needed, and the flow is single.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM is available in many forms, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for portal expansion, comprising:
acquiring configuration information of the FPGA and a plurality of paths of network ports;
acquiring connection information between a gigabit network card controller of a CPU and the FPGA according to the configuration information of the FPGA and a multi-path network port;
acquiring information that the FPGA collects the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the connection information between the gigabit network card controller of the CPU and the FPGA;
and summarizing the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the FPGA to control the CPU and the specified network ports to receive or send data.
2. The method for network port expansion according to claim 1, wherein the acquiring configuration information of the FPGA and the multi-path network port comprises:
acquiring connection information of the FPGA and a plurality of paths of network ports;
acquiring initialization information of a plurality of network ports after the FPGA is electrified according to the connection information of the FPGA and the plurality of network ports;
acquiring the information that the CPU configures the MAC address to the FPGA through the SPI according to the initialization information of the multi-path network port;
and configuring the MAC address to FPGA information through an SPI interface according to the CPU, and acquiring the information of configuring the MAC address to a multi-path network port.
3. The method for network port expansion according to claim 2, wherein the obtaining, according to the initialization information of the multi-path network port, the information that the CPU configures the MAC address to the FPGA through the SPI interface comprises:
the CPU sends MAC address information of a plurality of network ports to the FPGA through the SPI bus;
the CPU obtains the state information of the multi-path network port through the SPI bus;
the CPU is configured in a host mode of the SPI bus;
the FPGA is configured in a slave mode of the SPI bus.
4. The method for network port expansion according to claim 1, wherein the obtaining the connection information between the gigabit network card controller of the CPU and the FPGA according to the configuration information between the FPGA and the multi-channel network port comprises:
acquiring MAC configuration information of the multi-path network port according to the configuration parameter information of the FPGA and the multi-path network port;
acquiring physical connection information between a gigabit network card controller of the CPU and the FPGA according to the MAC configuration information of the multi-path network port;
and acquiring the connection information of the road network port and the gigabit network card controller of the CPU according to the physical connection information of the gigabit network card controller of the CPU and the FPGA.
5. The method for network port expansion according to claim 1, wherein the acquiring, by the FPGA, information that the FPGA aggregates the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the connection information between the gigabit network card controller of the CPU and the FPGA comprises:
the FPGA acquires MAC configuration information of the multi-path network port;
and the FPGA collects the MAC configuration information of the multi-path network port to a gigabit network card controller of the CPU.
6. The method for network port expansion according to claim 1, wherein the aggregating the MAC addresses of the multiple network ports to a gigabit network card controller of the CPU according to the FPGA to control the CPU to perform data reception or transmission with a specified network port includes:
the FPGA acquires data information sent by any one or more network ports in the multi-path network ports;
the FPGA sends the received data information to a gigabit network card controller of the CPU;
the FPGA acquires data information analyzed by the gigabit network card controller of the CPU, wherein the data information analyzed by the gigabit network card controller of the CPU comprises MAC address information of a network port;
and the FPGA acquires the MAC address information of the network port analyzed by the gigabit network card controller of the CPU.
7. The method for network port expansion according to claim 1, wherein the aggregating the MAC addresses of the multiple network ports to a gigabit network card controller of the CPU according to the FPGA to control the CPU to perform data reception or transmission with a specified network port includes:
the FPGA acquires data information sent by a gigabit network card controller of the CPU;
the FPGA analyzes data information sent by a gigabit network card controller of the CPU, and obtains an MAC address of a target network port sent by the data information;
and the FPGA sends the data information to the corresponding target network port according to the analyzed MAC address of the target network port.
8. An apparatus for portal expansion, the apparatus comprising:
the acquisition module is used for acquiring the connection information between the FPGA and the multi-path network port and acquiring the connection information between the gigabit network card controller of the CPU and the FPGA according to the configuration information between the FPGA and the multi-path network port;
the address summarizing module is used for acquiring the information that the FPGA summarizes the MAC addresses of the multiple network ports to the gigabit network card controller of the CPU according to the connection information between the gigabit network card controller of the CPU and the FPGA;
and the data receiving and transmitting module is used for summarizing the MAC addresses of the multi-path network ports to the gigabit network card controller of the CPU according to the FPGA to control the CPU and the specified network ports to receive or transmit data.
9. An electronic device, comprising one or more processors and memory, the memory to store one or more programs;
the one or more programs, when executed by the processor, cause the processor to implement the method of any of claims 1-7.
10. A computer-readable storage medium storing a computer program, characterized in that the computer program, when executed, implements the method of any one of claims 1 to 7.
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