CN103823785A - Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD - Google Patents

Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD Download PDF

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CN103823785A
CN103823785A CN201410113491.0A CN201410113491A CN103823785A CN 103823785 A CN103823785 A CN 103823785A CN 201410113491 A CN201410113491 A CN 201410113491A CN 103823785 A CN103823785 A CN 103823785A
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transceiver
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CN103823785B (en
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王玮
陈刚
李鹏
丁振兴
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Beihang University
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Abstract

本发明公开了一种基于DSP和CPLD开发的多路ARINC429数据收发电路结构，包括DSP电路、多组ARINC429总线收发芯片电路、由CPLD编程实现的辅助控制电路，其中ARINC429总线收发芯片的数据端与DSP连接，控制端与CPLD连接，DSP电路向由CPLD芯片编程实现的寄存器电路发送控制指令来实现对多组ARINC429总线收发芯片的控制，并通过在DSP芯片中的软件编程实现ARINC429数据的接收解码和发送编码。本发明可以将多路ARINC429数据通过DSP芯片数据总线实时读取和发送，避免数据冲突、丢失和误码，实现对数据的高速处理。

The invention discloses a multi-channel ARINC429 data transceiver circuit structure developed based on DSP and CPLD, including a DSP circuit, multiple groups of ARINC429 bus transceiver chip circuits, and an auxiliary control circuit realized by CPLD programming, wherein the data terminal of the ARINC429 bus transceiver chip is connected to the DSP connection, the control terminal is connected with CPLD, and the DSP circuit sends control instructions to the register circuit programmed by the CPLD chip to realize the control of multiple groups of ARINC429 bus transceiver chips, and realize the reception and decoding of ARINC429 data through software programming in the DSP chip and send encoding. The invention can read and send multiple ARINC429 data in real time through the DSP chip data bus, avoiding data conflict, loss and bit error, and realizing high-speed data processing.

Description

A kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation
Technical field
The present invention relates to the technical field of ARINC429 data transmit-receive circuit, be specifically related to a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation.
Background technology
At present, the known ARINC429 data transmit-receive circuit based on DSP and FPGA is made up of DSP circuit, FPGA circuit and ARINC429 bus transceiving chip circuit, while carrying out multichannel data reception, the ways that adopt FPGA algorithm exampleization more, although this design has multichannel transmitting-receiving ability, multiplexer channel synchronization receives ARINC429 data and easily occurs data collision, loss and error code.And known multi-channel A RINC429 receiving circuit based on DSP and CPLD takies the too much external interrupt of DSP, make DSP very limited in circuit function, and in the time that receiving and dispatching, multichannel data synchronization easily there is communication conflict, make in DSP deal with data process, easily occur that the reception of multi-channel A RINC429 data is lost.
Summary of the invention
The present invention is intended to overcome deficiency of the prior art, a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation is provided, the data bus direct read/write that this data transmit-receive circuit structure can not only be applied dsp chip is organized the data terminal of ARINC429 bus transceiving chip more, utilize CPLD(CPLD) programming realize register circuit control sequential and logical relation, and multiple external interrupt signals of many groups ARINC429 bus transceiving chip are integrated, greatly save the use to DSP external interrupt resource, effectively avoid data collision, lose and error code.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation, comprise DSP circuit, many group ARINC429 bus transceiving chip circuit, also comprise the register circuit of being realized by CPLD chip programming;
Data bus XD0～the XD15 of described DSP circuit is connected with the data bus BD00～BD15 of described many group ARINC429 bus transceiving chip circuit by electrical level matching circuit, the steering order end D429_A0～D429_A7 of described DSP circuit, steering order completes excitation end D429_ARDY, data send state end D429_TX/R, data send Enable Pin D429_ENTX, comprehensive receive interruption port D429_RINT, the steering order end D429_A0～D429_A7 of receiving cable coded address end D429_RINTA0～D429_RINTA3 and the described register circuit of being realized by CPLD chip programming, steering order completes excitation end D429_ARDY, data send state end D429_TX/R, data send Enable Pin D429_ENTX, comprehensive receive interruption port D429_RINT, receiving cable coded address end D429_RINTA0～D429_RINTA3 is corresponding to be connected, described many group ARINC429 bus transceiving chip circuit comprise 4 groups, can receive 8 road ARINC429 data simultaneously, send 4 road ARINC429 data, the data sink 1 receive interruption port of the 1st group of transmission circuit wherein
Figure BDA0000481645550000021
data sink 2 receive interruption ports
Figure BDA0000481645550000022
receive high/low 16 of data and read selecting side SEL, data sink 1 Enable Pin
Figure BDA0000481645550000023
data sink 2 Enable Pins
Figure BDA0000481645550000024
send low 16 of data and write selecting side send high 16 of data and write selecting side
Figure BDA0000481645550000026
data send state end TX/R, data send Enable Pin ENTX, chip configuration Enable Pin
Figure BDA0000481645550000027
the data sink 1 receive interruption port C429A_RDY1 of the 1st group of transmission circuit by electrical level matching circuit and the described register circuit of being realized by CPLD chip programming, the data sink 2 receive interruption port C429A_RDY2 of the 1st group of transmission circuit, high/low 16 of the reception data of the 1st group of transmission circuit read selecting side C429A_SEL, the data sink 1 Enable Pin C429A_EN1 of the 1st group of transmission circuit, the data sink 2 Enable Pin C429A_EN2 of the 1st group of transmission circuit, low 16 of the transmission data of the 1st group of transmission circuit write selecting side C429A_PL1, high 16 of the transmission data of the 1st group of transmission circuit write selecting side C429A_PL2, the data of the 1st group of transmission circuit send state end C429A_TX/R, the data of the 1st group of transmission circuit send Enable Pin C429A_ENTX, the corresponding connection of chip configuration Enable Pin C429A_CWSTR of the 1st group of transmission circuit, the 2nd group of transmission circuit
Figure BDA0000481645550000028
sEL,
Figure BDA0000481645550000032
tX/R, ENTX,
Figure BDA0000481645550000033
end is by the data sink 1 receive interruption port C429B_RDY1 of the 2nd group of transmission circuit of electrical level matching circuit and the described register circuit of being realized by CPLD chip programming, the data sink 2 receive interruption port C429B_RDY2 of the 2nd group of transmission circuit, high/low 16 of the reception data of the 2nd group of transmission circuit read selection C429B_SEL, the data sink 1 Enable Pin C429B_EN1 of the 2nd group of transmission circuit, the data sink 2 Enable Pin C429B_EN2 of the 2nd group of transmission circuit, low 16 of the transmission data of the 2nd group of transmission circuit write selecting side C429B_PL1, high 16 of the transmission data of the 2nd group of transmission circuit write selecting side C429B_PL2, the data of the 2nd group of transmission circuit send state end C429B_TX/R, the data of the 2nd group of transmission circuit send Enable Pin C429B_ENTX, the corresponding connection of chip configuration Enable Pin C429B_CWSTR of the 2nd group of transmission circuit, the 3rd group of transmission circuit
Figure BDA0000481645550000034
sEL,
Figure BDA0000481645550000035
Figure BDA0000481645550000036
tX/R, ENTX,
Figure BDA0000481645550000037
end is by the data sink 1 receive interruption port C429C_RDY1 of the 3rd group of transmission circuit of electrical level matching circuit and the described register circuit of being realized by CPLD chip programming, the data sink 2 receive interruption port C429C_RDY2 of the 3rd group of transmission circuit, high/low 16 of the reception data of the 3rd group of transmission circuit read selecting side C429C_SEL, the data sink 1 Enable Pin C429C_EN1 of the 3rd group of transmission circuit, the data sink 2 Enable Pin C429C_EN2 of the 3rd group of transmission circuit, low 16 of the transmission data of the 3rd group of transmission circuit write selecting side C429C_PL1, high 16 of the transmission data of the 3rd group of transmission circuit write selecting side C429C_PL2, the data of the 3rd group of transmission circuit send state end C429C_TX/R, the data of the 3rd group of transmission circuit send Enable Pin C429C_ENTX, the corresponding connection of chip configuration Enable Pin C429C_CWSTR of the 3rd group of transmission circuit, the 4th group of transmission circuit
Figure BDA0000481645550000038
sEL,
Figure BDA0000481645550000039
tX/R, ENTX,
Figure BDA00004816455500000310
end is by the data sink 1 receive interruption port C429D_RDY1 of the 4th group of transmission circuit of electrical level matching circuit and the described register circuit of being realized by CPLD chip programming, the data sink 2 receive interruption port C429D_RDY2 of the 4th group of transmission circuit, high/low 16 of the reception data of the 4th group of transmission circuit read selecting side C429D_SEL, the data sink 1 Enable Pin C429D_EN1 of the 4th group of transmission circuit, the data sink 2 Enable Pin C429D_EN2 of the 4th group of transmission circuit, low 16 of the transmission data of the 4th group of transmission circuit write selecting side C429D_PL1, high 16 of the transmission data of the 4th group of transmission circuit write selecting side C429D_PL2, the data of the 4th group of transmission circuit send state end C429D_TX/R, the data of the 4th group of transmission circuit send Enable Pin C429D_ENTX, the corresponding connection of chip configuration Enable Pin C429D_CWSTR of the 4th group of transmission circuit.
Wherein, the chip that described DSP circuit adopts is TMS320F28335.
Wherein, the chip that the register circuit that described CPLD chip programming is realized adopts is EPM570.
Wherein, the chip that described ARINC429 bus transceiving chip circuit adopts is HS3282 and HS3182.
Principle of the present invention is:
As Figure 1-5, a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation, comprises DSP circuit 1, organizes ARINC429 bus transceiving chip circuit 2 more, also comprises the register circuit 3 of being realized by CPLD chip programming; By the data bus terminal of the many groups of DSP circuit 1 read-write ARINC429 bus transceiving chip circuit 2, realize the control to many groups ARINC429 bus transceiving chip to register circuit 3 sending controling instructions of being realized by CPLD chip programming.First coordinate DSP circuit 1, by data bus, configuration signal is passed to many group ARINC429 bus transceiving chip circuit 2 successively by register circuit 3, the ARINC429 bus transceiving chip having configured receives ARINC429 data by serial line interface, any road serial line interface receives after ARINC429 data, D429_RINT is held reset by the register circuit 3 of being realized by CPLD chip programming, to trigger the external interrupt of DSP circuit 1, DSP circuit 1 judges the concrete receiving cable of ARINC429 data by reading D429_RINTA0～D429RINTA3, hold negative edge signal of generation to read the ARINC429 data of corresponding receiving cable by the steering order of configuration D429_A0～D429_A7 end with at D429_ARDY again, because the data bus of ARINC429 bus transceiving chip is 16, and the transceiving format of ARINC429 data is 32, therefore read road ARINC429 data, DSP circuit 1 needs double operation D429_A0～D429_A7 and D429_ARDY end, after current read data operation completes, DSP circuit 1 detects D429_RINT port status, if D429_RINT holds register circuit 3 sets that realized by CPLD chip programming, show that current read operation completes, if D429_RINT holds register circuit 3 resets that realized by CPLD chip programming, indicate that multi-path serial interface receives ARINC429 data simultaneously, or receive other follow-up ARINC429 data when other road serial line interfaces in the process of the ARINC429 data that front port receives reading, now DSP circuit 1 again reads D429_RINTA0～D429RINTA3 and judges the concrete receiving cable of not reading ARINC429 data, and repeat aforementioned read operation process, and again detect D429_RINT port status, until register circuit 3 sets that D429_RINT port is realized by CPLD chip programming detected.When the ARINC429 bus transceiving chip having configured sends ARINC429 data by serial line interface, DSP circuit 1 is according to the steering order of the corresponding configuration of the transmission interface of wanting required use D429_A0～D429_A7 end and generate a negative edge signal and write the ARINC429 data of corresponding transmission interface at D429_ARDY end, because the data bus of ARINC429 bus transceiving chip is 16, and the transceiving format of ARINC429 data is 32, therefore send road ARINC429 data, DSP circuit 1 needs double operation D429_A0～D429_A7 and D429_ARDY end, DSP circuit 1 detects the state of D429_TX/R end afterwards, after D429_TX/R end is by reset, D429_ENTX is held set by DSP circuit 1, then DSP circuit 1 detects the state of D429_TX/R end again, after D429_TX/R end is by set, D429_ENTX is held reset by DSP circuit 1.
The various circuit that adopt in this circuit are all bus read modes at a high speed, control transmitting-receiving sequential and the logical relation of multi-channel A RINC429 data by the register circuit 3 of being realized by CPLD chip programming, avoid occurring multichannel data conflict, loss of data and error code, and connect the reset signal of ARINC429 bus transceiving chip by dsp chip, to make ARINC429 bus transceiving chip reset the in the situation that of data from overflow, guarantee data normal transmission.
Compared with prior art, the invention has the beneficial effects as follows:
1, the present invention can be read multi-channel A RINC429 data in real time and be sent by dsp chip data bus, avoids data collision, loss and error code, realizes the high speed processing to data.
2, multiple external interrupt signals of organizing ARINC429 bus transceiving chip are integrated into one by circuit structure of the present invention more, greatly reduce the usage quantity of DSP circuit external interrupt, the in the situation that of DSP external interrupt resource-constrained, make more multi-channel A RINC429 data transmit-receive become possibility, thoroughly solved data collision when multi-channel A RINC429 data are accepted simultaneously, and data in data handling procedure are lost a yard problem.
3, circuit structure of the present invention is comparatively succinct, and the sequential confusion while having avoided transceiving data has been saved a large amount of computational resources of DSP inside, rationally distributed, easy to operate, cost is low.
Accompanying drawing explanation
Fig. 1 is circuit structure structural diagrams intention of the present invention;
Fig. 2 is the detailed signal processing algorithm schematic diagram of the specific embodiment of the invention;
Fig. 3 is the DSP circuit theory diagrams of the specific embodiment of the invention;
Fig. 4 is the ARINC429 bus transceiving chip circuit theory diagrams of the specific embodiment of the invention;
Fig. 5 is the register circuit schematic diagram that the CPLD chip programming of the specific embodiment of the invention is realized;
Fig. 6 is the transmission example waveform of the ARINC429 bus data 0x8025806A of the specific embodiment of the invention;
Fig. 7 is the reception example waveform of the ARINC429 bus data 0x03958584 of the specific embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention will be further described.The present invention, to receive 8 road ARINC429 data, sends 4 road ARINC429 data instances and describes.All brackets " (transmission) " and " (reception) " only represent data and sense.
In Fig. 1, the closure of each functional block diagram and arrow has represented basic circuit principle of the present invention and signal controlling relation, based on the multi-channel A RINC429 data transmit-receive circuit of DSP and CPLD exploitation, comprise DSP circuit 1, also comprise many group ARINC429 bus transceiving chip circuit 2 and the register circuit 3 of being realized by CPLD chip programming;
Below in conjunction with accompanying drawing 2-accompanying drawing 4, the present invention is further described.
16 bit data bus XD0～XD15 of described DSP circuit 1 are connected with the data bus BD00～BD15 of described many group ARINC429 bus transceiving chip circuit 2 by electrical level matching circuit;
Control output end D429_A0～D429_A7, D429_ARDY, the D429_ENTX end of described DSP circuit 1 are held corresponding connection with control input end D429_A0～D429_A7, D429_ARDY, the D429_ENTX of the described register circuit of being realized by CPLD chip programming 3;
Data accepted flag transmitting terminal D429_RINT, the D429_RINTA0～D429_RINTA3 of the described register circuit of being realized by CPLD chip programming 3 is connected with data accepted flag receiving end D429_RINT and the D429_RINTA0～D429_RINTA3 of described DSP circuit 1;
The ARINC429 data of the described register circuit of being realized by CPLD chip programming 3 send state output end D429_TX/R and are connected with the data transmission state input end D429_TX/R of described DSP circuit 1;
Described many group ARINC429 bus transceiving chip circuit comprise 4 groups, the read-write control end SEL of the 1st group of transmission circuit wherein,
Figure BDA0000481645550000071
eNTX,
Figure BDA0000481645550000072
input end is by being connected with read-write control output end C429A_SEL, C429A_EN1, C429A_EN2, C429A_PL1, C429A_PL2, C429A_ENTX, the C429A_CWSTR of register circuit 3 respectively after electrical level matching circuit, the read-write control end SEL of the 2nd group of transmission circuit,
Figure BDA0000481645550000073
Figure BDA0000481645550000074
eNTX, input end is by being connected with read-write control output end C429B_SEL, C429B_EN1, C429B_EN2, C429B_PL1, C429B_PL2, C429B_ENTX, the C429B_CWSTR of register circuit 3 respectively after electrical level matching circuit, the read-write control end SEL of the 3rd group of transmission circuit,
Figure BDA0000481645550000076
input end is by being connected with read-write control output end C429C_SEL, C429C_EN1, C429C_EN2, C429C_PL1, C429C_PL2, C429C_ENTX, the C429C_CWSTR of register circuit 3 respectively after electrical level matching circuit, the read-write control end SEL of the 4th group of transmission circuit,
Figure BDA0000481645550000077
eNTX,
Figure BDA0000481645550000078
input end is connected with read-write control output end C429D_SEL, C429D_EN1, C429D_EN2, C429D_PL1, C429D_PL2, C429D_ENTX, the C429D_CWSTR of register circuit 3 respectively by after electrical level matching circuit;
The reiving/transmitting state output terminal of the 1st group of transmission circuit in described many group ARINC429 bus transceiving chip circuit 2
Figure BDA0000481645550000079
the corresponding connection of reiving/transmitting state input end C429A_RDY1, C429A_RDY2, C429A_TX/R of the register circuit 3 that TX/R realizes with described CPLD chip programming by electrical level matching circuit, the reiving/transmitting state output terminal of the 2nd group of transmission circuit
Figure BDA0000481645550000081
the corresponding connection of reiving/transmitting state input end C429B_RDY1, C429B_RDY2, C429B_TX/R of the register circuit 3 that TX/R realizes with described CPLD chip programming by electrical level matching circuit, the reiving/transmitting state output terminal of the 3rd group of transmission circuit the corresponding connection of reiving/transmitting state input end C429C_RDY1, C429C_RDY2, C429C_TX/R of the register circuit 3 that TX/R realizes with described CPLD chip programming by electrical level matching circuit, the reiving/transmitting state output terminal of the 4th group of transmission circuit
Figure BDA0000481645550000083
the corresponding connection of reiving/transmitting state input end C429D_RDY1, C429D_RDY2, C429D_TX/R of the register circuit 3 that TX/R realizes with described CPLD chip programming by electrical level matching circuit.
According to above-mentioned connected mode, as shown in Figure 2, the steering order that DSP circuit sends at D429_A0～D429_A7 comprises the instruction of ARINC429 bus transceiving chip initial configuration, ARINC429 bus receives data reading command, ARINC429 bus sends data and writes instruction, receive after these one-level steering orders, the register circuit of being realized by CPLD programming is by the read-write control end of direct control corresponding A RINC429 bus transceiving chip after electrical level matching circuit, also decoding goes out secondary steering order contained in one-level steering order simultaneously, the data of indicating corresponding ARINC429 bus transceiving chip circuit in one-level instruction are sent state end (C429A_TX/R by secondary steering order, C429B_TX/R, C429C_TX/R or C429D_TX/R) the level state data that copy to the register circuit of being realized by CPLD programming send states (transmissions) and hold D429_TX/R to judge for DSP electric circuit inspection, and the data transmission Enable Pin D429_ENTX level state of the register circuit of realizing being programmed by CPLD copies to the data transmission Enable Pin (C429A_ENTX of corresponding ARINC429 bus transceiving chip, C429B_ENTX, C429C_ENTX or C429D_ENTX) to realize DSP circuit, the data of ARINC429 bus transceiving chip circuit are sent and enabled.In the time receiving ARINC429 data, the register circuit of being realized by CPLD programming is all the time by receive interruption (reception) port (C429A_RDY1 of 8 road ARINC429 bus receiving cables, C429A_RDY2, C429B_RDY1, C429B_RDY2, C429C_RDY1, C429C_RDY2, C429D_RDY1, C429D_RDY2) comprehensive Wei Yi road comprehensive receive interruption port D429_RINT, in the time interrupting occurring, receiving cable coded address (transmission) end D429_RINTA0～D429_RINTA3 is sent to in current receiving cable coded address to interrupt reading for DSP circuit, if Multiple Interrupt occurs or new receive interruption occurs when reading out data simultaneously, DSP circuit completes after current data read operation, comprehensive receive interruption port D429_RINT maintains interruption status, and other are not sent to receiving cable coded address (transmission) end D429_RINTA0～D429_RINTA3 in the channel coding address of read channel, realize whole receiving circuit with this accurate, high speed processing, avoid data collision, lose and error code.
The chip that DSP circuit of the present invention adopts is TMS320F28335.
CPLD chip of the present invention adopts EPM570.
The chip that ARINC429 bus transceiving chip circuit of the present invention adopts is HS3282 and HS3182.
Fig. 5 is the register circuit schematic diagram that the CPLD chip programming of the specific embodiment of the invention is realized;
Fig. 6 is the transmission example waveform of the ARINC429 bus data 0x8025806A of the specific embodiment of the invention; This transmission example waveform is the schematic diagram that correct coding of the present invention is sent out several.
Fig. 7 is the reception example waveform of the ARINC429 bus data 0x03958584 of the specific embodiment of the invention.This reception example waveform is that the present invention correctly, inerrably encodes and receives the schematic diagram of number.
The not detailed disclosed part of the present invention belongs to the known technology of this area.
Although above the illustrative embodiment of the present invention is described; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and definite the spirit and scope of the present invention in, these variations are apparent, all utilize innovation and creation that the present invention conceives all at the row of protection.

Claims (4)

1.一种基于DSP和CPLD开发的多路ARINC429数据收发电路结构，包括DSP电路（1），多组ARINC429总线收发芯片电路（2），其特征在于还包括由CPLD芯片编程实现的寄存器电路（3）；1. A multi-channel ARINC429 data transceiver circuit structure developed based on DSP and CPLD, comprising a DSP circuit (1), a plurality of groups of ARINC429 bus transceiver chip circuits (2), characterized in that it also includes a register circuit realized by CPLD chip programming ( 3); 所述DSP电路（1）的数据总线XD0～XD15通过电平匹配电路与所述多组ARINC429总线收发芯片电路（2）的数据总线BD00～BD15连接，所述DSP电路（1）的控制指令端D429_A0～D429_A7、控制指令完成激励端D429_ARDY、数据发送状态端D429_TX/R、数据发送使能端D429_ENTX、综合接收中断端口D429_RINT、接收通道编码地址端D429_RINTA0～D429_RINTA3与所述由CPLD芯片编程实现的寄存器电路（3）的控制指令端D429_A0～D429_A7、控制指令完成激励端D429_ARDY、数据发送状态端D429_TX/R、数据发送使能端D429_ENTX、综合接收中断端口D429_RINT、接收通道编码地址端D429_RINTA0～D429_RINTA3对应连接，所述多组ARINC429总线收发芯片电路（2）包括4组，能够同时接收8路ARINC429数据，发送4路ARINC429数据，其中的第1组收发电路的数据接收器1接收中断端口数据接收器2接收中断端口
Figure FDA0000481645540000012
接收数据高/低16位读取选择端SEL、数据接收器1使能端
Figure FDA0000481645540000013
数据接收器2使能端
Figure FDA0000481645540000014
、发送数据低16位写入选择端
Figure FDA0000481645540000015
发送数据高16位写入选择端
Figure FDA0000481645540000016
数据发送状态端TX/R、数据发送使能端ENTX、芯片配置使能端通过电平匹配电路与所述由CPLD芯片编程实现的寄存器电路（3）的第1组收发电路的数据接收器1接收中断端口C429A_RDY1、第1组收发电路的数据接收器2接收中断端口C429A_RDY2、第1组收发电路的接收数据高/低16位读取选择端C429A_SEL、第1组收发电路的数据接收器1使能端C429A_EN1、第1组收发电路的数据接收器2使能端C429A_EN2、第1组收发电路的发送数据低16位写入选择端C429A_PL1、第1组收发电路的发送数据高16位写入选择端C429A_PL2、第1组收发电路的数据发送状态端C429A_TX/R、第1组收发电路的数据发送使能端C429A_ENTX、第1组收发电路的芯片配置使能端C429A_CWSTR对应连接，第2组收发电路的
Figure FDA0000481645540000021
Figure FDA0000481645540000022
TX/R、ENTX、
Figure FDA0000481645540000023
端通过电平匹配电路与所述由CPLD芯片编程实现的寄存器电路（3）的第2组收发电路的数据接收器1接收中断端口C429B_RDY1、第2组收发电路的数据接收器2接收中断端口C429B_RDY2、第2组收发电路的接收数据高/低16位读取选择C429B_SEL、第2组收发电路的数据接收器1使能端C429B_EN1、第2组收发电路的数据接收器2使能端C429B_EN2、第2组收发电路的发送数据低16位写入选择端C429B_PL1、第2组收发电路的发送数据高16位写入选择端C429B_PL2、第2组收发电路的数据发送状态端C429B_TX/R、第2组收发电路的数据发送使能端C429B_ENTX、第2组收发电路的芯片配置使能端C429B_CWSTR对应连接，第3组收发电路的
Figure FDA0000481645540000024
SEL、
Figure FDA0000481645540000025
TX/R、ENTX、
Figure FDA0000481645540000026
端通过电平匹配电路与所述由CPLD芯片编程实现的寄存器电路（3）的第3组收发电路的数据接收器1接收中断端口C429C_RDY1、第3组收发电路的数据接收器2接收中断端口C429C_RDY2、第3组收发电路的接收数据高/低16位读取选择端C429C_SEL、第3组收发电路的数据接收器1使能端C429C_EN1、第3组收发电路的数据接收器2使能端C429C_EN2、第3组收发电路的发送数据低16位写入选择端C429C_PL1、第3组收发电路的发送数据高16位写入选择端C429C_PL2、第3组收发电路的数据发送状态端C429C_TX/R、第3组收发电路的数据发送使能端C429C_ENTX、第3组收发电路的芯片配置使能端C429C_CWSTR对应连接，第4组收发电路的
Figure FDA0000481645540000027
Figure FDA0000481645540000028
SEL、
Figure FDA0000481645540000029
TX/R、ENTX、
Figure FDA00004816455400000210
端通过电平匹配电路与所述由CPLD芯片编程实现的寄存器电路（3）的第4组收发电路的数据接收器1接收中断端口C429D_RDY1、第4组收发电路的数据接收器2接收中断端口C429D_RDY2、第4组收发电路的接收数据高/低16位读取选择端C429D_SEL、第4组收发电路的数据接收器1使能端C429D_EN1、第4组收发电路的数据接收器2使能端C429D_EN2、第4组收发电路的发送数据低16位写入选择端C429D_PL1、第4组收发电路的发送数据高16位写入选择端C429D_PL2、第4组收发电路的数据发送状态端C429D_TX/R、第4组收发电路的数据发送使能端C429D_ENTX、第4组收发电路的芯片配置使能端C429D_CWSTR对应连接。The data buses XD0-XD15 of the DSP circuit (1) are connected to the data buses BD00-BD15 of the multiple sets of ARINC429 bus transceiver chip circuits (2) through a level matching circuit, and the control command terminal of the DSP circuit (1) D429_A0～D429_A7, control command completion excitation terminal D429_ARDY, data transmission status terminal D429_TX/R, data transmission enable terminal D429_ENTX, integrated receiving interrupt port D429_RINT, receiving channel code address terminal D429_RINTA0～D429_RINTA3 and the register realized by CPLD chip programming Corresponding connection of control command terminal D429_A0～D429_A7, control command completion excitation terminal D429_ARDY, data transmission status terminal D429_TX/R, data transmission enable terminal D429_ENTX, integrated receiving interrupt port D429_RINT, receiving channel code address terminal D429_RINTA0～D429_RINTA3 of circuit (3) , the multiple groups of ARINC429 bus transceiver chip circuits (2) include 4 groups, capable of simultaneously receiving 8-way ARINC429 data and sending 4-way ARINC429 data, wherein the data receiver 1 of the first group of transceiver circuits receives the interrupt port Data Receiver 2 Receive Interrupt Port
Figure FDA0000481645540000012
Receive data high/low 16-bit read selection terminal SEL, data receiver 1 enable terminal
Figure FDA0000481645540000013
Data receiver 2 enable terminal
Figure FDA0000481645540000014
, Send data lower 16 bits to write to select terminal
Figure FDA0000481645540000015
Send data high 16 bits to write to select terminal
Figure FDA0000481645540000016
Data transmission status terminal TX/R, data transmission enabling terminal ENTX, chip configuration enabling terminal Through the level matching circuit and the register circuit (3) realized by CPLD chip programming, the data receiver 1 of the first group of transceiver circuits receives the interrupt port C429A_RDY1, and the data receiver 2 of the first group of transceiver circuits receives the interrupt port C429A_RDY2, The receiving data high/low 16-bit read selection terminal C429A_SEL of the first group of transceiver circuits, the data receiver 1 enable terminal C429A_EN1 of the first group of transceiver circuits, the data receiver 2 enable terminal C429A_EN2 of the first group of transceiver circuits, The lower 16 bits of the sending data of the first group of transceiver circuits are written into the selection terminal C429A_PL1, the upper 16 bits of the sending data of the first group of transceiver circuits are written into the selection terminal C429A_PL2, the data transmission status of the first group of transceiver circuits C429A_TX/R, the first group The data transmission enable terminal C429A_ENTX of the transceiver circuit, the chip configuration enable terminal C429A_CWSTR of the first group of transceiver circuits are connected correspondingly, and the second group of transceiver circuits
Figure FDA0000481645540000021
Figure FDA0000481645540000022
TX/R, ENTX,
Figure FDA0000481645540000023
The data receiver 1 receiving interrupt port C429B_RDY1 of the second group of transceiver circuits of the register circuit (3) realized by CPLD chip programming through the level matching circuit, and the data receiver 2 receiving interrupt port C429B_RDY2 of the second group of transceiver circuits , The high/low 16-bit read selection of the received data of the second group of transceiver circuits C429B_SEL, the data receiver 1 enable terminal of the second group of transceiver circuits C429B_EN1, the data receiver 2 enable terminal of the second group of transceiver circuits C429B_EN2, the second group of transceiver circuits The lower 16 bits of the sending data of the 2 groups of transceiver circuits are written into the selection terminal C429B_PL1, the upper 16 bits of the sending data of the second group of transceiver circuits are written into the selection terminal C429B_PL2, the data sending status terminal of the second group of transceiver circuits C429B_TX/R, the second group The data transmission enable terminal C429B_ENTX of the transceiver circuit, the chip configuration enable terminal C429B_CWSTR of the second group of transceiver circuits are connected correspondingly, and the third group of transceiver circuits
Figure FDA0000481645540000024
SEL,
Figure FDA0000481645540000025
TX/R, ENTX,
Figure FDA0000481645540000026
The data receiver 1 receiving interrupt port C429C_RDY1 of the third group of transceiver circuits of the register circuit (3) realized by CPLD chip programming through the level matching circuit, and the data receiver 2 receiving interrupt port C429C_RDY2 of the third group of transceiver circuits , The receiving data high/low 16-bit read selection terminal C429C_SEL of the third group of transceiver circuits, the data receiver 1 enable terminal C429C_EN1 of the third group of transceiver circuits, the data receiver 2 enable terminal C429C_EN2 of the third group of transceiver circuits, The lower 16 bits of the sending data of the third group of transceiver circuits are written into the selection port C429C_PL1, the upper 16 bits of the sending data of the third group of sending and receiving circuits are written into the selection port C429C_PL2, the data sending status port of the third group of sending and receiving circuits C429C_TX/R, the third The data transmission enable terminal C429C_ENTX of the first group of transceiver circuits, the chip configuration enable terminal C429C_CWSTR of the third group of transceiver circuits are connected correspondingly, and the fourth group of transceiver circuits
Figure FDA0000481645540000027
Figure FDA0000481645540000028
SEL,
Figure FDA0000481645540000029
TX/R, ENTX,
Figure FDA00004816455400000210
The data receiver 1 receiving interrupt port C429D_RDY1 of the fourth group transceiver circuit of the register circuit (3) realized by CPLD chip programming through the level matching circuit, and the data receiver 2 receiving interrupt port C429D_RDY2 of the fourth group transceiver circuit , The receiving data high/low 16-bit read selection terminal C429D_SEL of the fourth group of transceiver circuits, the data receiver 1 enable terminal C429D_EN1 of the fourth group of transceiver circuits, the data receiver 2 enable terminal C429D_EN2 of the fourth group of transceiver circuits, The lower 16 bits of the sending data of the fourth group of transceiver circuits are written into the selection terminal C429D_PL1, the upper 16 bits of the sending data of the fourth group of transceiver circuits are written into the selection terminal C429D_PL2, the data transmission status of the fourth group of transceiver circuits C429D_TX/R, the fourth The data transmission enable terminal C429D_ENTX of the first group of transceiver circuits and the chip configuration enable terminal C429D_CWSTR of the fourth group of transceiver circuits are connected correspondingly. 2.根据权利要求1所述的一种基于DSP和CPLD开发的多路ARINC429数据收发电路结构，其特征是：所述DSP电路（1）采用的芯片是TMS320F28335。2. A multi-channel ARINC429 data transceiver circuit structure developed based on DSP and CPLD according to claim 1, characterized in that: the chip used in the DSP circuit (1) is TMS320F28335. 3.根据权利要求1所述的一种基于DSP和CPLD开发的多路ARINC429数据收发电路结构，其特征是：所述CPLD芯片编程实现的寄存器电路（3）采用的芯片是EPM570。3. A multi-channel ARINC429 data transceiver circuit structure developed based on DSP and CPLD according to claim 1, characterized in that: the chip used in the register circuit (3) implemented by programming the CPLD chip is EPM570. 4.根据权利要求1所述的一种基于DSP和CPLD开发的多路ARINC429数据收发电路结构，其特征是：所述ARINC429总线收发芯片电路（2）采用的芯片是HS3282和HS3182。4. A multi-channel ARINC429 data transceiver circuit structure developed based on DSP and CPLD according to claim 1, characterized in that: the chips used in the ARINC429 bus transceiver chip circuit (2) are HS3282 and HS3182.
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