CN204695304U - A kind of 1553B Bus PC 104 interface board - Google Patents
A kind of 1553B Bus PC 104 interface board Download PDFInfo
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- CN204695304U CN204695304U CN201520375972.9U CN201520375972U CN204695304U CN 204695304 U CN204695304 U CN 204695304U CN 201520375972 U CN201520375972 U CN 201520375972U CN 204695304 U CN204695304 U CN 204695304U
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Abstract
The utility model discloses a kind of 1553B Bus PC 104 interface board, comprise a FPGA master controller, and PC104 interface and 1553B transceiver controller; PC104 interface controller is provided with in FPGA master controller; PC104 interface comprises PC104 interface connector and level transferring chip group, and the two is connected with control bus by data bus, address bus; Level transferring chip group is connected with PC104 interface controller in FPGA master controller with control bus by data bus, address bus; 1553B transceiver controller comprises 1553B transceiver and 1553B connector, and 1553B connector is connected with 1553B transceiver communications, 1553B transceiver and the communication connection of FPGA master controller.This interface board enables main frame connect 1553B bus network, becomes a terminal in network, realizes distributing real communication.
Description
Technical field
The utility model relates to a kind of 1553B Bus PC 104 interface board.
Background technology
PC/104 is a kind of industrial computer bus standard, is embedded Control and the bus standard formulated specially, electrically completely different from other PC buses with mechanical specification, is the embedded control system of a kind of optimization, small-sized, nesting structural embedded control.PC104 adopts small scale structures compared with other PC buses, and the mechanical dimension of standard module is 96 × 90mm, is applied to portable use especially.PC104 bus also adopts stacking-type to connect, remove bus backplane and plate slideway, bus is with the stacked connection of " pin " and " hole " form, and namely between PC104 bus module, the connection of bus mutually to be stung with the hole of lower floor by the pin on upper strata and is connected, and this laminate packaging has fabulous shock resistance.
1553B bus is as the conventional high reliability bus of the military, and its reliability, shock resistance, extensibility modularization etc. require to agree with mutually with PC104 bus, therefore realizes 1553B bus functionality by PC/104 interface bus module and have very strong practicality.
In view of this, special proposition the utility model.
Utility model content
The purpose of this utility model is to provide a kind of 1553B Bus PC 104 interface board, comprises a FPGA master controller, and the PC104 interface communicated to connect with FPGA master controller respectively and 1553B transceiver controller form; PC104 interface controller is provided with in FPGA master controller;
PC104 interface comprises PC104 interface connector and level transferring chip group, and the two is connected with control bus by data bus, address bus; Level transferring chip group is connected with PC104 interface controller in FPGA master controller with control bus by data bus, address bus;
1553B transceiver controller comprises 1553B transceiver and 1553B connector, and 1553B connector is connected with 1553B transceiver communications, 1553B transceiver and the communication connection of FPGA master controller.
Preferably, in above-mentioned 1553B Bus PC 104 interface board, described level transferring chip group is made up of 4 SN74ALVC164245 chips.
Preferably, in above-mentioned 1553B Bus PC 104 interface board, described PC104 interface connector is made up of the first connector and the second connector, and wherein the first connector is 64 pins, comprise data pin, address pin, read-write control signal pin, interrupt request singal pin and power supply; Second connector is 40 pins, comprises data pin, extended address pin and interrupt request singal pin.
After adopting technique scheme, the utility model has following beneficial effect:
1553B Bus PC 104 interface board of the present utility model, adopt PC104 bus standard, can be connected together with the motherboard stack of PC104 bus, the communication interface meeting MIL-STD-1553B standard is provided, main frame is enable to connect 1553B bus network, become a terminal in network, realize distributing real communication.
Accompanying drawing explanation
Fig. 1 is 1553B Bus PC 104 interface board module totality block diagram.
Fig. 2 is PC104 interface framework.
Fig. 3-1,3-2 are PC104 interface singnal charts.
Fig. 4 is 1553B communication control section block diagram.
Fig. 5 is 1553B data memory format figure.
Fig. 6 is 1553B Bus PC 104 interface board mounting structure figure.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail, to help understanding content of the present utility model.
As depicted in figs. 1 and 2,1553B Bus PC 104 interface board, adopt Standard PC 104 agreement regulation board structure, board is of a size of 96mm × 90mm, comprise a FPGA master controller, and the PC104 interface communicated to connect with FPGA master controller respectively and 1553B transceiver controller form; PC104 interface controller is provided with in FPGA master controller;
PC104 interface comprises PC104 interface connector and level transferring chip group, and the two is connected with control bus by data bus, address bus; Level transferring chip group is connected with PC104 interface controller in FPGA master controller with control bus by data bus, address bus; PC104 interface singnal chart is as Fig. 3;
1553B transceiver controller comprises multiple unit, and each unit is made up of the 1553B transceiver communicated to connect successively, transformer and 1553B connector.
PC104 interface connector is made up of the first connector and the second connector, and wherein the first connector 64 pin, mainly includes low 8bit data bus, 20bit address bus, read-write control signal, interrupt request singal and power supply.Second connector 40 pin, mainly includes high 8bit data bus, extended address bus and interrupt request singal.
Level transferring chip group is made up of 4 SN74ALVC164245 chips, SN74ALVC164245 is the 5V-3.3V level conversion device of TI company, realize 2 group of 8 tunnel level conversion, this chip can well solve the unmatched problem of 3.3V Transistor-Transistor Logic level in PC104 interface 5V Transistor-Transistor Logic level and FPGA.
In FPGA master controller, PC104 interface controller is included in FPGA inside, is completed by VHDL program, mainly realizes main frame by the read-write capability of PC104 to master controller.
FPGA master controller part is the core of module, the programmable logic device (PLD) EP3C55F484I7N of ALTERA company is adopted to complete, be mainly used to remote terminal (RT) function realized in 1553B agreement, as shown in Figure 4, wherein each functions of modules is as follows for the composition of this part:
A) BC → RT message processing module: RT receives BC send and receives command word and stated number destination data word, beams back a status word to BC after verification message.Command word and data word receive not have the conitnuous forms of word space.
B) RT → BC message processing module: RT receives the transmission command word that BC sends, and beams back a status word to BC, succeeded by stated number destination data word after examining command word.Status word and data word send not have the conitnuous forms of word space.
C) RT → RT message processing module:
1. RT is as the receiving end (similar BC → RT message) of RT → RT message
2. RT is as the transmitting terminal (similar RT → BC message) of RT → RT message
D) BC → RT message processing module (broadcast): RT receives reception command word and the stated number destination data word that an address field sending of BC is " 11111 ", by the broadcasting instructions received bit set in status word but not loopback status word after verification message.Command word and data word receive not have the conitnuous forms of word space.
E) RT → RT message processing module (broadcast): RT is as the receiving end of RT → RT message.
F) mode codeword processing module: module achieves " synchronous not with data word ", " send laststate word ", " transmitter closedown ", " cancel transmitter to close ", " forbid end mark position ", " end mark position is forbidden in cancellation ", " transmission vector font ", " band data word synchronous ", " sending a upper instruction word " mode code function.
G) mode codeword processing module (broadcast): module achieves " synchronous not with data word ", " transmitter closedown ", " cancel transmitter to close ", " forbid end mark position ", " end mark position is forbidden in cancellation ", " band data word synchronous " broadcast mode code function.
Mode code allocation table is as follows:
Synchronous (00001) not with data word: after RT receives this mode instruction, by time tag counter O reset, thus complete the synchronous of the total built-in unit of 1553B.
Send laststate word (00010): after RT receives this instruction, beam back the status word in the upper efficient message that this terminal receives.Status word is not upgraded when performing which code operation.
Transmitter cuts out (00100): this instruction only uses in two remaining bus system.Be used for making RT close the transmitter be connected with remaining bus.
Cancel transmitter and close (00101): this instruction only uses in two remaining bus system.Be used for making remote terminal start previous buttoned-up transmitter.
Forbid end mark position (00110): end mark position in RT forces to be set to logical zero by this instruction.
Cancel and forbid end mark position (00111): this instruction is used for cancelling the prohibiting function of " forbidding end mark position ".
Send vector font (10000): RT can loopback data word pre-set after receiving this mode instruction.
Synchronous (10001) with data word: data word content is write time tag counter after receiving this mode instruction by RT, thus completes the synchronous of bus.
Send a upper instruction word (10010): after RT receives this mode instruction, using the instruction word in a upper efficient message as the data word loopback of message to BC, do not upgrade status word when performing which code operation.
In master controller, 1553B data storage section adopts FPGA internal storage unit dual port RAM to realize.Data memory format as shown in Figure 5.
1553B transceiver controller is responsible for correct reception and is sent the command word, data word, the status word that meet 1553B bus protocol form.
1553B transceiver controller part is the part of carrying out data communication with 1553B transceiver (Hi-1573), and the interface signal of this part is as shown in table 1:
Table 1 1553B transceiver controller interface table
| Interface defines | Interface describes | Interface direction | Reset rear port state |
| TXA | Transmitter A data input (forward) | Export | Low level |
| TXA# | Transmitter A data input (oppositely) | Export | Low level |
| TXINHA | Transmitter A disable signal, high level is effective | Export | High level |
| RXA | Receiver A data export (forward) | Input | Low level |
| RXA# | Receiver A data export (oppositely) | Input | Low level |
| RXENA | Receiver A enable signal, high level is effective | Export | High level |
| TXB | Transmitter B data input (forward) | Export | Low level |
| TXB# | Transmitter B data input (oppositely) | Export | Low level |
| TXINHB | Transmitter B disable signal, high level is effective | Export | High level |
| RXB | Receiver B data export (forward) | Input | Low level |
| RXB# | Receiver B data export (oppositely) | Input | Low level |
| RXENB | Receiver B enable signal, high level is effective | Export | High level |
Data send: 1553B signal adopts Manchester II type alternating binary coding, and speed is 1Mbit/s, so each is made up of 0.5us high level and 0.5us low level.1553B transceiver controller adopts 2MHz clock to send data word or status word;
Data receiver: to accept filter and reception is sampled as committed step.
Accepting filter, employing 40MHz clock is double samples to received signal, if sampled value is different, then thinks to there is burr in Received signal strength, and is filtered out (the method can filter out in signal the burr being less than 25ns).
Receiving sampling adopts 40MHz clock to sample to filtered signal, counter carries out+1 counting at rising edge clock, if Received signal strength changes or Counter Value equals 19 hour counters clearings, the reception data under adopting when counter equals 15 think valid data, and are received.
Product is installed: this 1553B Bus PC 104 interface board adopts Standard PC 104 agreement regulation board structure, and board is of a size of 96mm × 90mm, and mounting structure figure is as Fig. 6.
The above is only preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (3)
1. 1553B Bus PC 104 interface board, is characterized in that, comprises a FPGA master controller, and the PC104 interface communicated to connect with FPGA master controller respectively and 1553B transceiver controller; PC104 interface controller is provided with in FPGA master controller;
PC104 interface comprises PC104 interface connector and level transferring chip group, and the two is connected with control bus by data bus, address bus; Level transferring chip group is connected with PC104 interface controller in FPGA master controller with control bus by data bus, address bus;
1553B transceiver controller comprises 1553B transceiver and 1553B connector, and 1553B connector is connected with 1553B transceiver communications, 1553B transceiver and the communication connection of FPGA master controller.
2. 1553B Bus PC 104 interface board according to claim 1, is characterized in that, described level transferring chip group is made up of 4 SN74ALVC164245 chips.
3. 1553B Bus PC 104 interface board according to claim 1, it is characterized in that, described PC104 interface connector is made up of the first connector and the second connector, wherein the first connector is 64 pins, comprise data pin, address pin, read-write control signal pin, interrupt request singal pin and power supply; Second connector is 40 pins, comprises data pin, extended address pin and interrupt request singal pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520375972.9U CN204695304U (en) | 2015-06-03 | 2015-06-03 | A kind of 1553B Bus PC 104 interface board |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520375972.9U CN204695304U (en) | 2015-06-03 | 2015-06-03 | A kind of 1553B Bus PC 104 interface board |
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| CN204695304U true CN204695304U (en) | 2015-10-07 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106886206A (en) * | 2015-12-15 | 2017-06-23 | 西安富成防务科技有限公司 | A kind of missile-borne computer product Auto-Test System |
| CN107943732A (en) * | 2017-11-21 | 2018-04-20 | 北京宇航系统工程研究所 | One kind realizes 1553B bus modules based on production domesticization FPGA device |
-
2015
- 2015-06-03 CN CN201520375972.9U patent/CN204695304U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106886206A (en) * | 2015-12-15 | 2017-06-23 | 西安富成防务科技有限公司 | A kind of missile-borne computer product Auto-Test System |
| CN107943732A (en) * | 2017-11-21 | 2018-04-20 | 北京宇航系统工程研究所 | One kind realizes 1553B bus modules based on production domesticization FPGA device |
| CN107943732B (en) * | 2017-11-21 | 2020-05-12 | 北京宇航系统工程研究所 | 1553B bus module realized based on domestic FPGA device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: 1553B bus PC104 interface board Effective date of registration: 20151211 Granted publication date: 20151007 Pledgee: Beijing technology intellectual property financing Company limited by guarantee Pledgor: Beijing Vast-Tagee Technology Co., Ltd. Registration number: 2015990001107 |
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| PLDC | Enforcement, change and cancellation of contracts on pledge of patent right or utility model | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20170113 Granted publication date: 20151007 Pledgee: Beijing technology intellectual property financing Company limited by guarantee Pledgor: Beijing Vast-Tagee Technology Co., Ltd. Registration number: 2015990001107 |
|
| PLDC | Enforcement, change and cancellation of contracts on pledge of patent right or utility model |