CN203084719U - SJA1000 interface IP core based on processor local bus (PLB) - Google Patents
SJA1000 interface IP core based on processor local bus (PLB) Download PDFInfo
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Abstract
The utility model relates to an SJA1000 interface IP core based on a processor local bus (PLB). The SJA1000 interface IP core based on the PLB is characterized in that the IP core comprises a PLB interface module, a user logic module and an interrupt control module. The PLB interface module is connected with the PLB through an address/data signal line and a control signal line, the PLB interface module is connected with the user logic module and the interrupt control module through an IPIC interface, the user logic module is connected with the interrupt control module through an IntrEvent to achieve an interrupt control function, the user logic module is further connected with an SJA 1000 independent CAN controller through the address/data signal line and the control signal line, and the interrupt control module is connected with a CPU through an Intr2Bus_DevIntr signal. The SJA1000 interface IP core based on the PLB is reasonable in design, achieves nationalization and localization of the IP core with the adoption of a PLB+ SJA 1000 interface IP core+SAJ1000 method, simplifies development of the IP core, effectively reduces development cost of products, and improves market competitiveness.
Description
Technical field
The utility model belongs to the industrial bus technical field, especially a kind of SJA1000 interface IP kernel based on the PLB bus.
Background technology
SJA1000 is the independent CAN bus controller, is used to articulate any node device under the CAN bus.The SJA1000 functional module comprises the interface management module, sends data buffer, receive data buffer, checks and accepts wave filter, bit stream processor etc.The interface management module of SJA1000 is used to explain the order from external piloting control system device, provide interrupting information and status information to outside master controller, this just externally sets up an interface in order to realize the exchanges data between master controller and the SJA1000 independent CAN bus controller between master controller and the SJA1000, adopt which type of peripheral control unit and adopt which type of interface mode to depend on.Though the external piloting control system of SJA1000 device can use the liaison function of ARM, chip microcontroller and independent CAN controller, but, the IP kernel that designs owing to the VHDL language based on FPGA can provide dirigibility and the better controller of performance, the FPGA/SOPC technology will be to realize the development trend of embedded system, therefore, will be based on the FPGA_ system-on-chip designs of the soft nuclear of PLB bus MicroBlaze as first-selection.
In the prior art, realize that the conventional method of PLB bus and the mutual communication of CAN equipment is: use the IP kernel of PLB+CAN to form a complete CAN node.Above-mentioned IP kernel is LogiCORE IP XPS Controller AreaNetwork (CAN) IP kernel, be that U.S. XILINX company aims at the general-purpose interface IP kernel that the CAN bus apparatus provides, its SJA1000 CAN controllers with XILINX company is identical on sequential, any CAN node device be can articulate, and can order and recipient node data be sent to node device by the soft nuclear of Microblaze of PLB bus.But this IP kernel could use after must authorizing and pay, and require to pay according to the quantity of equipment, an equipment is handed over a money, and that will be the expense of a costliness if the intelligent parking lot of a hundreds of parking stall is paid according to the CAN equipment on each parking stall; Secondly, with regard to the implementation method of LogiCORE IP XPS Controller Area Network (CAN) IP kernel itself, this IP kernel also designs the function of SJA1000 CAN controllers in this IP kernel simultaneously, as functions such as the examination wave filter of SJA1000, bit stream processors, be embodied in LogiCORE IP XPS Controller AreaNetwork (CAN) IP kernel and be all functions of transport layer, therefore, this IP kernel implementation method is very complicated.
Summary of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, provide a kind of reasonable in design, cost performance is high, implementation method is simply based on the SJA1000 interface IP kernel of PLB bus.
The utility model solves its technical matters and takes following technical scheme to realize:
A kind of SJA1000 interface IP kernel based on the PLB bus, comprise PLB interface module, user logic module and interrupt control module, described PLB interface module is connected with the PLB bus with control signal wire by the address/data signal line, and this PLB interface module is connected with user logic module and interrupt control module by the IPIC interface; Be connected by interrupt control signal wire Intr2Bus_DevIntr between described user logic module and the interrupt control module and realize the interrupt control function, the user logic module also is connected with the SJA1000 CAN controllers with control signal wire by the address/data signal line; The interrupt control module connects CPU by the Intr2Bus_DevIntr signal.
And described PLB interface module, user logic module, interrupt control module are built in the FPGA.
And described CPU kind comprises the MicroBlaze soft nucleus CPU, and is built in the FPGA.
And described user logic module selects module to connect and compose by read-write state machine and address date, and the read-write state machine transmits with carrying out bi-directional data between the PLC interface module by IPIC control signal (IPIC Control Signals); Described address/data selects module to transmit with carrying out bi-directional data between the PLB interface module by address wire (Address Bus), data line (Data Bus).
And, the interface module that described PLB interface module carries for the PLB bus.
And described user logic module comprises following input signal: from the clock signal (Bus_2IP_Clk) of PLB interface module, reset signal (Bus2IP_Reset), address signal (Bus2IP_Addr[4:0]), data-signal (Bus2IP_Data[24:31]) and from the look-at-me (INT) of SJA1000 CAN controllers, data-signal (DATA[7:0]); Described user logic module comprises following output signal: send to the look-at-me (IP2Bus_IntrEvent), answer signal (IP2Bus_Ack), data-signal (Bus2IP_Data[24:31]) of PLB interface module, send to address/data signal (DATA[7:0]), address enable signal (ALE), chip selection signal (CS), read-write (RD/WR), the reset signal (RST) of SJA1000 CAN controllers and the interrupt event signal (IntrEvent) that sends to the interrupt control module.
Advantage of the present utility model and good effect are:
The service function that the utility model utilizes existing SJA1000 controller to provide, the SJA1000 function is separated from IP kernel, be absorbed in the data-interface function of realization to SJA1000, IP kernel nucleus module (user logic module) is by the data-transformation facility of IPIC interface realization with the PLB interface module, realize SJA1000 CAN controllers data write function by the read-write state machine, by the two-way interrupt control function between IntrEvent interrupt trigger signal triggering interrupt control module realization PLB and the CAN equipment is provided; The utility model adopts the method for PLB+SJA1000 interface IP kernel+SAJ1000 to realize the production domesticization and the localization of IP kernel, has simplified the exploitation of IP kernel, effectively reduces the Products Development cost, has strengthened the market competitiveness.
Description of drawings
Fig. 1 is a circuit block diagram of the present utility model;
Fig. 2 is the structural representation of user logic module;
Fig. 3 be between the utility model internal module and and SJA1000 between the signal connection diagram;
Fig. 4 is an application system connection diagram of the present utility model;
Fig. 5 is the sequential chart of writing of read-write state machine;
Fig. 6 is the sequential chart of reading of read-write state machine.
Embodiment
Below in conjunction with accompanying drawing the utility model embodiment is further described:
A kind of SJA1000 interface IP kernel based on the PLB bus, as shown in Figure 1, comprise PLB interface module, user logic module and interrupt control module, described PLB interface module is connected with the PLB bus with control signal wire by the address/data signal line, this PLB interface module is connected with user logic module and interrupt control module by IPIC interface (IPIC Interface), and this IPIC interface is used to provide between user logic module and the PLB interface module and the exchange of the internal logic between PLB interface module and the interrupt control module; Be connected by interrupt control signal wire (IntrEvent) between described user logic module and the interrupt control module, this interrupt control module is used to realize for interrupt control outside and inside, and zero clearing interrupt control position, the interrupt control module is connected with CPU by the Intr2Bus_DevIntr signal wire, described CPU kind comprises the MicroBlaze soft nucleus CPU, and is built in the FPGA.The user logic module also is connected with the SJA1000 CAN controllers with control signal wire by the address/data signal line.PLB interface module, user logic module, interrupt control module are built in the FPGA.
In the present embodiment, the PLB interface module is the interface module that the PLB bus carries, this PLB interface module provides an interface between user logic module and the PLB, the PLB interface module is guaranteed the basic function when the PLB interface is operated, and finishes agreement necessary between PLB and the IPIC interface and sequential communication.
The user logic module as shown in Figure 2, selects module to connect and compose by read-write state machine and address date as the corn module of SJA1000 interface IP kernel.This read-write state machine carries out bi-directional data by IPIC interface (IPICControl Signals) and PLB interface module and transmits, and this read-write state machine is connected with the interrupt control module by the IntrEvent signal wire and realizes the interrupt control function; This address/data selects module to carry out the bi-directional data transmission by address wire (Address Bus), data line (Data Bus) with the PLB interface module.
As shown in Figure 3, the user logic module comprises and PLB interface module, interrupt control module and SJA1000 CAN controllers between input/output signal, wherein the input signal of user logic module comprises: from the clock signal (Bus_2IP_Clk) of PLB interface module, reset signal (Bus2IP_Reset), address signal (Bus2IP_Addr[4:0]), data-signal (Bus2IP_Data[24:31]), from the look-at-me (INT) of SJA1000 CAN controllers, data-signal (DATA[7:0]); The output signal of user logic module: the look-at-me (IP2Bus_IntrEvent), answer signal (IP2Bus_Ack), data-signal (Bus2IP_Data[24:31]) that upwards send to the PLB interface module; Send to address/data signal (DATA[7:0]), address enable signal (ALE), chip selection signal (CS), read-write (RD/WR), the reset signal (RST) of SJA1000 CAN controllers downwards; Interrupt event signal (IntrEvent) to the transmission of interrupt control module.
As shown in Figure 4, SJA1000 interface IP kernel of the present utility model is built in the FPGA, also comprises CPU, SPI interface IP kernel, SSI interface IP kernel, GPIO module and ISA interface module on this FPGA.CPU by SJA1000 interface IP kernel and GPIO interface link to each other with SJA1000 CAN controllers in the AGV interface board, by the SPI interface with the gyroscope in the AGV interface board link to each other with accelerometer, to pass through the SSI interface continuous with the scrambler in the AGV interface board; Be connected with PC104 by the ISA interface module; This SJA1000 CAN controllers can connect any CAN equipment, and for example motor 1 is to motor 8, thereby constitutes a complete AGV control system.
User state machine in the user logic module is realized corresponding read-write control function by judging current read-write state.Below in conjunction with read-write sequence figure reading control procedure and write control procedure and describe respectively the read-write state machine respectively.
The read-write state machine write control procedure, as shown in Figure 5, comprise following process:
1, the read-write state machine obtains current state for writing state by control signal (IPIC Control Signals) from the PLB interface module;
2, the PLB interface module is to read-write state machine tranmitting data register signal (Bus2IP_Clk);
3, after 1 clock period, the address date of user logic module is selected module to open address path (AddressBus) to have obtained address date (Bus2IP_Addr[4:0]) from the PLB interface module and give the read-write state machine, after the read-write state machine address acquisition data, to SJA1000 OPADD enable signal (ALE) and address signal (AD), again after 1 clock period, the read-write state machine is exported disable address enable signal (ALE) to SJA1000, and keeps current address signal (AD); Again after 1 clock period, the address date of user logic module selects module to open data path (Data Bus), obtain 8 bit data (Bus2IP_Data[24:31]) from the PLB interface module and give the read-write state machine, after the read-write state machine is received data, to SJA1000 outputting data signals (DATA[7:0]),
Write signal (low level is effective),
Chip selection signal, after 1 clock period, the read-write state organizational security is held current data-signal, and forbids again
Write signal (high level is invalid),
Chip selection signal (high level is invalid), read while write state machine and write answer signal (WR_ACK) to the transmission of PLB interface module by acknowledge signal line (IP2Bus_Ack), after 1 clock period, remove and write answer signal again, the read-write state machine returns idle condition.
The read-write state machine read control procedure, as shown in Figure 6, comprise following process:
1, the read-write state machine is read states by control signal (IPIC Control Signals) from PLB interface module acquisition current state;
2, the PLB bus is to read-write state machine tranmitting data register signal (Bus2IP_Clk);
3, after 1 clock period, the address date of user logic module is selected module to open address path (Address Bus) to have obtained address date (Bus2IP_Addr[4:0]) from the PLB interface module and give the read-write state machine, after the read-write state machine address acquisition data, OPADD enable signal (ALE) and address signal (AD), again after 1 clock period, read-write state machine disable address enable signal (ALE), and keep current address signal (AD); Again after 1 clock period, read-write state machine disable address signal (AD), and output
Read signal (low level is effective),
Chip selection signal (low level is effective), after 2.5 clock period, the read-write state machine obtains data, outputting data signals by data line (DATA[7:0]) from SJA1000; 0.5 after the individual clock period, the read-write state organizational security is held current data-signal, and forbids
Signal (high level is invalid) and
Chip selection signal (high level is invalid), simultaneously, the read-write state machine sends to the PLB interface module by acknowledge signal line (IP2Bus_Ack) and reads answer signal (RD_ACK), again after 1 clock period, answer signal is read in removing, and data keep, and after 0.5 clock period, the read-write state machine switches to idle condition.
It is emphasized that; embodiment described in the utility model is illustrative; rather than it is determinate; therefore the utility model is not limited to the embodiment described in the embodiment; every by those skilled in the art according to other embodiments that the technical solution of the utility model draws, belong to the scope of the utility model protection equally.
Claims (6)
1. SJA1000 interface IP kernel based on the PLB bus, it is characterized in that: comprise PLB interface module, user logic module and interrupt control module, described PLB interface module is connected with the PLB bus with control signal wire by the address/data signal line, and this PLB interface module is connected with user logic module and interrupt control module by the IPIC interface; Be connected by interrupt control signal wire IntrEvent between described user logic module and the interrupt control module and realize the interrupt control function, the user logic module also is connected with the SJA1000 CAN controllers with control signal wire by the address/data signal line; The interrupt control module connects CPU by the Intr2Bus_DevIntr signal.
2. the SJA1000 interface IP kernel based on the PLB bus according to claim 1, it is characterized in that: described PLB interface module, user logic module, interrupt control module are built in the FPGA.
3. the SJA1000 interface IP kernel based on the PLB bus according to claim 2, it is characterized in that: described CPU kind comprises the MicroBlaze soft nucleus CPU, and is built in the FPGA.
4. according to each described SJA1000 interface IP kernel of claim 1 to 3 based on the PLB bus, it is characterized in that: described user logic module selects module to connect and compose by read-write state machine and address date, and the read-write state machine transmits with carrying out bi-directional data between the PLC interface module by IPIC control signal IPIC Control Signals; Described address/data selects module to transmit with carrying out bi-directional data between the PLB interface module by address wire Address Bus, data line Data Bus.
5. the SJA1000 interface IP kernel based on the PLB bus according to claim 4 is characterized in that: the interface module that described PLB interface module carries for the PLB bus.
6. the SJA1000 interface IP kernel based on the PLB bus according to claim 4, it is characterized in that: described user logic module comprises following input signal: from clock signal Bus_2IP_Clk, reset signal Bus2IP_Reset, the address signal Bus2IP_Addr[4:0 of PLB interface module], data-signal Bus2IP_Data[24:31] and from look-at-me INT, the data-signal DATA[7:0 of SJA1000 CAN controllers]; Described user logic module comprises following output signal: look-at-me IP2Bus_IntrEvent, the answer signal IP2Bus_Ack, the data-signal Bus2IP_Data[24:31 that send to the PLB interface module], send to the address/data signal DATA[7:0 of SJA1000 CAN controllers], address enable signal ALE, chip selection signal CS, read-write RD/WR, reset signal RST and the interrupt event signal IntrEvent that sends to the interrupt control module.
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| CN 201320016223 CN203084719U (en) | 2013-01-14 | 2013-01-14 | SJA1000 interface IP core based on processor local bus (PLB) |
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| CN 201320016223 CN203084719U (en) | 2013-01-14 | 2013-01-14 | SJA1000 interface IP core based on processor local bus (PLB) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103218325A (en) * | 2013-01-14 | 2013-07-24 | 无锡普智联科高新技术有限公司 | SJA1000 interface IP (Internet Protocol) core based on PLB (Processor Local Bus) and control method thereof |
| CN105446914A (en) * | 2014-09-02 | 2016-03-30 | 施耐德电器工业公司 | Method and device for generating interruption/event of upper CPU in PLC module |
-
2013
- 2013-01-14 CN CN 201320016223 patent/CN203084719U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103218325A (en) * | 2013-01-14 | 2013-07-24 | 无锡普智联科高新技术有限公司 | SJA1000 interface IP (Internet Protocol) core based on PLB (Processor Local Bus) and control method thereof |
| CN103218325B (en) * | 2013-01-14 | 2016-03-16 | 无锡普智联科高新技术有限公司 | Based on SJA1000 Interface IP Core and the control method thereof of PLB bus |
| CN105446914A (en) * | 2014-09-02 | 2016-03-30 | 施耐德电器工业公司 | Method and device for generating interruption/event of upper CPU in PLC module |
| CN105446914B (en) * | 2014-09-02 | 2018-05-29 | 施耐德电器工业公司 | The method and device to interruption/event of upper bit CPU is generated in PLC module |
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Granted publication date: 20130724 Termination date: 20170114 |
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