CN205692166U - Core board based on PowerPC framework central processing unit - Google Patents
Core board based on PowerPC framework central processing unit Download PDFInfo
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- CN205692166U CN205692166U CN201620558158.5U CN201620558158U CN205692166U CN 205692166 U CN205692166 U CN 205692166U CN 201620558158 U CN201620558158 U CN 201620558158U CN 205692166 U CN205692166 U CN 205692166U
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Abstract
The utility model discloses a kind of core board based on PowerPC framework central processing unit, including central processing unit, field programmable gate array, CPLD, power module, reseting module, clock module, communication unit and memory element；Field programmable gate array is connected with central processing unit, and CPLD is connected with central processing unit, field programmable gate array, power module, reseting module and clock module；Communication unit includes the Gigabit Ethernet module being connected with central processing unit, gigabit ethernet switch and the RS232 transceiver being connected with field programmable gate array, RS422 transceiver, LVTTL buffer；Memory element includes DRAM, eMMC and the SSD being connected with central processing unit.The core board that this utility model provides, integrated level is high, volume is little, Peripheral Interface is abundant, is suitable for being integrated in ownership goal board, shortens the time of product development of designer.
Description
Technical field
This utility model relates to technical field of integrated circuits, is specifically related to a kind of based on PowerPC framework central processing unit
Core board.
Background technology
Core board is the one piece of electronics mainboard encapsulated of the Core Feature of mini PC being packed.During most of core boards are integrated with
Central processor (CPU, Central Processing Unit), storage device and pin, be connected with supporting base plate by pin
Together thus realize the System on Chip/SoC in certain field.On the one hand, owing to core board is integrated with the general utility functions of core, so it
Various different base plate can be customized, substantially increase the development efficiency of single-chip microcomputer；On the other hand, core board is as one piece of independence
Module separate, also reduce development difficulty, add stability and the maintainability of system.
Central processing unit is a most important part in core board.Along with the fast development of embedded technology, science and technology neck
Territory creates numerous CPU architecture and standard, and various central processing unit models continue to bring out especially.Such as, current city
CPU type popular on field includes ARM, Power, DSP, MCU, MIPS etc., and concrete device model is the highest reaches hundred
Thousands of kinds.EBI and the Peripheral Interface of various central processing units the most all vary, and are difficult to find a kind of central authorities to process
Device its peripheral hardware of energy flexible customization, causes in the design of final products, it is difficult to provide all of special with single central processing unit
Interface, it is impossible to realize the maximization of design compatibility.
Utility model content
To be solved in the utility model is that existing core board is difficult to provide all special connect with single central processing unit
Mouthful, the maximized problem of design compatibility can not be realized.
This utility model is achieved through the following technical solutions:
Core board based on PowerPC framework central processing unit, including central processing unit, field programmable gate array, answers
Miscellaneous PLD, power module, reseting module, clock module, communication unit and memory element；Wherein, described existing
Field programmable gate array is connected with described central processing unit by eLBC interface and GPIO interface, described complicated programmable logic device
Part and described central processing unit, described field programmable gate array, described power module, described reseting module and described clock
Module connects；Described communication unit includes that Gigabit Ethernet module, gigabit ethernet switch, RS232 transceiver, RS422 receive
Send out device and LVTTL buffer, described Gigabit Ethernet module and described gigabit ethernet switch by RGM II interface and institute
Stating central processing unit to connect, described RS232 transceiver and described RS422 transceiver are by UART interface and described field-programmable
Gate array connects, and described LVTTL buffer is connected with described field programmable gate array by GPIO interface；Described memory element
Including DRAM, eMMC and SSD, described DRAM connects described central processing unit by Memory Controller Hub, and described eMMC passes through
EMMC bus connects described central processing unit, and described SSD connects described central processing unit by HSSI High-Speed Serial Interface.
The general purpose core core that this utility model provides, has power supply status management and Working Status Monitoring function, supports low
Power consumption and wake operation, and there is SSD, eMMC and DRAM memory device, there is Gigabit Ethernet module and gigabit Ethernet
Switch, draws RS232 transceiver, RS422 transceiver and LVTTL buffer, for central processing unit provide eLBC interface and
GPIO interface is to field programmable gate array.This core board integrated level is high, volume is little, Peripheral Interface is abundant, is suitable for being integrated into
In ownership goal board, shorten the time of product development of designer.
Optionally, described central processing unit is the P2040 processor of Freescale Semiconductor.
Optionally, described field programmable gate array is the XC7K325T chip of company of match SEL.
Optionally, described CPLD is the EPM2210 chip of Altera Corp.
Optionally, described gigabit ethernet switch connects the Gigabit Ethernet module of extension by RGM II interface and adds
Close module.
Optionally, described core board based on PowerPC framework central processing unit also includes with described central processing unit even
The first GPIO interface, the first optical module and the SRIO exchange chip connect.
Optionally, described core board based on PowerPC framework central processing unit also includes and described field programmable gate
Second GPIO interface of array connection and the second optical module.
This utility model compared with prior art, has such advantages as and beneficial effect:
The general purpose core core based on PowerPC framework central processing unit that this utility model provides, using the teaching of the invention it is possible to provide abundant many
The Peripheral Interface of sample, versatility, compatibility are strong, adapt to exploitation and the upgrading of existing product of major part new product, thus contract
The time of product development of short designer, reduces product development cost.Meanwhile, this core board also has that integrated level is high, volume is little
Advantage.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing being further appreciated by this utility model embodiment, constitutes the one of the application
Part, is not intended that the restriction to this utility model embodiment.In the accompanying drawings:
Fig. 1 is the structural representation of the core board based on PowerPC framework central processing unit of this utility model embodiment.
Detailed description of the invention
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with embodiment and accompanying drawing,
The utility model is described in further detail, and exemplary embodiment of the present utility model and explanation thereof are only used for explaining this
Utility model, is not intended as restriction of the present utility model.
Embodiment
Fig. 1 is the structural representation of the general purpose core core of this utility model embodiment, and described general purpose core core includes central authorities
Processor 10, field programmable gate array (FPGA, Field Programming Gate Array) 11, complex programmable logic
Device (CPLD, Complex Programmable Logic Device) 12, power module 131, reseting module 132, clock mould
Block 133, communication unit and memory element.Communication interface between above-described each module is as follows:
In the present embodiment, described central processing unit (CPU, Central Processing Unit) 10 is Freescale
The P2040 processor of semiconductor company.P2040 processor framework based on PowerPC, dominant frequency 1GHz, embedded strengthen logical
Letter processing unit and ciphering unit.The full name of POWER is Performance Optimized With Enhanced RISC, i.e.
Strengthen RISC performance to optimize, be the microprocessor that developed of the AIM alliance being made up of Apple, IBM, Motorola for 1991
Framework, has simple in construction, efficiency is high, retractility is good, a convenient, flexible feature.
Described field programmable gate array 11 is by enhancement mode local bus controller (eLBC, Enhance Local Bus
Controller) interface and universal input output (GPIO, General Purpose Input Output) interface are with described
Central processing unit 10 connects.In the present embodiment, described field programmable gate array 11 is the XC7K325T core of company of match SEL
Sheet, XC7K325T chip is a kind of low-power consumption, high performance fpga chip.FPGA is at programming devices such as PAL, GAL, CPLD
On the basis of the product of further development, it is to occur as a kind of semi-custom circuit in special IC field,
Both solve the deficiency of custom circuit, overcome again the shortcoming that original programming device gate circuit number is limited.Modern FPGA also collects
Become high speed serialization transceiver (Serdes), multiple high-speed serial bus agreement can have been realized.
Described CPLD 12 and described central processing unit 10, described field programmable gate array 11, institute
State power module 131, described reseting module 132 and described clock module 133 to connect.In the present embodiment, described complexity can
Programmed logic device 12 is the EPM2210 chip of Altera Corp.Specifically ,+12V power supply is led to by described power module 131
Crossing DC-DC power module by Power convert is power supply needed for described CPLD 12, and described complex programmable is patrolled
Collect the device 12 monitoring means as system, the power supply of control system, reset and clock.Power supply+3.3V needed for core board,
+ 2.5V ,+1.5V ,+1.2V ,+1.0V are carried out conversion by controlled power module 131 and realize, real by management power module 131
Show core board and the power management of system and the status monitoring of system.Described clock module 133 provides various for device in plate
Clock, this core board use programmable clock chip, board provides multiple frequency, including 100MHz, 50MHz,
The frequencies such as 64MHz, 16.384MHz.Described reseting module 132 provides electrification reset, cold reset, hot reset for device in plate, sees
The management functions that reset such as door Canis familiaris L. reset.
Described communication unit include Gigabit Ethernet module 141, gigabit ethernet switch 142, RS232 transceiver 161,
RS422 transceiver 162 and LVTTL buffer 163.Described Gigabit Ethernet module 141 and described gigabit ethernet switch
142 are connected with described central processing unit 10 by RGM II interface, and gigabit Ethernet is built upon on the ethernet standard of basis
Technology.Gigabit Ethernet and a large amount of Ethernet used are completely compatible with Fast Ethernet, and make use of former ethernet standard institute
Whole technical specifications of regulation, including CSMA/CD agreement, ethernet frame, full duplex, flow-control and IEEE802.3
Management object defined in standard.Gigabit Ethernet ceiling for accumulation speed 1.0Gbps, uses 8B10B coding, at full-duplex mode
Under, the highest transmitted in both directions bandwidth realizing 200MB.In the present embodiment, P2040 chip Shang mono-road RGMII interface is used
Realize gigabit Ethernet, be connected with described Gigabit Ethernet module 141, it is provided that individually data interaction；Use on P2040 chip
Another road RGMII interface is connected with described gigabit ethernet switch 142, it is achieved gigabit Ethernet extends external Ethernet and connects
Mouthful, described gigabit ethernet switch 142 connects Gigabit Ethernet module 143 and the encrypting module of extension by RGM II interface
144.Described encrypting module 144 is by the SRIO embedded system of internal extended, it is achieved data encryption and decryption operation at a high speed.
Data link in system communication processes is it cannot be guaranteed that link data will not be revealed, then ensure the safety of communication data particularly
Important, particularly those sensitive informations, data encryption is exactly the Main Means solving data safety.Described encrypting module 144 is main
Complete the data that will send to be encrypted operation, operation is decrypted for the most encrypted data received.
Described RS232 transceiver 161, described RS422 transceiver 162 and described LVTTL buffer 163 are by general different
Step receiving-transmitting transmitter (UART, Universal Asynchronous Receiver Transmitter) interface and described scene
Programmable gate array 11 connects.RS422 bus and RS232 bus all meet the serial data communication interface standard that EIA formulates, quilt
It is widely used in the occasions such as the connection of computer serial interface peripheral hardware and Industry Control, on-scene communication, telecommunication.RS232 uses
Single-ended level standard, represents data 0 with+3 ~+15V, represents data 1 with-3 ~-15V；RS422 uses differential level standard, thus
Transfer rate is higher, uses four line full duplex transmission modes.In the present embodiment, described RS232 transceiver 161 is with XC7K325T
The internal logic resource of chip realizes 16 road UART, is exported by RS232 level transceiver, by 16.384MHz clock or
100MHz clock realizes baud rate able to programme, adjustable to 1MHz from 4800；Described RS422 transceiver 162 is with XC7K325T core
The internal logic resource of sheet realizes 16 road UART, is exported by RS422 level transceiver, by 16.384MHz clock or
100MHz clock realizes baud rate able to programme, adjustable to 10MHz from 115200；Described LVTTL buffer 163 is with XC7K325T
The internal logic resource of chip realizes 24 road GPIO, and input/output direction, each road can customize, thus realizes multipurpose flexibly
Discrete digital signal line, is exported by the self adaptation bidirectional buffer of LVTTL level.
Described memory element includes dynamic random access memory (DRAM, Dynamic Random Access Memory)
151, embedded multi-media card (eMMC, Embedded Multi Media Card) 152 and solid state hard disc (SSD, Solid
State Drives) 153, described dynamic random access memory 151 connects described central processing unit 10 by Memory Controller Hub,
Described embedded multi-media card 152 connects described central processing unit 10 by eMMC bus, and described solid state hard disc 153 is by a high speed
Serial line interface connects described central processing unit 10.Along with the development of modern bus communication technology, bus communication data transfer rate is increasingly
Height, there is increasing problem in traditional parallel bus, becomes the most at high frequencies to be difficult to align, parallel between multiple signals
Interfering between wire becomes serious etc., causes the data of transmission to become to recover.And universal serial bus is because wire is few,
And use differential voltage to be transmitted, transfer rate can be improved by improving constantly clock frequency, the most common with
The too bus such as net, PCI-E, SATA all uses high-speed serial bus, i.e. can reach the highest data bandwidth with a small amount of cable.Enter
One step, described dynamic random access memory 151 is that Double Data Rate (DDR, Double Data Rate) dynamic randon access is deposited
Reservoir.The hard disk that described solid state hard disc 153 is made with solid-state electronic storage chip array, by control unit and memory element
Composition.In the present embodiment, described solid state hard disc 153 is with single encapsulation chip form, has that volume is little, low in energy consumption, reliability
High feature.
The core board of the present embodiment also includes: first GPIO interface the 171, first light being connected with described central processing unit 10
Module 172 and SRIO exchange chip 173；The second GPIO interface 181 being connected with described field programmable gate array 11 and
Two optical modules 182.It is Serial Rapid I/O interface by configuring the high-speed interface of P2040 chip, it is possible to obtain 2 × 1 tunnels
High-speed communication interface, plug-in SRIO exchange chip 173 can be right to external expansion 2 × 2 road Serial Rapid I/O interface
Interior extension 1 × 2 road Serial Rapid I/O interface.
In sum, the core board that the present embodiment provides has multiple bus interface and Peripheral Interface, is applied to produce
In product design, the different demands of different product can be met, thus realize the maximization of design compatibility, it is ensured that leading to of core board
By property and compatibility, it is allowed to adapt to exploitation and the upgrading of existing product of major part new product, thus shortens the week of product development
Phase, reduce the cost of product development.
Above-described detailed description of the invention, is entered the purpose of this utility model, technical scheme and beneficial effect
One step describes in detail, be it should be understood that and the foregoing is only detailed description of the invention of the present utility model, is not used to limit
Fixed protection domain of the present utility model, all within spirit of the present utility model and principle, any amendment, the equivalent made are replaced
Change, improvement etc., within should be included in protection domain of the present utility model.
Claims (7)
1. a core board based on PowerPC framework central processing unit, it is characterised in that include that central processing unit, scene can
Programming gate array, CPLD, power module, reseting module, clock module, communication unit and storage are single
Unit；Wherein,
Described field programmable gate array is connected with described central processing unit by eLBC interface and GPIO interface, and described complexity can
Programmed logic device and described central processing unit, described field programmable gate array, described power module, described reseting module with
And described clock module connects；
Described communication unit include Gigabit Ethernet module, gigabit ethernet switch, RS232 transceiver, RS422 transceiver with
And LVTTL buffer, described Gigabit Ethernet module and described gigabit ethernet switch are by RGM II interface and described central authorities
Processor connects, and described RS232 transceiver and described RS422 transceiver are by UART interface and described field programmable gate array
Connecting, described LVTTL buffer is connected with described field programmable gate array by GPIO interface；
Described memory element includes DRAM, eMMC and SSD, and described DRAM connects described central authorities by Memory Controller Hub and processes
Device, described eMMC connects described central processing unit by eMMC bus, and described SSD connects described central authorities by HSSI High-Speed Serial Interface
Processor.
Core board based on PowerPC framework central processing unit the most according to claim 1, it is characterised in that in described
Central processor is the P2040 processor of Freescale Semiconductor.
Core board based on PowerPC framework central processing unit the most according to claim 1, it is characterised in that described existing
Field programmable gate array is the XC7K325T chip of company of match SEL.
Core board based on PowerPC framework central processing unit the most according to claim 1, it is characterised in that described multiple
Miscellaneous PLD is the EPM2210 chip of Altera Corp.
Core board based on PowerPC framework central processing unit the most according to claim 1, it is characterised in that described thousand
Mbit ethernet switch connects Gigabit Ethernet module and the encrypting module of extension by RGM II interface.
Core board based on PowerPC framework central processing unit the most according to claim 1, it is characterised in that also include
The first GPIO interface, the first optical module and the SRIO exchange chip being connected with described central processing unit.
Core board based on PowerPC framework central processing unit the most according to claim 1, it is characterised in that also include
The second GPIO interface being connected with described field programmable gate array and the second optical module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620558158.5U CN205692166U (en) | 2016-06-12 | 2016-06-12 | Core board based on PowerPC framework central processing unit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620558158.5U CN205692166U (en) | 2016-06-12 | 2016-06-12 | Core board based on PowerPC framework central processing unit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108108316A (en) * | 2017-12-14 | 2018-06-01 | 上海斐讯数据通信技术有限公司 | A kind of Interface Expanding method and system based on field programmable gate array |
| CN108833242A (en) * | 2018-05-22 | 2018-11-16 | 天津市英贝特航天科技有限公司 | One kind two takes the processing of two secure datas and arbitration device and method |
| CN109240169A (en) * | 2018-10-23 | 2019-01-18 | 深圳市施罗德工业测控设备有限公司 | A kind of power communication car owner plate and power communication vehicle |
| CN109405810A (en) * | 2018-12-20 | 2019-03-01 | 中国海洋大学 | Seabed observation system and method in real time in situ |
| CN113032325A (en) * | 2021-03-09 | 2021-06-25 | 中车青岛四方车辆研究所有限公司 | Processor board card, control method thereof, and storage medium |
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2016
- 2016-06-12 CN CN201620558158.5U patent/CN205692166U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108108316A (en) * | 2017-12-14 | 2018-06-01 | 上海斐讯数据通信技术有限公司 | A kind of Interface Expanding method and system based on field programmable gate array |
| CN108108316B (en) * | 2017-12-14 | 2023-08-11 | 珠海西格电力科技有限公司 | Interface expansion method and system based on field programmable gate array |
| CN108833242A (en) * | 2018-05-22 | 2018-11-16 | 天津市英贝特航天科技有限公司 | One kind two takes the processing of two secure datas and arbitration device and method |
| CN108833242B (en) * | 2018-05-22 | 2021-03-23 | 天津市英贝特航天科技有限公司 | Two-out-of-two safety data processing and arbitration method |
| CN109240169A (en) * | 2018-10-23 | 2019-01-18 | 深圳市施罗德工业测控设备有限公司 | A kind of power communication car owner plate and power communication vehicle |
| CN109405810A (en) * | 2018-12-20 | 2019-03-01 | 中国海洋大学 | Seabed observation system and method in real time in situ |
| CN113032325A (en) * | 2021-03-09 | 2021-06-25 | 中车青岛四方车辆研究所有限公司 | Processor board card, control method thereof, and storage medium |
| CN113032325B (en) * | 2021-03-09 | 2023-01-17 | 中车青岛四方车辆研究所有限公司 | Control method of processor board card and storage medium |
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