CN205692166U - Core board based on PowerPC framework central processing unit - Google Patents
Core board based on PowerPC framework central processing unit Download PDFInfo
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- CN205692166U CN205692166U CN201620558158.5U CN201620558158U CN205692166U CN 205692166 U CN205692166 U CN 205692166U CN 201620558158 U CN201620558158 U CN 201620558158U CN 205692166 U CN205692166 U CN 205692166U
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Abstract
The utility model discloses a kind of core board based on PowerPC framework central processing unit, including central processing unit, field programmable gate array, CPLD, power module, reseting module, clock module, communication unit and memory element；Field programmable gate array is connected with central processing unit, and CPLD is connected with central processing unit, field programmable gate array, power module, reseting module and clock module；Communication unit includes the Gigabit Ethernet module being connected with central processing unit, gigabit ethernet switch and the RS232 transceiver being connected with field programmable gate array, RS422 transceiver, LVTTL buffer；Memory element includes DRAM, eMMC and the SSD being connected with central processing unit.The core board that this utility model provides, integrated level is high, volume is little, Peripheral Interface is abundant, is suitable for being integrated in ownership goal board, shortens the time of product development of designer.
Description
Technical Field
The utility model relates to an integrated circuit technical field, concretely relates to nuclear core plate based on powerPC framework central processing unit.
Background
The core board is an electronic main board which packages and encapsulates the core functions of the mini PC. Most of core boards integrate a Central Processing Unit (CPU), a storage device, and pins, and are connected to a matching base board through the pins, thereby implementing a system chip in a certain field. On one hand, the core board integrates the general functions of the core, so that various different bottom boards can be customized, and the development efficiency of the single chip microcomputer is greatly improved; on the other hand, the core board is separated as an independent module, so that the development difficulty is reduced, and the stability and maintainability of the system are improved.
The central processing unit is one of the most important parts of the core board. With the rapid development of embedded technology, the technology field generates numerous architectures and standards of central processing units, and various models of central processing units are increasingly emerging. For example, the types of central processing units currently on the market include ARM, Power, DSP, MCU, MIPS, etc., and the specific device models are more hundreds or thousands. Bus interfaces and peripheral interfaces of various central processing units are different from each other, and it is difficult to find a central processing unit which can flexibly customize its peripheral, so that it is difficult to provide all special interfaces with a single central processing unit in the design of the final product, and the maximization of design compatibility cannot be realized.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the problem that the current nuclear core plate is difficult to provide all special interfaces with single central processing unit, can not realize the design compatibility maximize.
The utility model discloses a following technical scheme realizes:
the core board based on the PowerPC architecture central processing unit comprises a central processing unit, a field programmable gate array, a complex programmable logic device, a power supply module, a reset module, a clock module, a communication unit and a storage unit; the field programmable gate array is connected with the central processing unit through an eLBC interface and a GPIO interface, and the complex programmable logic device is connected with the central processing unit, the field programmable gate array, the power supply module, the reset module and the clock module; the communication unit comprises a gigabit Ethernet module, a gigabit Ethernet switch, an RS232 transceiver, an RS422 transceiver and an LVTTL buffer, wherein the gigabit Ethernet module and the gigabit Ethernet switch are connected with the central processing unit through an RGMII interface, the RS232 transceiver and the RS422 transceiver are connected with the field programmable gate array through a UART interface, and the LVTTL buffer is connected with the field programmable gate array through a GPIO interface; the storage unit comprises a DRAM, an eMMC and an SSD, the DRAM is connected with the central processing unit through a memory controller, the eMMC is connected with the central processing unit through an eMMC bus, and the SSD is connected with the central processing unit through a high-speed serial interface.
The utility model provides a general nuclear core plate has power state management and operating condition monitor function, supports low-power consumption and awakens up the operation to have SSD, eMMC and DRAM memory device, have gigabit Ethernet module and gigabit Ethernet switch, draw forth RS232 transceiver, RS422 transceiver and LVTTL buffer, provide eLBC interface and GPIO interface to field programmable gate array for central processing unit. The core board has high integration level, small volume and rich peripheral interfaces, is suitable for being integrated into a user target board card, and shortens the product development time of designers.
Optionally, the central processing unit is a P2040 processor of the semiconductor company of freescale.
Optionally, the field programmable gate array is XC7K325T chip from seling corporation.
Optionally, the complex programmable logic device is an EPM2210 chip of altra corporation.
Optionally, the gigabit ethernet switch connects the expanded gigabit ethernet module and the encryption module through an RGM ii interface.
Optionally, the core board based on the PowerPC architecture central processing unit further includes a first GPIO interface connected to the central processing unit, a first optical module, and an SRIO switch chip.
Optionally, the core board based on the PowerPC architecture central processing unit further includes a second GPIO interface and a second optical module connected to the field programmable gate array.
Compared with the prior art, the utility model, following advantage and beneficial effect have:
the utility model provides a general nuclear core plate based on powerPC framework central processing unit can provide abundant various peripheral hardware interface, and commonality, compatibility are strong, can adapt to the development of most new products and the upgrading of original product to shorten designer's product development time, reduce product development cost. Simultaneously, this nuclear core plate still has the advantage that the integrated level is high, small.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a schematic structural diagram of a core board based on a PowerPC architecture cpu according to an embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following examples and drawings, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended as limitations of the present invention.
Examples
Fig. 1 is a schematic structural diagram of a general core board according to an embodiment of the present invention, where the general core board includes a central processing unit 10, a Field Programmable Gate Array (FPGA) 11, a Complex Programmable Logic Device (CPLD) 12, a power module 131, a reset module 132, a clock module 133, a communication unit, and a storage unit. The communication interfaces between the modules are as follows:
in the present embodiment, the Central Processing Unit (CPU) 10 is a P2040 processor from the company of swiekal semiconductor. The P2040 processor is based on a PowerPC (personal computer) architecture, has a main frequency of 1GHz, and is embedded with an enhanced communication processing unit and an encryption unit. Power is called Performance Optimized With Enhanced RISC, namely the Performance optimization of Enhanced RISC, is a microprocessor architecture developed by AIM alliance composed of Apple, IBM and Motorola in 1991, and has the characteristics of simple structure, high efficiency, good flexibility, convenience and flexibility.
The field programmable gate array 11 is connected to the central processing unit 10 through an enhanced Local bus controller (ebbc) interface and a General Purpose Input/Output (GPIO) interface. In this embodiment, the field programmable gate array 11 is an XC7K325T chip of saint corporation, and the XC7K325T chip is an FPGA chip with low power consumption and high performance. The FPGA is a product developed further on the basis of programmable devices such as PAL, GAL, CPLD and the like, and appears as a semi-custom circuit in the field of application-specific integrated circuits, thereby not only solving the defects of the custom circuit, but also overcoming the defect of limited gate circuit number of the original programmable device. Modern FPGAs also integrate high-speed serial transceivers (Serdes), which can implement multiple high-speed serial bus protocols.
The complex programmable logic device 12 is connected to the central processing unit 10, the field programmable gate array 11, the power module 131, the reset module 132, and the clock module 133. In the present embodiment, the complex programmable logic device 12 is an EPM2210 chip of altra. Specifically, the power module 131 converts the +12V power into the power required by the complex programmable logic device 12 through the DC-DC power module, and the complex programmable logic device 12 is used as a monitoring unit of the system to control the power, the reset and the clock of the system. The +3.3V, +2.5V, +1.5V, +1.2V, +1.0V that the core board needs are realized by the conversion of controlled power module 131, realize the power management of core board and system and the state monitoring of system through managing power module 131. The clock module 133 provides various clocks for the devices in the board, and the core board uses a programmable clock chip to provide a plurality of frequency points including 100MHz, 50MHz, 64MHz, 16.384MHz and the like in the board. The reset module 132 provides reset management functions such as power-on reset, cold reset, hot reset, watchdog reset, etc. for the in-board devices.
The communication unit includes a gigabit ethernet module 141, a gigabit ethernet switch 142, an RS232 transceiver 161, an RS422 transceiver 162, and an LVTTL buffer 163. The gigabit ethernet module 141 and the gigabit ethernet switch 142 are connected to the central processing unit 10 via an rgmbi interface, and gigabit ethernet is a technology based on the basic ethernet standard. Gigabit ethernet and the heavily used ethernet are fully compatible with fast ethernet and utilize all specifications specified by the original ethernet standard, including CSMA/CD protocol, ethernet frames, full duplex, flow control, and management objects defined in the IEEE802.3 standard. The maximum line rate of the gigabit Ethernet is 1.0Gbps, 8B10B coding is adopted, and the maximum bidirectional transmission bandwidth of 200MB can be realized in a full duplex mode. In this embodiment, one RGMII interface on the P2040 chip is used to implement a gigabit ethernet, and is connected to the gigabit ethernet module 141 to provide independent data interaction; and the other path of RGMII interface on the P2040 chip is connected to the gigabit ethernet switch 142 to implement an external ethernet interface for gigabit ethernet expansion, and the gigabit ethernet switch 142 is connected to the expanded gigabit ethernet module 143 and the encryption module 144 through an rgmbi interface. The encryption module 144 is embedded in the system through an internally extended SRIO, so as to implement high-speed data encryption and decryption operations. Data link in the system communication process can not ensure that link data can not be leaked, so that the security of communication data is guaranteed to be particularly important, and especially for sensitive information, data encryption is a main means for solving data security. The encryption module 144 mainly performs an encryption operation on data to be transmitted and a decryption operation on received encrypted data.
The RS232 transceiver 161, the RS422 transceiver 162 and the LVTTL buffer 163 are connected to the field programmable gate array 11 through a Universal Asynchronous Receiver Transmitter (UART) interface. The RS422 bus and the RS232 bus both conform to the serial data communication interface standard formulated by EIA, and are widely used for the occasions of computer serial interface peripheral connection, industrial control, field communication, remote communication and the like. RS232 adopts a single-ended level standard, data 0 is represented by +3 to +15V, and data 1 is represented by-3 to-15V; the RS422 adopts a differential level standard, so that the transmission rate is higher, and a four-wire full duplex transmission mode is used. In this embodiment, the RS232 transceiver 161 uses the internal logic resource of the XC7K325T chip to implement 16-way UART, and the programmable baud rate is implemented by using a 16.384MHz clock or a 100MHz clock through the output of the RS232 level transceiver, and is adjustable from 4800 to 1 MHz; the RS422 transceiver 162 realizes 16 paths of UARTs by using internal logic resources of an XC7K325T chip, realizes programmable baud rate by using an RS422 level transceiver output and a 16.384MHz clock or a 100MHz clock, and is adjustable from 115200 to 10 MHz; the LVTTL buffer 163 uses the internal logic resources of the XC7K325T chip to implement 24 GPIOs, and each input/output direction can be customized, thereby implementing a flexible multi-purpose discrete digital signal line, which is output through the adaptive bidirectional buffer of the LVTTL level.
The Memory unit includes a Dynamic Random Access Memory (DRAM) 151, an Embedded multimedia Card (eMMC) 152, and a Solid State Disk (SSD) 153, the Dynamic Random Access Memory 151 is connected to the central processing unit 10 through a Memory controller, the Embedded multimedia Card 152 is connected to the central processing unit 10 through an eMMC bus, and the solid state disk 153 is connected to the central processing unit 10 through a high-speed serial interface. With the development of modern bus communication technology, the data rate of bus communication is higher and higher, and more problems occur in the conventional parallel bus, for example, multiple signals become difficult to align at high frequency, mutual interference between parallel wires becomes serious, and the like, so that the transmitted data becomes unrecoverable. The serial bus has few wires and adopts differential voltage for transmission, and can improve the transmission rate by continuously increasing the clock frequency, for example, common buses such as ethernet, PCI-E, SATA and the like all adopt high-speed serial buses, and a very high data bandwidth can be achieved by a small number of cables. Further, the dram 151 is a Double Data Rate (DDR) dram. The solid state disk 153 is a hard disk made of a solid state electronic memory chip array, and is composed of a control unit and a storage unit. In this embodiment, the solid state disk 153 is in the form of a single packaged chip, and has the characteristics of small volume, low power consumption and high reliability.
The core board of this embodiment further includes: a first GPIO interface 171, a first optical module 172, and an SRIO switch chip 173 connected to the central processor 10; and the second GPIO interface 181 is connected to the field programmable gate array 11, and the second optical module 182 is connected to the field programmable gate array 11. By configuring the high-speed interface of the P2040 chip as a Serial Rapid I/O interface, a 2 × 1-way high-speed communication interface can be obtained, and the external SRIO switch chip 173 can externally extend 2 × 2-way Serial Rapid I/O interfaces and internally extend 1 × 2-way Serial Rapid I/O interfaces.
In summary, the core board provided in this embodiment has a plurality of bus interfaces and peripheral interfaces, and when the core board is applied to product design, different requirements of different products can be met, so that maximization of design compatibility is achieved, the universality and compatibility of the core board are ensured, and the core board is adapted to development of most new products and upgrade of original products, so that the product development period is shortened, and the product development cost is reduced.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A core board based on a PowerPC architecture central processing unit is characterized by comprising a central processing unit, a field programmable gate array, a complex programmable logic device, a power supply module, a reset module, a clock module, a communication unit and a storage unit; wherein,
the field programmable gate array is connected with the central processing unit through an eLBC interface and a GPIO interface, and the complex programmable logic device is connected with the central processing unit, the field programmable gate array, the power supply module, the reset module and the clock module;
the communication unit comprises a gigabit Ethernet module, a gigabit Ethernet switch, an RS232 transceiver, an RS422 transceiver and an LVTTL buffer, wherein the gigabit Ethernet module and the gigabit Ethernet switch are connected with the central processing unit through an RGMII interface, the RS232 transceiver and the RS422 transceiver are connected with the field programmable gate array through a UART interface, and the LVTTL buffer is connected with the field programmable gate array through a GPIO interface;
the storage unit comprises a DRAM, an eMMC and an SSD, the DRAM is connected with the central processing unit through a memory controller, the eMMC is connected with the central processing unit through an eMMC bus, and the SSD is connected with the central processing unit through a high-speed serial interface.
2. The PowerPC architecture cpu-based core board of claim 1, wherein the cpu is a ciscarl semiconductor P2040 processor.
3. The PowerPC architecture cpu-based core board of claim 1, wherein the field programmable gate array is a sailing XC7K325T chip.
4. The PowerPC architecture cpu-based core board of claim 1, wherein the complex programmable logic device is an altra EPM2210 chip.
5. The PowerPC architecture cpu-based core board of claim 1, wherein the gigabit ethernet switch is configured to connect the extended gigabit ethernet module and the encryption module via an RGM ii interface.
6. The PowerPC architecture central processing unit-based core board of claim 1, further comprising a first GPIO interface, a first optical module and an SRIO switch chip connected to the central processing unit.
7. The PowerPC architecture central processing unit-based core board of claim 1, further comprising a second GPIO interface and a second optical module connected to the field programmable gate array.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108108316A (en) * | 2017-12-14 | 2018-06-01 | 上海斐讯数据通信技术有限公司 | A kind of Interface Expanding method and system based on field programmable gate array |
| CN108833242A (en) * | 2018-05-22 | 2018-11-16 | 天津市英贝特航天科技有限公司 | One kind two takes the processing of two secure datas and arbitration device and method |
| CN109240169A (en) * | 2018-10-23 | 2019-01-18 | 深圳市施罗德工业测控设备有限公司 | A kind of power communication car owner plate and power communication vehicle |
| CN109405810A (en) * | 2018-12-20 | 2019-03-01 | 中国海洋大学 | Seabed observation system and method in real time in situ |
| CN113032325A (en) * | 2021-03-09 | 2021-06-25 | 中车青岛四方车辆研究所有限公司 | Processor board card, control method thereof, and storage medium |
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2016
- 2016-06-12 CN CN201620558158.5U patent/CN205692166U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108108316A (en) * | 2017-12-14 | 2018-06-01 | 上海斐讯数据通信技术有限公司 | A kind of Interface Expanding method and system based on field programmable gate array |
| CN108108316B (en) * | 2017-12-14 | 2023-08-11 | 珠海西格电力科技有限公司 | Interface expansion method and system based on field programmable gate array |
| CN108833242A (en) * | 2018-05-22 | 2018-11-16 | 天津市英贝特航天科技有限公司 | One kind two takes the processing of two secure datas and arbitration device and method |
| CN108833242B (en) * | 2018-05-22 | 2021-03-23 | 天津市英贝特航天科技有限公司 | Two-out-of-two safety data processing and arbitration method |
| CN109240169A (en) * | 2018-10-23 | 2019-01-18 | 深圳市施罗德工业测控设备有限公司 | A kind of power communication car owner plate and power communication vehicle |
| CN109405810A (en) * | 2018-12-20 | 2019-03-01 | 中国海洋大学 | Seabed observation system and method in real time in situ |
| CN113032325A (en) * | 2021-03-09 | 2021-06-25 | 中车青岛四方车辆研究所有限公司 | Processor board card, control method thereof, and storage medium |
| CN113032325B (en) * | 2021-03-09 | 2023-01-17 | 中车青岛四方车辆研究所有限公司 | Control method of processor board card and storage medium |
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