CN108108316A - A kind of Interface Expanding method and system based on field programmable gate array - Google Patents
A kind of Interface Expanding method and system based on field programmable gate array Download PDFInfo
- Publication number
- CN108108316A CN108108316A CN201711339980.8A CN201711339980A CN108108316A CN 108108316 A CN108108316 A CN 108108316A CN 201711339980 A CN201711339980 A CN 201711339980A CN 108108316 A CN108108316 A CN 108108316A
- Authority
- CN
- China
- Prior art keywords
- data
- interface
- escape
- data message
- target terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention provides a kind of Interface Expanding method and system based on field programmable gate array, field programmable gate array (i.e. FPGA) is connected by first kind interface with central processing unit (i.e. CPU), it is connected by the second class interface with target terminal, the second class interface has several, different target terminals corresponds to the second different class interfaces, further includes：The data sent by CPU described in the first kind interface, obtain the first data message；First data message is parsed, obtains the first initial data that the CPU issues the corresponding target terminal of first data message；First initial data is issued by the corresponding target terminal of first data message by the second class interface.The present invention realizes Interface Expanding by FPGA so that single CPU can control the module for supporting multiple and different interface protocols by a kind of data-interface, reduce cost, and software adjustment is more flexible.
Description
Technical field
The present invention relates to Interface Expanding field, espespecially a kind of Interface Expanding method based on field programmable gate array and it is
System.
Background technology
In product of the research and development for scenes of internet of things, central processing unit (Central Processing Unit, CPU)
Need by serial ports or Serial Peripheral Interface (SPI) (Serial Peripheral Interface, SPI) etc. and Internet of Things module into
Row communication, but a product may need to connect multiple Internet of Things modules, one piece of CPU may can not meet multiple Internet of Things modules
Interface quantity requirement.
Usually when cpu i/f number is inadequate, the more CPU of one piece of interface quantity can be changed or use multiple CPU,
So product cost can improve, while the difficulty that hardware stacks can also increase.
The content of the invention
The purpose of the present invention is a kind of Interface Expanding method and system based on field programmable gate array, can by scene
It programs gate array and realizes Interface Expanding so that single CPU can be controlled by a kind of data-interface and be supported multiple and different interface protocols
Module, reduce cost, while software adjustment is more flexible.
Technical solution provided by the invention is as follows：
A kind of Interface Expanding method based on field programmable gate array, including：Field programmable gate array passes through first
Class interface is connected with central processing unit, is connected by the second class interface with target terminal, the second class interface has several, no
Same target terminal corresponds to the second different class interfaces, further includes：Step S100 is by described in the first kind interface
The data that central processor is sent, obtain the first data message；Step S200 parses first data message, obtains institute
State the first initial data of the corresponding target terminal of the first data message；Step S300 is by the second class interface by institute
It states the first initial data and issues the corresponding target terminal of first data message.
In the above-mentioned technical solutions, field programmable gate array, i.e. FPGA (Field Programming Gate
Array), Interface Expanding is realized by FPGA so that single CPU can be controlled by a kind of data-interface and be supported multiple and different interfaces
The module of agreement, reduces cost；It, can flexible expansion interface, increase and newly-increased target terminal by updating FPGA softwares
Interaction.
Further, first data message includes：Data after packet header mark, address information and the first escape, it is described
Step S200 is specifically included：Step S210 finds the packet header mark in first data message；Step S220 is when in institute
It states when packet header mark is found in the first data message, obtains described address information and corresponding target terminal；Step S230
When finding the packet header mark in first data message, it is whole to obtain the corresponding target of first data message
Data after first escape at end；Step S240 inverts the data after first escape according to default escape rule
Justice obtains first initial data.
In the above-mentioned technical solutions, a kind of method for obtaining the first initial data is provided, after to the first escape
Data carry out reversion justice, so as to accurately obtain the first initial data that central processing unit is sent.
Further, further include：The data that step S400 is sent by target terminal described in the second class interface obtain the
Two initial data；Step S500 assembles second initial data, obtains the second data message；Step S600 passes through institute
It states first kind interface and second data message is issued into the central processing unit.
In the above-mentioned technical solutions, the interactive interfacing mistake of up direction (from target terminal to FPGA, then to CPU) is given
Journey, perfect entire scheme.
Further, the step S500 is specifically included：Step S510 is included when second initial data by escape character
When, escape is carried out according to default escape rule by escape character by described, obtains the data after the second escape；Step S520 exists
Plus packet header mark and address information before data after second escape, according to the central processing unit and field programmable gate
Interface format between array is assembled into second data message.
In the above-mentioned technical solutions, a kind of method for obtaining the second data message is provided, by the second initial data
Escape is carried out, packet header mark is avoided and is analysed with the misunderstanding of original data content recipient when identical.
Further, the packet header is identified as a character；Default escape rule is：There are two by escape character,
In, with packet header it is sensible with character for first by escape character, second by escape character is preset characters, and described second is turned
Adopted character is different by escape character from described first；One byte group for being obtained being made of two characters after escape character escape
It closes, wherein, the first character in the combination of bytes is fixed as second by escape character, second in the combination of bytes
Character is calculated according to described by escape character and preset function operational formula.
In the above-mentioned technical solutions, a kind of escape rule is provided.
Further, the step S600 is specifically included：Step S610 caches second data message；Step S620 is when slow
It is excellent according to the priority of the target terminal when having second data message of no less than one target terminal in depositing
Second data message of the high target terminal of priority is first sent to the central processing unit.
In the above-mentioned technical solutions, issue CPU for the second data message and increased a kind of transmission scheme newly, can preferentially protect
Demonstrate,prove the data sending of the high target terminal of priority.
The present invention also provides a kind of field programmable gate array, including：Field programmable gate array passes through first kind interface
It is connected with central processing unit, is connected by the second class interface with target terminal, the second class interface there are several, different mesh
Mark terminal-pair answers the second different class interfaces；The field programmable gate array includes：Second receiving module, it is described for passing through
The data that central processing unit described in first kind interface is sent, obtain the first data message；Parsing module connects with described second
Module electrical connection is received, for parsing first data message, obtains the corresponding target terminal of first data message
The first initial data；Second sending module is electrically connected with the parsing module, described in being incited somebody to action by the second class interface
First initial data issues the corresponding target terminal of first data message.
In the above-mentioned technical solutions, Interface Expanding is realized by FPGA so that single CPU can be controlled by a kind of data-interface
System supports the module of multiple and different interface protocols, reduces cost；By updating FPGA softwares, can flexible expansion interface,
Increase the interaction with newly-increased target terminal.
Further, first data message includes：Data after packet header mark, address information and the first escape；It is described
Parsing module is further used for finding the packet header mark in first data message；And when in first data
When the packet header mark is found in information, described address information and corresponding target terminal are obtained；And when in the described first number
It is believed that when the packet header mark is found in breath, after obtaining the first escape of the corresponding target terminal of first data message
Data；And the data after first escape are subjected to reversion justice according to default escape rule, it is former to obtain described first
Beginning data.
In the above-mentioned technical solutions, a kind of method for obtaining the first initial data is provided, after to the first escape
Data carry out reversion justice, so as to accurately obtain the first initial data that central processing unit is sent.
Further, second receiving module is further used for sending by target terminal described in the second class interface
Data, obtain the second initial data that the target terminal issues the central processing unit；The parsing module, is further used
It is assembled in second initial data, obtains the second data message；Second sending module, is further used for passing through
Second data message is issued the central processing unit by the first kind interface.
In the above-mentioned technical solutions, the interactive interfacing mistake of up direction (from target terminal to FPGA, then to CPU) is given
Journey, perfect entire scheme.
The present invention also provides a kind of Interface Expanding system based on field programmable gate array, including：Foregoing scene can
Program gate array；It further includes：Central processing unit, several target terminals；The central processing unit, with the field programmable gate
Array is electrically connected；Each target terminal, is electrically connected with the field programmable gate array；The central processing unit includes：
First sending module, for sending first data message to the field-programmable gate array by the first kind interface
Row；First receiving module, for passing through second data of the first kind interface from field programmable gate array
Information；Each target terminal includes：3rd sending module, it is original for sending described second by the second class interface
Data give the field programmable gate array；3rd receiving module, it is described existing for being come from by the second class interface
First initial data of field programmable gate array.
In the above-mentioned technical solutions, connecing for single CPU and several target terminals is realized by field programmable gate array
Oral sex is mutual, extends the interface of single CPU, reduces cost.
By a kind of Interface Expanding method and system based on field programmable gate array provided by the invention, can bring
Following advantageous effect：
The present invention realizes Interface Expanding by FPGA so that single CPU can control support multiple by a kind of data-interface
The module of distinct interface agreement, reduces cost；By updating FPGA softwares, can flexible expansion interface, increase and newly-increased
The interaction of target terminal.
Description of the drawings
Below by a manner of clearly understandable, preferred embodiment is described with reference to the drawings, field-programmable is based on to one kind
Above-mentioned characteristic, technical characteristic, advantage and its realization method of the Interface Expanding method and system of gate array are further described.
Fig. 1 is a kind of flow of one embodiment of Interface Expanding method based on field programmable gate array of the present invention
Figure；
Fig. 2 is a kind of stream of another embodiment of Interface Expanding method based on field programmable gate array of the present invention
Cheng Tu；
Fig. 3 a are a kind of another embodiments of Interface Expanding method based on field programmable gate array of the present invention
Flow chart；
Fig. 3 b are a kind of another embodiments of Interface Expanding method based on field programmable gate array of the present invention
Partial process view；
Fig. 4 is a kind of structure diagram of one embodiment of field programmable gate array of the present invention；
Fig. 5 is a kind of structure diagram of another embodiment of field programmable gate array of the present invention；
Fig. 6 is a kind of structure of one embodiment of Interface Expanding system based on field programmable gate array of the present invention
Schematic diagram；
Fig. 7 is a kind of FPGA of one embodiment of Interface Expanding method based on field programmable gate array of the present invention
Interface diagram between CPU；
Fig. 8 is the first of one embodiment of a kind of Interface Expanding system based on field programmable gate array of the present invention
The schematic diagram of class interface, the second class interface.
Drawing reference numeral explanation：
100. central processing unit, 200. field programmable gate arrays, 300. target terminals, 110. first sending modules,
120. the first receiving module, 210. second sending modules, 220. second receiving modules, 230. parsing modules, 240. cache modules,
310. the 3rd sending modules, 320. the 3rd receiving modules, 1. first kind interfaces, 2. second class interfaces.
Specific embodiment
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, control is illustrated below
The specific embodiment of the present invention.It should be evident that the accompanying drawings in the following description is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing, and obtain other embodiments.
To make simplified form, part related to the present invention is only schematically shown in each figure, they are not represented
Its practical structures as product.In addition, so that simplified form readily appreciates, there is identical structure or function in some figures
Component only symbolically depicts one of those or has only marked one of those.Herein, "one" is not only represented
" only this " can also represent the situation of " more than one ".
In one embodiment of the invention, as shown in Figure 1, a kind of Interface Expanding side based on field programmable gate array
Method, applied to field programmable gate array, the field programmable gate array is connected by first kind interface with central processing unit,
It is connected by the second class interface with target terminal, the second class interface there are several, and different target terminals corresponds to different
Second class interface；It further includes：
The data that step S100 is sent by central processing unit described in the first kind interface obtain the first data letter
Breath；
Step S200 parses first data message, obtains the corresponding target of first data message
First initial data of terminal；
First initial data is issued first data message by the second class interface and corresponded to by step S300
The target terminal.
Specifically, field programmable gate array, i.e. FPGA (Field Programming GateArray)；Central processing
Device, i.e. CPU (Central Processing Unit).First kind interface refers to the interface between FPGA and CPU, and FPGA passes through
First kind interface is connected with CPU, which may be only comprising an interface, and CPU, which sends message and receives message, all to be led to
Cross same interface；The first kind interface may also include two interfaces, and a hair interface sends message for CPU, a receipts connect
For mouth for receiving the message of CPU transmissions, the two is mutual indepedent.
Second class interface refers to that the interface between FPGA and each target terminal, such as FPGA are connected with 3 target terminals,
FPGA and first aim terminal, FPGA and second target terminal, the interface of FPGA and the 3rd target terminal belong to the
Two class interfaces.Different target terminals corresponds to the second different class interfaces, for example, connecing between FPGA and first aim terminal
The interface between interface, FPGA and the 3rd target terminal between mouth, FPGA and second target terminal is independent from each other,
Walk different passages.All target terminals being connected with FPGA, the interface protocol followed may be all identical, it is also possible to part
It is identical, it is also possible to entirely different.The second class interface include GPIO mouthfuls, serial ports, pcm interface, I2C interface, SPI interface.
FPGA softwares need the interface protocol followed according to the quantity and each module of connected target terminal to design；Second class
The traffic rate of interface can also be configured according to the rate that target terminal is supported.
The data that FPGA is sent by first kind interface CPU are assisted by the physical interface followed between CPU-FPGA
View is received, for example is serial ports between CPU-FPGA, is just received by serial ports agreement, is obtained the user data of CPU transmissions, i.e., and the
One data message.There are many forms of first data message, for example, packet header mark+target terminal number+data type+original
Data, it is necessary to by agreement interface format, the first data message is parsed, obtains initial data, be CPU issue first
The first initial data of the target terminal of target terminal number is corresponded in data message；It is connect by the second class interface, such as SPI
First initial data is issued the target terminal of corresponding target terminal number by SPI interface protocol conventions by mouth.
In another embodiment of the present invention, as shown in Fig. 2, a kind of Interface Expanding based on field programmable gate array
Method, applied to field programmable gate array, the field programmable gate array passes through first kind interface and central processing unit phase
Even, it is connected by the second class interface with target terminal, the second class interface there are several, and different target terminals corresponds to different
The second class interface；It further includes：
The data that step S100 is sent by central processing unit described in the first kind interface obtain the first data letter
Breath；
Step S200 parses first data message, obtains the corresponding target of first data message
First initial data of terminal；
First initial data is issued first data message by the second class interface and corresponded to by step S300
The target terminal；
The data that step S400 is sent by target terminal described in the second class interface, obtain the second initial data；
Step S500 assembles second initial data, obtains the second data message；
Second data message is issued the central processing unit by step S600 by the first kind interface.
Specifically, compared with previous embodiment, up direction, i.e. connecing from target terminal → FPGA → CPU are added
Mouth interaction flow.FPGA, according to the interface protocol between FPGA- target terminals, receives target terminal hair by the second class interface
The data sent obtain the second initial data；Second initial data is issued CPU by FPGA, before this, it is necessary to first press CPU-
The interface protocol of FPGA assembles the second initial data, obtains the second data message；Assuming that the second data of CPU-FPGA
The form of information is packet header mark+target terminal number+data type+initial data, then needs to add before the second initial data
Upper packet header mark+target terminal number+data type forms the second data message；FPGA is again by first kind interface by described in
Second data message issues CPU.
In another embodiment of the present invention, as shown in Figure 3a, 3b, a kind of connecing based on field programmable gate array
Mouth extended method, applied to field programmable gate array, the field programmable gate array passes through first kind interface and centre
Reason device is connected, and is connected by the second class interface with target terminal, the second class interface has several, different target terminals pair
Answer the second different class interfaces；It further includes：
The data that step S100 is sent by central processing unit described in the first kind interface obtain the first data letter
Breath；
First data message includes：Data after packet header mark, address information and the first escape；
Step S210 finds the packet header mark in first data message；
Step S220 obtains described address information and right when finding packet header mark in first data message
The target terminal answered；
Step S230 obtains first data message when finding the packet header mark in first data message
Data after first escape of the corresponding target terminal；
Data after first escape are carried out reversion justice by step S240 according to default escape rule, obtain described the
One initial data；
The step S240 is specifically included：
Step S241 travels through the content of each byte in the data after first escape, judges whether at least one
First byte；
First byte is the byte content byte identical with the first escape character；
Step S242 is when there are during at least one first byte, according to existing first byte, obtaining each institute
State the corresponding combination of bytes of the first byte；
Each combination of bytes includes：The content of one first byte and first byte are corresponding next
The content of byte；
Step S243 obtains each combination of bytes and each corresponds to according to default escape rule and each combination of bytes
By escape character；
All combination of bytes in data after first escape are replaced with corresponding described turned by step S244
Adopted character obtains the first initial data of the corresponding target terminal of first data message；
First initial data is issued first data message by the second class interface and corresponded to by step S300
The target terminal；
The data that step S400 is sent by target terminal described in the second class interface, obtain the second initial data；
Step S510 when second initial data include by escape character when, by it is described by escape character according to default
Escape rule carries out escape, obtains the data after the second escape；
Plus packet header mark and address information before data of the step S520 after second escape, according to the centre
The interface format between device and field programmable gate array is managed, is assembled into second data message；
The packet header is identified as a character；
Default escape rule is：
There are two by escape character, wherein, turned with the sensible same character of packet header for first by escape character, second
Adopted character is preset characters, and described second is different by escape character from described first by escape character；
One is obtained the combination of bytes being made of two characters after escape character escape, wherein, in the combination of bytes
First character be fixed as second by escape character, second character in the combination of bytes is according to described by escape character
It is calculated with preset function operational formula；
Step S610 caches second data message；
Step S620 is when there is second data message of no less than one target terminal in caching, according to described
The priority of target terminal, preferential second data message for sending the high target terminal of priority is to the centre
Manage device.
Specifically, compared with previous embodiment, with step S210-S240 alternative steps S200, with step S241-S244
Step S240 is refined, with step S510-S520 alternative steps S500, step S610-S620 alternative steps S600.Fig. 3 a are described
The adopted process of reversion is described in detail in whole flow process, Fig. 3 b.
In order to avoid occur in initial data with packet header it is sensible with byte when, receiving terminal to the misunderstanding of receive information,
Transmitting terminal has carried out escape to original data content；FPGA by the second initial data of target terminal when being sent to CPU, traversal
Second raw data packets, when second initial data is included by escape character, by it is described by escape character according to default
Escape rule carry out escape, obtain the data after the second escape；On this basis, in addition packet header mark and address information, are pressed
According to the interface format between CPU and FPGA, second data message is assembled into；Similarly FPGA is right when receiving the data of CPU
Justice is unpacked and inverted to the first data message received, so as to obtain the first initial data.It is assumed that connecing between CPU-FPGA
Mouthful form is：Data content after packet header mark+address information+escape, as shown in fig. 7, wherein 0x7E identifies for packet header, Addr
A byte is accounted for, meaning is as shown in the table：
| Addr | Function |
| 0x0 | Send data to target terminal 0 |
| 0x1 | Send data to target terminal 1 |
| 0x2 | Send data to target terminal 2 |
| 0x3 | Receive the data of target terminal 0 |
| 0x4 | Receive the data of target terminal 1 |
| 0x5 | Receive the data of target terminal 2 |
Escape rule is as follows：
Wherein, be 0x7E and 0x7D by escape character, wherein 0x7E for first by escape character, it is sensible same with packet header,
0x7D is for second by escape character；One is obtained the combination of bytes being made of two characters, wherein word after escape character escape
First character in section combination is 0x7D, i.e., second by escape character, and second character in combination of bytes is according to default letter
Number operational formula is calculated, for example, above table is according to formulaIt is calculated,Represent exclusive or behaviour
Make, as x=0x7E, obtain second character after escape as 0x5E；As x=0x7D, second word after escape is obtained
It accords with as 0x5D.Preset function operational formula can also be other functional forms, for example,It the above is only one kind
Embodiment.
Assuming that the first data message that CPU is sent to target terminal 0 is：0x7E、0x0、0x1、0x7D、0x5E、0x2、
0x7D、0x5D、0x7D、0x5E、0x5E；FPGA receive CPU transmission first data message when, to the first data message into
Row parsing, the 1st byte 0x7E identify for packet header, and 0x0 Addr show to be intended for the data of target terminal 0；After Addr
Data are the data after the first escape, are 0x1,0x7D, 0x5E, 0x2,0x7D, 0x5D, 0x7D, 0x5E, 0x5E；Traversal the
The content of each byte, judges whether at least one first byte in data after one escape；The first byte herein is
The byte for being 0x7D for byte content judges that the data after the first escape whether there is escape character 0x7D；If it is present
Reversion justice is carried out by default escape rule, i.e. 0x7D5E, which is corresponded to, to be corresponded to by escape character 0x7E, 0x7D5D by escape character
0x7D；In this example, after reversion justice, 0x1,0x7E, 0x2,0x7D, 0x7E, 0x5E are obtained, is the first initial data.Such as
When escape character 0x7D being not present in the data after the first escape of fruit, the data after the first escape are the first initial data.Such as
There are escape character 0x7D in data after the first escape of fruit, but the corresponding combination of bytes of the first byte neither 0x7D5E,
When not being 0x7D5D, then illustrate in transmission process that there may be mistakes, this first data message to abandon.
FPGA to CPU send target terminal 0 the second initial data when, it is assumed that the second initial data for 0x1,0x7E,
0x2,0x7D, 0x7E, 0x5E are, it is necessary to check that the second initial data whether there is by escape character 0x7E or 0x7D；If it does,
Escape then is carried out by default escape rule, i.e. 0x7E corresponds to 0x7D5E, and 0x7D corresponds to 0x7D5D, after escape, obtains the
Data after two escapes, i.e. 0x1,0x7D, 0x5E, 0x2,0x7D, 0x5D, 0x7D, 0x5E, 0x5E.By the number after the second escape
According to, in addition packet header identifies 0x7E and determines Addr according to target terminal as 0x3, in addition Addr, obtains the second data message,
That is 0x7E, 0x3,0x1,0x7D, 0x5E, 0x2,0x7D, 0x5D, 0x7D, 0x5E, 0x5E.
There may be multiple target terminals to send data to FPGA simultaneously, FPGA is received and cached successively；When FPGA is sent out to CPU
When sending, preferential the second data message for sending the high target terminal of priority is to CPU.
In another embodiment of the present invention, as shown in figure 4, a kind of field programmable gate array 200 includes：
Field programmable gate array 200 is connected by first kind interface 1 with central processing unit 100, passes through the second class interface 2
It is connected with target terminal 300, the second class interface 2 there are several, and different target terminals 300 corresponds to the second different classes and connects
Mouth 2；
The field programmable gate array 200 includes：
Second receiving module 220, for receiving the number of the transmission of central processing unit 100 by the first kind interface 1
According to obtaining the first data message；
Parsing module 230 is electrically connected with second receiving module 220, for parsing first data message, is obtained
The central processing unit 100 issues the first initial data of the corresponding target terminal 300 of first data message；
Second sending module 210 is electrically connected with the parsing module 230, described in being incited somebody to action by the second class interface 2
First initial data issues the corresponding target terminal 300 of first data message.
Specifically, field programmable gate array 200, i.e. FPGA (Field Programming GateArray)；Centre
Manage device 100, i.e. CPU (Central Processing Unit).First kind interface 1 refers to the interface between FPGA and CPU,
FPGA is connected by first kind interface 1 with CPU, which may be only comprising an interface, and CPU sends message with receiving
Message all passes through same interface；The first kind interface may also include two interfaces, one hair interface for CPU send message,
One is received the message that interface is used to receive CPU transmissions, and the two is mutual indepedent.
Second class interface 2 refers to the interface between FPGA and each target terminal, such as FPGA and 3 target terminal phases
Even, FPGA and the interface of first aim terminal, FPGA and second target terminal, FPGA and the 3rd target terminal belong to
Second class interface 2.Different target terminals 300 corresponds to the second different class interfaces 2, for example, FPGA and first aim terminal
Between interface, the interface between FPGA and second target terminal, the interface between FPGA and the 3rd target terminal be phase
It is mutually independent, walk different passages.All target terminals 300 being connected with FPGA, the interface protocol followed may whole phases
Together, it is also possible to which part is identical, it is also possible to entirely different.The second class interface 2 connects including GPIO mouthfuls, serial ports, pcm interface, I2C
Mouth and SPI interface.FPGA softwares need to be designed according to the quantity and the interface protocol that is followed of the target terminal being connected；It is described
The traffic rate of second class interface 2 can be configured according to the rate that target terminal 300 is supported.
FPGA receives the data of CPU transmissions by first kind interface 1, is assisted by the physical interface followed between CPU-FPGA
View is received, for example is serial ports between CPU-FPGA, is just received by serial ports agreement, is obtained the user data of CPU transmissions, i.e., and the
One data message.There are many forms of first data message, for example, packet header mark+target terminal number+data type+original
Data, it is necessary to by agreement interface format, the first data message is parsed, obtains initial data, be CPU issue first
The first initial data of the target terminal 300 of target terminal number is corresponded in data message；Pass through the second class interface 2, such as SPI
First initial data is issued the target terminal that corresponding target terminal 300 numbers by interface by SPI interface protocol conventions.
In another embodiment of the present invention, as shown in figure 4, a kind of field programmable gate array 200 includes：
Field programmable gate array 200 is connected by first kind interface 1 with central processing unit 100, passes through the second class interface 2
It is connected with target terminal 300, the second class interface 2 there are several, and different target terminals 300 corresponds to the second different classes and connects
Mouth 2；
The field programmable gate array 200 includes：
Second receiving module 220, for receiving the number of the transmission of central processing unit 100 by the first kind interface 1
According to obtaining the first data message；
Parsing module 230 is electrically connected with second receiving module 220, for parsing first data message, is obtained
First initial data of the corresponding target terminal 300 of first data message；
Second sending module 210 is electrically connected with the parsing module 230, described in being incited somebody to action by the second class interface 2
First initial data issues the corresponding target terminal 300 of first data message；
Second receiving module 220 is further used for the number for receiving the target terminal by the second class interface 2 and sending
According to obtaining the second initial data that the target terminal 300 issues the central processing unit 100；
The parsing module 230 is further used for assembling second initial data, obtains the second data letter
Breath；
Second sending module 210 is further used for sending out second data message by the first kind interface 1
To the central processing unit 100.
Specifically, compared with previous embodiment, up direction, i.e. connecing from target terminal → FPGA → CPU are added
Mouth interaction flow.FPGA, according to the interface protocol between FPGA- target terminals, receives target terminal by the second class interface 2
300 data sent, obtain the second initial data；Second initial data is issued CPU by FPGA, before this, it is necessary to first press
The interface protocol of CPU-FPGA assembles the second initial data, obtains the second data message；Assuming that the second of CPU-FPGA
The form of data message is that packet header mark+target terminal number+data type+initial data is then needed before the second initial data
Packet header mark+target terminal number+data type is added, forms the second data message；FPGA again will by first kind interface 1
Second data message issues CPU.
In another embodiment of the present invention, as shown in figure 5, a kind of field programmable gate array 200 includes：
Field programmable gate array 200 is connected by first kind interface 1 with central processing unit 100, passes through the second class interface 2
It is connected with target terminal 300, the second class interface 2 there are several, and different target terminals 300 corresponds to the second different classes and connects
Mouth 2；
The field programmable gate array 200 includes：
Second receiving module 220, for receiving the number of the transmission of central processing unit 100 by the first kind interface 1
According to obtaining the first data message；
Parsing module 230 is electrically connected with second receiving module 220, for parsing first data message, is obtained
First initial data of the corresponding target terminal 300 of first data message；
Second sending module 210 is electrically connected with the parsing module 230, described in being incited somebody to action by the second class interface 2
First initial data issues the corresponding target terminal 300 of first data message；
First data message includes：Data after packet header mark, address information and the first escape；
The parsing module 230 is further used for finding the packet header mark in first data message；And
When finding the packet header mark in first data message, described address information and corresponding target terminal 300 are obtained；
And when finding the packet header mark in first data message, it is corresponding described to obtain first data message
Data after first escape of target terminal 300；And by the data after first escape according to default escape rule into
Row reversion justice, obtains first initial data；
The parsing module 230 is further used for traveling through the content of each byte in the data after first escape, sentences
It is disconnected to whether there is at least one first byte；First byte is the byte content byte identical with the first escape character；With
And when there are during at least one first byte, according to existing first byte, each first byte of acquisition corresponds to
Combination of bytes；Each combination of bytes includes：The content of one first byte and first byte are corresponding next
The content of a byte；And according to default escape rule and each combination of bytes, it is each right to obtain each combination of bytes
Answer by escape character；And all combination of bytes in the data after first escape are replaced with corresponding described
By escape character, the central processing unit 100 issues the corresponding target terminal 300 of first data message is obtained
One initial data；
Second receiving module 220, is further used for receiving the target terminal 300 by the second class interface 2 and sends
Data, obtain the second initial data that the target terminal 300 issues the central processing unit 100；
The parsing module 230 is further used for assembling second initial data, obtains the second data letter
Breath；
Second sending module 210 is further used for sending out second data message by the first kind interface 1
To the central processing unit 100；
The parsing module 230 is further used for when second initial data is included by escape character, by the quilt
Escape character carries out escape according to default escape rule, obtains the data after the second escape；And after second escape
Data before plus packet header mark and address information, according between the central processing unit 100 and field programmable gate array 200
Interface format, be assembled into second data message；
The packet header is identified as a character；
Default escape rule is：
There are two by escape character, wherein, turned with the sensible same character of packet header for first by escape character, second
Adopted character is preset characters, and described second is different by escape character from described first by escape character；
One is obtained the combination of bytes being made of two characters after escape character escape, wherein, in the combination of bytes
First character be fixed as second by escape character, second character in the combination of bytes is according to described by escape character
It is calculated with preset function operational formula；
Cache module 240 is further included, is electrically connected with the parsing module 230, for caching second data message；
Second sending module 210 is further used for when the institute for having no less than one target terminal 300 in caching
When stating the second data message, according to the priority of the target terminal 300, the high target terminal of preferential transmission priority
Second data message gives the central processing unit 100.
Specifically, in order to avoid in initial data occur with packet header it is sensible with byte when, receiving terminal is to receive information
Misunderstanding, transmitting terminal carried out escape to original data content；FPGA is sent to by the second initial data of target terminal 300
During CPU, the second raw data packets are traveled through, when second initial data is included by escape character, by described by escape word
Symbol carries out escape according to default escape rule, obtains the data after the second escape；On this basis, in addition packet header identifies, press
According to the interface format between CPU and FPGA, second data message is assembled into；Similarly FPGA is right when receiving the data of CPU
Justice is unpacked and inverted to the first data message received, so as to obtain the first initial data.It is assumed that connecing between CPU-FPGA
Mouthful form is：Data content after packet header mark+address information+escape, as shown in fig. 7, wherein 0x7E identifies for packet header, Addr
A byte is accounted for, meaning is as shown in the table：
| Addr | Function |
| 0x0 | Send data to target terminal 0 |
| 0x1 | Send data to target terminal 1 |
| 0x2 | Send data to target terminal 2 |
| 0x3 | Receive the data of target terminal 0 |
| 0x4 | Receive the data of target terminal 1 |
| 0x5 | Receive the data of target terminal 2 |
Escape rule is as follows：
Wherein, be 0x7E and 0x7D by escape character, wherein 0x7E for first by escape character, it is sensible same with packet header,
0x7D is for second by escape character；One is obtained the combination of bytes being made of two characters, wherein word after escape character escape
First character in section combination is 0x7D, i.e., second by escape character, and second character in combination of bytes is according to default letter
Number operational formula is calculated, for example, above table is according to formulaIt is calculated,Represent exclusive or behaviour
Make, as x=0x7E, obtain second character after escape as 0x5E；As x=0x7D, second word after escape is obtained
It accords with as 0x5D.Preset function operational formula can also be other functional forms, for example,, the above is only one kind
Embodiment.
Assuming that the first data message that CPU is sent to target terminal 0 is：0x7E、0x0、0x1、0x7D、0x5E、0x2、
0x7D、0x5D、0x7D、0x5E、0x5E；FPGA receive CPU transmission first data message when, to the first data message into
Row parsing, the 1st byte 0x7E identify for packet header, and 0x0 Addr show to be intended for the data of target terminal 0；After Addr
Data are the data after the first escape, are 0x1,0x7D, 0x5E, 0x2,0x7D, 0x5D, 0x7D, 0x5E, 0x5E；Traversal the
The content of each byte, judges whether at least one first byte in data after one escape；The first byte herein is
The byte for being 0x7D for byte content judges that the data after the first escape whether there is escape character 0x7D；If it is present
Reversion justice is carried out by default escape rule, i.e. 0x7D5E, which is corresponded to, to be corresponded to by escape character 0x7E, 0x7D5D by escape character
0x7D；In this example, after reversion justice, 0x1,0x7E, 0x2,0x7D, 0x7E, 0x5E are obtained, is the first initial data.Such as
When escape character 0x7D being not present in the data after the first escape of fruit, the data after the first escape are the first initial data.Such as
There are escape character 0x7D in data after the first escape of fruit, but the corresponding combination of bytes of the first byte neither 0x7D5E,
When not being 0x7D5D, then illustrate in transmission process that there may be mistakes, this first data message to abandon.
FPGA to CPU send target terminal 0 the second initial data when, it is assumed that the second initial data for 0x1,0x7E,
0x2,0x7D, 0x7E, 0x5E are, it is necessary to check that the second initial data whether there is by escape character 0x7E or 0x7D；If it does,
Escape then is carried out by default escape rule, i.e. 0x7E corresponds to 0x7D5E, and 0x7D corresponds to 0x7D5D, after escape, obtains the
Data after two escapes, i.e. 0x1,0x7D, 0x5E, 0x2,0x7D, 0x5D, 0x7D, 0x5E, 0x5E.By the number after the second escape
According to, in addition packet header identifies 0x7E and determines Addr according to target terminal as 0x3, in addition Addr, obtains the second data message,
That is 0x7E, 0x3,0x1,0x7D, 0x5E, 0x2,0x7D, 0x5D, 0x7D, 0x5E, 0x5E.
There may be multiple target terminals 300 to send data to FPGA simultaneously, FPGA is received and cached successively；When FPGA to
When CPU is sent, preferential the second data message for sending the high target terminal 300 of priority is to CPU.
In another embodiment of the present invention, as shown in fig. 6, a kind of interface based on field programmable gate array 200
Expansion system, including：Field programmable gate array 200 described in any of the above-described embodiment；It further includes：Central processing unit 100,
Several target terminals 300；The central processing unit 100 is electrically connected with the field programmable gate array 200；It is each described
Target terminal 300 is electrically connected with the field programmable gate array 200；
The central processing unit 100 includes：
First sending module 110, for sending first data message to the scene by the first kind interface 1
Programmable gate array 200；
First receiving module 120, for being received by the first kind interface 1 from field programmable gate array 200
Second data message；
Each target terminal 300 includes：
3rd sending module 310, for sending second initial data to the scene by the second class interface 2
Programmable gate array 200；
3rd receiving module 320, for being received by the second class interface 2 from the field programmable gate array
200 first initial data.
Specifically, field programmable gate array 200 can be connected with multiple target terminals 300, Fig. 6 has drawn two target ends
End 300, is only used for illustrating.
Interface between FPGA and CPU is first kind interface 1, as shown in figure 8, being string by the interface between FPGA and CPU
Mouth is illustrated.CPU includes the first sending module and the first receiving module, by first kind interface 1, with FPGA into row information
Interaction.
FPGA is the second class interface 2 with several 300 direct interfaces of target terminal, as shown in figure 8, by FPGA and target
Interface between terminal is illustrated for SPI mouthfuls.Each target terminal 300 includes the 3rd sending module and the 3rd receiving module,
By the second class interface 2, with FPGA into the interaction of row information.Single CPU and several target terminals 300 are realized by FPGA
Interactive interfacing extends the interface of single CPU, reduces cost.
It should be noted that above-described embodiment can be freely combined as needed.The above is only the preferred of the present invention
Embodiment, it is noted that for those skilled in the art, do not departing from the premise of the principle of the invention
Under, several improvements and modifications can also be made, these improvements and modifications also should be regarded as protection scope of the present invention.
Claims (10)
- A kind of 1. Interface Expanding method based on field programmable gate array, it is characterised in that：Field programmable gate array passes through First kind interface is connected with central processing unit, is connected by the second class interface with target terminal, the second class interface has several A, different target terminals corresponds to the second different class interfaces, further includes：The data that step S100 is sent by central processing unit described in the first kind interface, obtain the first data message；Step S200 parses first data message, obtains the corresponding target terminal of first data message The first initial data；First initial data is issued the corresponding institute of first data message by step S300 by the second class interface State target terminal.
- 2. the Interface Expanding method according to claim 1 based on field programmable gate array, which is characterized in that described One data message includes：Data after packet header mark, address information and the first escape, the step S200 are specifically included：Step S210 finds the packet header mark in first data message；Step S220 obtains described address information and corresponding when finding packet header mark in first data message Target terminal；Step S230 obtains first data message and corresponds to when finding the packet header mark in first data message The target terminal the first escape after data；Data after first escape are carried out reversion justice by step S240 according to default escape rule, and it is former to obtain described first Beginning data.
- 3. the Interface Expanding method according to claim 1 based on field programmable gate array, which is characterized in that also wrap It includes：The data that step S400 is sent by target terminal described in the second class interface, obtain the second initial data；Step S500 assembles second initial data, obtains the second data message；Second data message is issued the central processing unit by step S600 by the first kind interface.
- 4. the Interface Expanding method according to claim 3 based on field programmable gate array, which is characterized in that the step Rapid S500 is specifically included：Step S510 when second initial data include by escape character when, by it is described by escape character according to default escape Rule carries out escape, obtains the data after the second escape；Plus packet header mark and address information before data of the step S520 after second escape, according to the central processing unit Interface format between field programmable gate array is assembled into second data message.
- 5. the Interface Expanding method based on field programmable gate array according to claim 2 or 4, it is characterised in that：The packet header is identified as a character；Default escape rule is：There are two by escape character, wherein, with the sensible same character of packet header for first by escape character, second by escape word Accord with for preset characters, described second it is different by escape character from described first by escape character；One is obtained the combination of bytes being made of two characters after escape character escape, wherein, in the combination of bytes One character is fixed as second by escape character, second character in the combination of bytes according to it is described by escape character with it is pre- If functional operation formula is calculated.
- 6. the Interface Expanding method according to claim 3 based on field programmable gate array, the step S600 are specific Including：Step S610 caches second data message；Step S620 is when there is second data message of no less than one target terminal in caching, according to the target The priority of terminal, preferential second data message for sending the high target terminal of priority is to the central processing Device.
- 7. a kind of field programmable gate array, it is characterised in that：Field programmable gate array is connected by first kind interface with central processing unit, passes through the second class interface and target terminal phase Even, the second class interface has several, and different target terminals corresponds to the second different class interfaces；The field programmable gate array includes：Second receiving module for the data sent by central processing unit described in the first kind interface, obtains first Data message；Parsing module is electrically connected with second receiving module, for parsing first data message, obtains first number It is believed that the first initial data of the corresponding target terminal of breath；Second sending module is electrically connected with the parsing module, for by the second class interface by first original number According to issuing the corresponding target terminal of first data message.
- 8. field programmable gate array according to claim 7, it is characterised in that：First data message includes：Data after packet header mark, address information and the first escape；The parsing module is further used for finding the packet header mark in first data message；And when described When the packet header mark is found in the first data message, described address information and corresponding target terminal are obtained；And when in institute It states when packet header mark is found in the first data message, obtains the of the corresponding target terminal of first data message Data after one escape；And the data after first escape are subjected to reversion justice according to default escape rule, obtain institute State the first initial data.
- 9. field programmable gate array according to claim 7, it is characterised in that：Second receiving module is further used for the data sent by target terminal described in the second class interface, obtains The target terminal issues the second initial data of the central processing unit；The parsing module is further used for assembling second initial data, obtains the second data message；Second sending module, be further used for by the first kind interface by second data message issue it is described in Central processor.
- 10. a kind of Interface Expanding system based on field programmable gate array, which is characterized in that including：Claim 7-9 is any The field programmable gate array；It further includes：Central processing unit, several target terminals；The central processing unit is electrically connected with the field programmable gate array；Each target terminal, is electrically connected with the field programmable gate array；The central processing unit includes：First sending module, for sending first data message to the field programmable gate by the first kind interface Array；First receiving module, for passing through second data of the first kind interface from field programmable gate array Information；Each target terminal includes：3rd sending module, for sending second initial data to the field programmable gate by the second class interface Array；3rd receiving module, for passing through described first of the second class interface from the field programmable gate array Initial data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711339980.8A CN108108316B (en) | 2017-12-14 | 2017-12-14 | Interface expansion method and system based on field programmable gate array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711339980.8A CN108108316B (en) | 2017-12-14 | 2017-12-14 | Interface expansion method and system based on field programmable gate array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108108316A true CN108108316A (en) | 2018-06-01 |
| CN108108316B CN108108316B (en) | 2023-08-11 |
Family
ID=62216940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711339980.8A Active CN108108316B (en) | 2017-12-14 | 2017-12-14 | Interface expansion method and system based on field programmable gate array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108108316B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880998A (en) * | 2019-12-03 | 2020-03-13 | 锐捷网络股份有限公司 | Message transmission method and device based on programmable device |
| CN111464638A (en) * | 2020-03-31 | 2020-07-28 | 潍柴动力股份有限公司 | Data message processing method and device |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6970956B1 (en) * | 2001-10-01 | 2005-11-29 | Juniper Networks, Inc. | Scaleable gap insertion in a data link |
| CN102377505A (en) * | 2010-08-06 | 2012-03-14 | 研祥智能科技股份有限公司 | Serial port-based IPMI (Intelligent Platform Management Interface) package transmission method |
| CN103714024A (en) * | 2013-12-18 | 2014-04-09 | 国核自仪系统工程有限公司 | Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array) |
| CN104484301A (en) * | 2014-12-25 | 2015-04-01 | 南京因泰莱电器股份有限公司 | FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with automatic recognition function |
| CN104636300A (en) * | 2015-02-09 | 2015-05-20 | 南京国电南自美卓控制系统有限公司 | Serial transceiver based on SOC FPGA and data receiving and sending method |
| CN105095139A (en) * | 2014-05-08 | 2015-11-25 | 中兴通讯股份有限公司 | Inter-integrated circuit system and data operation and transmission method thereof |
| CN105530590A (en) * | 2014-09-29 | 2016-04-27 | 阿里巴巴集团控股有限公司 | Method and electronic equipment for realizing resource sharing between equipment |
| CN205692166U (en) * | 2016-06-12 | 2016-11-16 | 成都傅立叶电子科技有限公司 | Core board based on PowerPC framework central processing unit |
| CN106201629A (en) * | 2016-07-22 | 2016-12-07 | 北京广利核系统工程有限公司 | A kind of method and apparatus to the programming of multi-disc target FPGA |
-
2017
- 2017-12-14 CN CN201711339980.8A patent/CN108108316B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6970956B1 (en) * | 2001-10-01 | 2005-11-29 | Juniper Networks, Inc. | Scaleable gap insertion in a data link |
| CN102377505A (en) * | 2010-08-06 | 2012-03-14 | 研祥智能科技股份有限公司 | Serial port-based IPMI (Intelligent Platform Management Interface) package transmission method |
| CN103714024A (en) * | 2013-12-18 | 2014-04-09 | 国核自仪系统工程有限公司 | Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array) |
| CN105095139A (en) * | 2014-05-08 | 2015-11-25 | 中兴通讯股份有限公司 | Inter-integrated circuit system and data operation and transmission method thereof |
| CN105530590A (en) * | 2014-09-29 | 2016-04-27 | 阿里巴巴集团控股有限公司 | Method and electronic equipment for realizing resource sharing between equipment |
| CN104484301A (en) * | 2014-12-25 | 2015-04-01 | 南京因泰莱电器股份有限公司 | FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with automatic recognition function |
| CN104636300A (en) * | 2015-02-09 | 2015-05-20 | 南京国电南自美卓控制系统有限公司 | Serial transceiver based on SOC FPGA and data receiving and sending method |
| CN205692166U (en) * | 2016-06-12 | 2016-11-16 | 成都傅立叶电子科技有限公司 | Core board based on PowerPC framework central processing unit |
| CN106201629A (en) * | 2016-07-22 | 2016-12-07 | 北京广利核系统工程有限公司 | A kind of method and apparatus to the programming of multi-disc target FPGA |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880998A (en) * | 2019-12-03 | 2020-03-13 | 锐捷网络股份有限公司 | Message transmission method and device based on programmable device |
| CN110880998B (en) * | 2019-12-03 | 2022-09-20 | 锐捷网络股份有限公司 | Message transmission method and device based on programmable device |
| CN111464638A (en) * | 2020-03-31 | 2020-07-28 | 潍柴动力股份有限公司 | Data message processing method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108108316B (en) | 2023-08-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ES2929124T3 (en) | Method for data transmission via a serial communication bus, correspondingly designed bus interface and correspondingly designed computer program | |
| CN102577268B (en) | Apparatus and method for transmitting a MAC PDU based on MAC header type information | |
| WO2017012510A1 (en) | Method and device for transmitting flexible ethernet service flow | |
| JP7282146B2 (en) | BRAS system-based packet encapsulation method and apparatus | |
| CN104246734B (en) | The expansible WSE HUB of the multi-hop tree of USB HUB or ancillary equipment are supported on wireless links | |
| US20140334492A1 (en) | Methods for Dynamically Binding Header Field Identifiers in a Network Control Protocol | |
| CN103077148B (en) | A kind of host communication method of Based PC IE and main frame | |
| WO2016191990A1 (en) | Packet conversion method and device | |
| CN108108316A (en) | A kind of Interface Expanding method and system based on field programmable gate array | |
| SE522878C2 (en) | Data communication systems | |
| CN106257434A (en) | A kind of data transmission method based on enhancement mode peripheral interconnection protocol bus and device | |
| WO2011140844A1 (en) | Method for processing messages on m2m platform and m2m platform system | |
| CN105338099A (en) | Method and system for realizing customized vehicle-mounted host based on Bluetooth MAC (Medium Access Control) address identification | |
| US10587572B1 (en) | Group signaling using synthetic media access control addresses | |
| CN106686553A (en) | Method and device for carrying out multicasting on core net EPC | |
| CN103916493B (en) | A kind of IP address section distribution method and device | |
| US20060109845A1 (en) | Method of transporting a RapidIO packet over an IP packet network | |
| CN207652705U (en) | A kind of system of control terminal and the equipment access network based on wifi Beacon frames | |
| CN102821055B (en) | Method for inter-board communication | |
| CN104871590B (en) | A kind of method, system and device of capability negotiation | |
| CN109951458A (en) | A kind of RapidIO/FC protocol conversion system and method applied to analog IC P environment | |
| CN108809795A (en) | Transparent shunt method and device in a kind of LAN environment | |
| CN105072026A (en) | Internet-of-things gateway communication system | |
| CN109861976A (en) | Internet of things equipment protocol fitting method | |
| CN106681778A (en) | Multi-single-chip-microcomputer one-time flash system based on network and implementation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20201110 Address after: 318015 no.2-3167, zone a, Nonggang City, no.2388, Donghuan Avenue, Hongjia street, Jiaojiang District, Taizhou City, Zhejiang Province Applicant after: Taizhou Jiji Intellectual Property Operation Co.,Ltd. Address before: 201616 Shanghai city Songjiang District Sixian Road No. 3666 Applicant before: Phicomm (Shanghai) Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20230606 Address after: Unit 402A, Building 2, Building 1, Keji 7th Road, Tangjiawan Town, High tech Zone, Zhuhai City, Guangdong Province, 519000 Applicant after: ZHUHAI SG ELECTRIC TECHNOLOGY CO.,LTD. Address before: 318015 no.2-3167, area a, nonggangcheng, 2388 Donghuan Avenue, Hongjia street, Jiaojiang District, Taizhou City, Zhejiang Province Applicant before: Taizhou Jiji Intellectual Property Operation Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20230720 Address after: Unit 402A, Building 2, Building 1, Keji 7th Road, Tangjiawan Town, High tech Zone, Zhuhai City, Guangdong Province, 519000 Applicant after: ZHUHAI SG ELECTRIC TECHNOLOGY CO.,LTD. Applicant after: Gao Wei Address before: Unit 402A, Building 2, Building 1, Keji 7th Road, Tangjiawan Town, High tech Zone, Zhuhai City, Guangdong Province, 519000 Applicant before: ZHUHAI SG ELECTRIC TECHNOLOGY CO.,LTD. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |