CN106201629A - A kind of method and apparatus to the programming of multi-disc target FPGA - Google Patents
A kind of method and apparatus to the programming of multi-disc target FPGA Download PDFInfo
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- CN106201629A CN106201629A CN201610586439.6A CN201610586439A CN106201629A CN 106201629 A CN106201629 A CN 106201629A CN 201610586439 A CN201610586439 A CN 201610586439A CN 106201629 A CN106201629 A CN 106201629A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Abstract
The invention belongs to the technical field of FPGA, relate to a kind of method and apparatus to the programming of multi-disc target FPGA；Wherein, described method comprises determining that target FPGA needing programming in described multi-disc target FPGA, is generated by computer and programs file accordingly；Programming file corresponding for described target FPGA needing to program is sent to described main FPGA；Send to described main FPGA and start program command and the enable signal corresponding with described target FPGA needing to program；Respectively described target FPGA is programmed, and the communication mode between described multi-disc target FPGA and described main FPGA selects at least one of which from communication.Therefore, use technique scheme, can realize using different communication protocol between target FPGA by main FPGA, can complete dissimilar target devices is programmed；Improve the range of application of product.
Description
Technical field
The present invention relates to the technical field of FPGA, particularly relate to a kind of method and apparatus to the programming of multi-disc target FPGA.
Background technology
FPGA, English full name is Field-Programmable Gate Array, and Chinese full name is field programmable gate
Array, it is to occur as a kind of semi-custom circuit in special IC (ASIC) field, has both solved customization electricity
The deficiency on road, overcomes again the shortcoming that original programming device gate circuit number is limited.
The advantages such as FPGA is fast by feat of speed, motility is high, aboundresources, have obtained more and more wider in embedded systems
General application.In order to realize a complicated control system, generally require multi-disc target FPGA and realize, and for multi-disc target
The system that FPGA is constituted, its program updates and general uses daisy chain to couple together serial download.
Inventor finds during realizing the present invention, in the system that multiple FPGA that daisy chain couples together are constituted,
There is used time longer shortcoming, and if have a piece of FPGA fault in daisy chain, the FPGA that may result in other can not add
Carry successfully；And typically also need to dismantle board when downloading, waste time and energy, and some occasions are just not suitable for staff
FPGA is programmed by ground.
Such as, in the patent that Chinese Patent Application No. is CN200610113841.9, disclose one CPU and add simultaneously
The method carrying multi-disc target FPGA, for including monolithic or multi-disc target FPGA and the system of CPU, the method includes: step one,
A FPGA load document is generated by the bit loading stream file of multi-disc target FPGA being merged process；Step 2, to institute
State the address bus of CPU to carry out logical extension and obtain loading the depositor needed for described multi-disc target FPGA and latch；And step
Rapid three, described CPU read described FPGA load document to the exented memory of described CPU and by control described depositor and described
Latch produces when loading a piece of FPGA in multi-disc target FPGA or described multi-disc target FPGA described in ordered pair and loads.
Although but the technical scheme in above-mentioned patent accelerates the CPU loading velocity to multi-disc target FPGA, improves
The reliability of loaded circuit and motility, but to be only applicable to each target FPGA type identical for this method, configuration protocol
Consistent system；The most this simultaneously little to the range loading multi-disc target FPGA method.
Summary of the invention
Technology in order to solve in prior art range present in the loading method to multi-disc target FPGA little is asked
Topic, the invention provides one and can load multi-disc target FPGA and each target FPGA is separate simultaneously, support a kind of or
The method and apparatus to the programming of multi-disc target FPGA of multiple programming protocol.
To achieve these goals, the technical scheme that the present invention provides includes:
On the one hand, it is provided that a kind of method to the programming of multi-disc target FPGA, it is characterised in that described multi-disc target FPGA is divided
Not being connected with main FPGA, described main FPGA is able to receive that external data；Described method includes:
Determine target FPGA needing programming in described multi-disc target FPGA, generated by computer and program literary composition accordingly
Part；
Programming file corresponding for described target FPGA needing to program is sent to described main FPGA；
Send to described main FPGA and start program command and the enable signal corresponding with described target FPGA needing to program；
Respectively described target FPGA is programmed, and the communication between described multi-disc target FPGA and described main FPGA
Mode selects at least one of which from communication.
Therefore, use technique scheme, can realize using different communication between target FPGA by main FPGA
Agreement, can complete to program dissimilar target devices；Improve the range of application of product.
Further, described method also includes: inquire about programming progress and/or the shape of target FPGA of described needs programming
State, and the programming progress of target FPGA programmed by described needs and/or feedback of status are to described computer.
Therefore, use above-mentioned further preferred technical scheme, can more preferably monitoring objective FPGA programming state, even if
Programming process occurs abnormality, also can know in time；Avoid follow-up maloperation.
And in order to solve present in prior art in the multiple programming technical scheme of multi-disc target FPGA, every time
More new procedures is required for being carried out in situ programming, it is impossible to program carries out the technical problems such as long-range renewal, the present invention further provides
Technical scheme include: the described computer communication mode by Ethernet, by described need programming target FPGA corresponding
Programming file sends to described main FPGA.It is thereby achieved that the long-range programming to multi-disc target FPGA.
Further, between described main FPGA and described target FPGA, it is respectively adopted point-to-point communication, and described multiple
Communication mode includes SPI and JTAG；And described target FPGA is programmed using individually programming or programs simultaneously
Mode carry out.
Further, described main FPGA receives the programming file that described target FPGA needing to program is corresponding, first to institute
State programming file resolve, and will resolve after programming file, according to the address that different target FPGA is corresponding, be respectively stored in
In zones of different in the external memory storage being connected with described main FPGA；And call corresponding volume respectively according to described enable signal
Journey file, is programmed target FPGA needing programming.Therefore, it is possible to use high-speed memory, and utilize at FPGA data
Reason speed is fast, the advantage of parallel work-flow, it is achieved the high-speed parallel program of different target FPGA；And each FPGA phase being loaded
The most independent, monolithic programming multi-disc can load again simultaneously, and the multiple programming for dissimilar FPGA can be completed, carry
The motility of high system.
On the other hand, the embodiment of the present invention also provides for a kind of device to the programming of multi-disc target FPGA, it is characterised in that institute
State device to include:
Multi-disc target FPGA, is respectively used to different targeted execution unit executive control operations；
The main FPGA being connected with described multi-disc target FPGA, described main FPGA are provided with receiving the transmitting-receiving of external data
Module and the command analysis module resolving described external data, described external data includes target FPGA that needs program
Corresponding programming file, the enable signal corresponding with described target FPGA and startup program command；
Wherein, described main FPGA is additionally provided with lower tubulature reason scheduler module, and described lower tubulature reason scheduler module can be to institute
State target FPGA and send corresponding programming communication mode between file, and described multi-disc target FPGA and described main FPGA therewith
At least one of which is selected from communication.
Further, described lower tubulature reason scheduler module can also inquire about being programmed into of described target FPGA needing programming
Degree and/or state, and programming progress and/or the feedback of status of described target FPGA needing programming are connected to described main FPGA
The peripheral hardware connect.
And in order to solve present in prior art in the multiple programming technical scheme of multi-disc target FPGA, every time
More new procedures is required for being carried out in situ programming, it is impossible to program carries out the technical problems such as long-range renewal, the present invention further provides
Technical scheme include: the transceiver module in described main FPGA is connected with computer by Ethernet, described computer generation phase
The programming file answered.
Further, between described main FPGA and described target FPGA, it is respectively adopted point-to-point communication, and described multiple
Communication mode includes SPI and JTAG；And described target FPGA is programmed using individually programming or programs simultaneously
Mode carry out.
Further, described main FPGA receives the programming file that described target FPGA needing to program is corresponding, described life
Parsing module is made first described programming file to be resolved, and the programming file after resolving, corresponding according to different target FPGA
Address, be respectively stored in the zones of different in the external memory storage being connected with described main FPGA；Described lower dress management and dispatching
Module is called respectively according to described enable signal and is programmed file accordingly, is programmed target FPGA needing programming.
The above-mentioned optimal technical scheme using the present invention to provide, can at least obtain the one in following beneficial effect:
1, can realize using different communication protocol between target FPGA by main FPGA, can complete inhomogeneity
Type target devices programs；Improve the range of application of product.
2, use above-mentioned further preferred technical scheme, can more preferably monitoring objective FPGA programming state, even if compile
Abnormality occurs during journey, also can know in time；Avoid follow-up maloperation.
3, point-to-point communication, and described communication it are respectively adopted between described main FPGA and described target FPGA
Including SPI and JTAG；And it is programmed described target FPGA to enter in the way of using individually programming or programming simultaneously
OK.
4, high-speed memory can be used, and utilize that FPGA data processing speed is fast, the advantage of parallel work-flow, it is achieved be different
The high-speed parallel program of target FPGA；And each FPGA being loaded is separate, can monolithic programming again can multi-disc simultaneously
Load, and the multiple programming for dissimilar FPGA can be completed, improve the motility of system.
Further feature and the advantage of invention will illustrate in the following description, and, partly become aobvious from description
And be clear to, or understand by implementing technical scheme.The purpose of the present invention and other advantages can be by explanations
Structure specifically noted in book, claims and accompanying drawing and/or flow process realize and obtain.
Accompanying drawing explanation
A kind of flow chart to multi-disc target FPGA programmed method that Fig. 1 provides for the embodiment of the present invention；
A kind of structured flowchart to multi-disc target FPGA programmer that Fig. 2 provides for the embodiment of the present invention；
Fig. 3 for the embodiment of the present invention provide a kind of to the structured flowchart of main FPGA in multi-disc target FPGA programmer.
Detailed description of the invention
Describe embodiments of the present invention in detail below with reference to drawings and Examples, whereby how the present invention is applied
Technological means solves technical problem, and the process that realizes reaching technique effect can fully understand and implement according to this.Need explanation
, these specific descriptions simply allow those of ordinary skill in the art be more prone to, clearly understand the present invention, rather than to this
Bright limited explanation；And if do not constitute conflict, each embodiment in the present invention and each spy in each embodiment
Levying and can be combined with each other, the technical scheme formed is all within protection scope of the present invention.
It addition, can be in the control system of a such as group controller executable instruction in the step shown in the flow chart of accompanying drawing
Middle execution, and, although show logical order in flow charts, but in some cases, can be to be different from herein
Step shown or described by order execution.
Below by the drawings and specific embodiments, technical scheme is described in detail:
Embodiment
The embodiment of the present invention provides a kind of device to the programming of multi-disc target FPGA, and this device directly uses with prior art
The mode of CPU is different, use main FPGA203 as main control chip, main FPGA203 can to other targets FPGAFPGA205,
206, the multiple programming of 207,208, the program of main FPGA203 needs to be cured, and target FPGAFPGA205,206,207,208
Can remotely update；Target FPGAFPGA205 in this device, 206,207,208 be Flash technique FPGA it can also be used to
The FPGA of SRAM technique, but its programming to as if its configuration memorizer.The most as shown in Figure 2 and Figure 3, this device includes:
Multi-disc target FPGA205,206,207,208, be respectively used to different targeted execution unit executive control operations,
And first object FPGA205, the second target FPGA206, the 3rd target FPGA207 ... the n-th target FPGA208, Ke Yigen
Demand according to concrete application scenarios, it can be provided identical, it is also possible to be arranged to difference；
With multi-disc target FPGA205,206,207, the 208 main FPGA203 being connected, main FPGA203 is provided with receiving
The transceiver module 310 of external data and the command analysis module 320 resolving external data, external data includes needing to compile
The programming file that target FPGA of journey is corresponding, the enable signal corresponding with target FPGA and start program command；The present embodiment
Middle target FPGA needing programming can be first object FPGA205, the second target FPGA206, the 3rd target FPGA207 ...
Whole FPGA in n-th target FPGA208, it is also possible to be arranged to part FPGA；
Be connected with main FPGA203 also have external memory storage 204, switch 202, switch 202 again with computer 201 phase
Even；External memory storage can be the mass storages such as SDRAM, NAND Flash, and external memory storage 204 stores all targets
The configuration data of FPGA, need it is carried out subregion, and address space distribution can be according to the type of target FPGA and configuration file
Size determine；Computer 201 can generate the binary system download file of each target FPGA, by leading to that switch 202 connects
Road is sent to main FPGA203；
Wherein, main FPGA203 is additionally provided with lower tubulature reason scheduler module 340, and lower tubulature reason scheduler module 340 can be to mesh
Mark FPGA sends correspondence therewith and programs the communication mode between file, and multi-disc target FPGA and main FPGA from multiple communication party
Formula selects at least one of which.
Therefore, it can realize using different communication protocol between target FPGA by main FPGA203, it is right to complete
Dissimilar target devices programs；Improve the range of application of product.
Preferably, lower tubulature reason scheduler module 340 can also inquire about need programming target FPGA programming progress and/or
State, and the computer that the programming progress and/or feedback of status that need target FPGA of programming are extremely connected with main FPGA203
201, the computer 201 in the present embodiment can also pass through other intelligent terminal, and the such as peripheral hardware such as panel computer, smart mobile phone takes
Generation.Therefore, it can the state of more preferable monitoring objective FPGA programming, even if programming process occurs abnormality, also can know in time
Dawn；Avoid follow-up maloperation.
And in order to solve present in prior art in the multiple programming technical scheme of multi-disc target FPGA, every time
More new procedures is required for being carried out in situ programming, it is impossible to program carries out the technical problems such as long-range renewal, the present invention further provides
Technical scheme include: transceiver module in main FPGA203 310 is connected with computer 201 by Ethernet, thus can be right
Target FPGA remotely programs, it is not necessary to dismounting FPGA card plate, easy to operate, time saving and energy saving, also can meet site environment and dislike
Bad, be not suitable for the occasion of manual site's operation.
Preferably, main FPGA203 and target FPGA205, it is respectively adopted point-to-point communication between 206,207,208, and
Communication includes SPI and JTAG；And to target FPGA205,206,207,208 it is programmed using individually volume
Journey or the mode simultaneously programmed are carried out.Therefore, the mode of programming is more flexibly, quickly.
Main FPGA203 is the core of device, it is achieved the reception of programming data, caching and lower tubulature reason, main FPGA203 receives
And cache after data are verified to external memory storage 204, and wait the program command of computer 201；And different target
The download file of FPGA is stored in external memory storage zones of different；After starting programming, main FPGA203 is from external memory storage 204
Read the data of each target FPGA, and according in agreement write target FPGA, it is achieved programming and the startup to target FPGA；In it
Portion's concrete structure, as it is shown on figure 3, main FPGA internal logic block diagram 300 includes:
Transceiver module 310, is provided with RAM1 (311) in transceiver module, receive target FPGA needing to program corresponding
Programming file, completes the transmitting-receiving of Ethernet data, and data can be temporarily stored in internal RAM 1 (311), to be verified correct after notify life
Parsing module 320 is made to read data；Transceiver module is mainly used in receiving configuration data, and its communication protocol can be selected as required
Select, the custom protocol of simplification can be used, it is possible to use Transmission Control Protocol.
Command analysis module 320 first to programming file resolve, and will resolve after programming file, according to different target
The address that FPGA is corresponding, is respectively stored in the zones of different in the external memory storage being connected with main FPGA；Data are needed into
The operation of row mainly includes three kinds:
(1), write configuration data command, show that this bag data are parts for configuration data, need to store to outside storage
Device 204, command analysis module 320 needs to judge which sheet target FPGA is this bag data belong to, and can send to memory read/write module
Write data, write address and written request signal；
(2), lower dress operation performs order, this order is that the lower tubulature of notice is managed module and started to perform down to fill, this order needs
After the configuration data receiver of all FPGA is complete, the most all after write chip external memory 203, this order determines every simultaneously
Whether target FPGA programs enable, enables and then represents that this sheet needs programming, does not enable and do not program it, it is achieved n sheet FPGA
Can arbitrarily be independently programmable；
(3), lower dress status inquiry command, this order is that the state to current programming is inquired about, and includes whether mistake occur
By mistake, progress, the address etc. of each chip are programmed.
Memory read/write module 330: this module completes the read-write to chip external memory 204,.The interface letter that this module includes
Number specifically include that write request, write address, write data, read request, reading initial address and the quantity of reading；When needing to write data, life
Make parsing module 320 according to currently providing data to be write and address；When needing to read data, lower tubulature reason scheduler module 340
Only providing the initial address of reading and need the data volume read, specifically read operation and address offset to memorizer calculate by this
Module completes.
Lower tubulature reason scheduler module 340: this module complete lower dress is performed module 351,352,353 control, overall under
The control of threading degree and scheduling；After receiving the lower dress order of command analysis module, start lower dress, and record the progress of dress；
First module calculates, according to the return signal that lower dress performs module 351,352,353, the data that this every FPGA needs to read
Amount, reading address etc., be successively read the data that each target FPGA needs afterwards from external memory storage 204, and be buffered in each
RAM341,342,343 in, after the FPGA configuration data that be there is a need to perform down fill reads, dress performs mould downwards
Block 340 sends ready for data signal and write order；After lower dress execution module 351,352,353 writes bag data, downwards
Tubulature reason scheduler module 340 sends data read request and reads initial address, and lower tubulature reason scheduler module 340 waits that all lower dresses are held
After row module 351,352,353 all sends read request, calculating this every FPGA needs the data volume of reading, reads address etc.；As
This circulation, complete to programming.
Lower dress performs module 351,352,353: be divided into upper and lower two-layer, upper strata be initializes, wipe, programming etc. operates, under
Layer is protocol conversion module, writes data to target FPGA, and obtains read back information from target FPGA；Lower dress execution module 351,
352, after the 353 lower dresses receiving lower tubulature reason scheduler module 340 start order, perform initialization successively, wipe, program, according to
Agreement calculates address and the data volume reading data in configuration file, and sends write order sum to lower-layer protocols modular converter
According to；Lower-layer protocols modular converter will be ordered or data write target FPGA, and obtain read back information from target FPGA；Lower dress agreement
Modular converter needs to determine according to the communication protocol type of target FPGA, can be SPI, JTAG etc..
All lower dresses perform module and are programmed work simultaneously, and programing work is the ring that in all operations, elapsed time is the longest
Joint, the technique scheme provided by embodiment, the executed in parallel of programming of multiple target FPGA can be allowed, it is achieved that real
Multiple programming, improve lower dress speed.
Use the above-mentioned optimal technical scheme that the present embodiment provides, it is possible to use high-speed memory, and utilize FPGA data
Processing speed is fast, the advantage of parallel work-flow, it is achieved the high-speed parallel program of different target FPGA；And each FPGA being loaded
Separate, monolithic programming multi-disc can load again simultaneously, and the multiple programming for dissimilar FPGA can be completed,
The motility of raising system.
As it is shown on figure 3, the present embodiment additionally provides a kind of method to the programming of multi-disc target FPGA, the method includes:
S101, generated by computer and program file accordingly: determine the target needing programming in multi-disc target FPGA
FPGA, is generated by computer and programs file accordingly；
S102: sent by Ethernet and program file accordingly: by programming file corresponding for target FPGA of needs programming
Send to main FPGA；
S103, to main FPGA send start program command and enable signal: to main FPGA send start program command and with
Need the enable signal that target FPGA of programming is corresponding；
S104: described target FPGA is programmed: respectively target FPGA is programmed, and multi-disc target FPGA with
Communication mode between main FPGA selects at least one of which from communication.
Therefore, use technique scheme, can realize using different communication between target FPGA by main FPGA
Agreement, can complete to program dissimilar target devices；Improve the range of application of product.
Preferably, method also includes:
S105, the programming progress of inquiry target FPGA and/or state: inquiry needs the programming progress of target FPGA of programming
And/or state；
S106, by programming progress and/or feedback of status to described computer: being programmed into of target FPGA of programming will be needed
Degree and/or feedback of status are to computer.
Therefore, use above-mentioned further preferred technical scheme, can more preferably monitoring objective FPGA programming state, even if
Programming process occurs abnormality, also can know in time；Avoid follow-up maloperation.
Use in the above-mentioned preferred version that the present embodiment provides: the computer communication mode by Ethernet, it would be desirable to compile
The programming file that target FPGA of journey is corresponding sends to main FPGA.It is thereby achieved that the long-range programming to multi-disc target FPGA.
Use in the above-mentioned preferred version that the present embodiment provides: be respectively adopted point-to-point logical between main FPGA and target FPGA
Believe, and communication includes SPI and JTAG；And it is programmed target FPGA using and individually programs or same
Time programming mode carry out.
Preferably, in above-mentioned steps S104: main FPGA receives the programming file that target FPGA needing to program is corresponding, first
To programming file resolve, and will resolve after programming file, according to the address that different target FPGA is corresponding, be respectively stored in
In zones of different in the external memory storage being connected with main FPGA；And call respectively program file accordingly according to enabling signal,
Target FPGA needing programming is programmed.Therefore, it is possible to use high-speed memory, and utilize FPGA data processing speed
Hurry up, the advantage of parallel work-flow, it is achieved the high-speed parallel program of different target FPGA；And each FPGA being loaded is the most only
Vertical, monolithic programming multi-disc can load again simultaneously, and the multiple programming for dissimilar FPGA can be completed, improve system
The motility of system.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each method embodiment can be led to
The hardware crossing programmed instruction relevant completes.Aforesaid program can be stored in a computer read/write memory medium.This journey
Sequence upon execution, performs to include the step of above-mentioned each method embodiment；And aforesaid storage medium includes: ROM, RAM, magnetic disc or
The various media that can store program code such as person's CD.
Last it should be noted that described above is only highly preferred embodiment of the present invention, not the present invention is appointed
What pro forma restriction.Any those of ordinary skill in the art, in the range of without departing from technical solution of the present invention, the most available
Technical solution of the present invention is made many possible variation and simple replacement etc. by the way of the disclosure above and technology contents, these
Broadly fall into the scope of technical solution of the present invention protection.
Claims (10)
1. one kind to multi-disc target FPGA programming method, it is characterised in that described multi-disc target FPGA respectively with main FPGA phase
Even, described main FPGA is able to receive that external data；Described method includes:
Determine target FPGA needing programming in described multi-disc target FPGA, generated by computer and program file accordingly；
Programming file corresponding for described target FPGA needing to program is sent to described main FPGA；
Send to described main FPGA and start program command and the enable signal corresponding with described target FPGA needing to program；
Respectively described target FPGA is programmed, and the communication mode between described multi-disc target FPGA and described main FPGA
At least one of which is selected from communication.
Method the most according to claim 1, it is characterised in that described method also includes: inquire about the mesh of described needs programming
The programming progress of mark FPGA and/or state, and the programming progress of target FPGA programmed by described needs and/or feedback of status are extremely
Described computer.
Method the most according to claim 1, it is characterised in that the described computer communication mode by Ethernet, by institute
State programming file corresponding to target FPGA needing to program to send to described main FPGA.
Method the most according to claim 1, it is characterised in that be respectively adopted between described main FPGA and described target FPGA
Point-to-point communication, and described communication includes SPI and JTAG；And it is programmed adopting to described target FPGA
Carry out by the mode individually programming or programming simultaneously.
Method the most according to claim 1, it is characterised in that described main FPGA receives the described target needing programming
Programming file corresponding for FPGA, first resolves described programming file, and will resolve after programming file, according to different target
The address that FPGA is corresponding, is respectively stored in the zones of different in the external memory storage being connected with described main FPGA；And according to institute
State enable signal to call respectively and program file accordingly, target FPGA needing programming is programmed.
6. the device to the programming of multi-disc target FPGA, it is characterised in that described device includes:
Multi-disc target FPGA, is respectively used to different targeted execution unit executive control operations；
The main FPGA being connected with described multi-disc target FPGA, described main FPGA are provided with receiving the transceiver module of external data
With the command analysis module resolving described external data, described external data includes that target FPGA that needs program is corresponding
Programming file, the enable signal corresponding with described target FPGA and start program command；
Wherein, described main FPGA is additionally provided with lower tubulature reason scheduler module, and described lower tubulature reason scheduler module can be to described mesh
Mark FPGA sends correspondence therewith and programs the communication mode between file, and described multi-disc target FPGA and described main FPGA from many
Plant and communication mode selects at least one of which.
Device the most according to claim 6, it is characterised in that described lower tubulature reason scheduler module can also inquire about described need
The programming progress of target FPGA to be programmed and/or state, and by described need programming target FPGA programming progress and/or
Feedback of status is to the peripheral hardware being connected with described main FPGA.
Device the most according to claim 6, it is characterised in that the transceiver module in described main FPGA passes through Ethernet and meter
Calculation machine connects, and described computer generates and programs file accordingly.
Device the most according to claim 6, it is characterised in that be respectively adopted between described main FPGA and described target FPGA
Point-to-point communication, and described communication includes SPI and JTAG；And it is programmed adopting to described target FPGA
Carry out by the mode individually programming or programming simultaneously.
Device the most according to claim 6, it is characterised in that described main FPGA receives the described target needing programming
Programming file corresponding for FPGA, described programming file is first resolved by described command analysis module, and will resolve after programming
File, according to the address that different target FPGA is corresponding, is respectively stored in the external memory storage being connected with described main FPGA not
With in region；Described lower tubulature reason scheduler module is called respectively according to described enable signal and is programmed file accordingly, compiles needs
Target FPGA of journey is programmed.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107255975A (en) * | 2017-07-21 | 2017-10-17 | 中国电子科技集团公司第二十九研究所 | A kind of utilization high-speed bus realizes the device and method that FPGA programs are quickly loaded |
| CN107944140A (en) * | 2017-11-24 | 2018-04-20 | 中科亿海微电子科技（苏州）有限公司 | The synchronous FPGA system and method for matching somebody with somebody code |
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| CN108181861A (en) * | 2018-03-19 | 2018-06-19 | 浙江国自机器人技术有限公司 | A kind of control system |
| CN108628798A (en) * | 2017-03-20 | 2018-10-09 | 大唐移动通信设备有限公司 | The method and FPGA of a kind of board, chip load configuration information |
| CN109388413A (en) * | 2017-08-03 | 2019-02-26 | 中车株洲电力机车研究所有限公司 | A kind of FPGA method for updating program and system |
| CN109446122A (en) * | 2018-09-30 | 2019-03-08 | 新华三技术有限公司 | The access method and communication equipment of programming device |
| CN110175056A (en) * | 2019-05-30 | 2019-08-27 | 西安微电子技术研究所 | A kind of control device and control method of heterogeneous platform Remote Dynamic load multiple target FPGA |
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| CN106682296A (en) * | 2016-12-19 | 2017-05-17 | 西安微电子技术研究所 | FPGA oriented multi-way universal configuration loading control system and method |
| CN108628798A (en) * | 2017-03-20 | 2018-10-09 | 大唐移动通信设备有限公司 | The method and FPGA of a kind of board, chip load configuration information |
| CN107255975A (en) * | 2017-07-21 | 2017-10-17 | 中国电子科技集团公司第二十九研究所 | A kind of utilization high-speed bus realizes the device and method that FPGA programs are quickly loaded |
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| CN109388413A (en) * | 2017-08-03 | 2019-02-26 | 中车株洲电力机车研究所有限公司 | A kind of FPGA method for updating program and system |
| CN107944140A (en) * | 2017-11-24 | 2018-04-20 | 中科亿海微电子科技（苏州）有限公司 | The synchronous FPGA system and method for matching somebody with somebody code |
| CN108108316A (en) * | 2017-12-14 | 2018-06-01 | 上海斐讯数据通信技术有限公司 | A kind of Interface Expanding method and system based on field programmable gate array |
| CN108108316B (en) * | 2017-12-14 | 2023-08-11 | 珠海西格电力科技有限公司 | Interface expansion method and system based on field programmable gate array |
| CN108181861A (en) * | 2018-03-19 | 2018-06-19 | 浙江国自机器人技术有限公司 | A kind of control system |
| CN109446122A (en) * | 2018-09-30 | 2019-03-08 | 新华三技术有限公司 | The access method and communication equipment of programming device |
| CN110175056A (en) * | 2019-05-30 | 2019-08-27 | 西安微电子技术研究所 | A kind of control device and control method of heterogeneous platform Remote Dynamic load multiple target FPGA |
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