CN109388413A - A kind of FPGA method for updating program and system - Google Patents
A kind of FPGA method for updating program and system Download PDFInfo
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- CN109388413A CN109388413A CN201710655725.8A CN201710655725A CN109388413A CN 109388413 A CN109388413 A CN 109388413A CN 201710655725 A CN201710655725 A CN 201710655725A CN 109388413 A CN109388413 A CN 109388413A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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Abstract
This application discloses a kind of FPGA method for updating program, master control borad receives the target program to be written of each FPGA sent by debugging terminal；The remote control command of the debugging terminal is received, the target program to be written is sent respectively to the FPGA by the master control borad；The program of the FPGA updates IP kernel and the target program to be written received is written to carry out program update in flash, and described program updates IP kernel and is set in advance in the FPGA.The application passes through Telnet master control borad, it is written into target program and is sent to the corresponding FPGA from plate, and then the program by being set in advance in FPGA updates IP kernel, be written into the flash of target program write-in FPGA, the update of single-point program is realized, update operation is greatly simplified.Disclosed herein as well is a kind of FPGA program updating systems, equally have above-mentioned beneficial effect.
Description
Technical field
This application involves electronic technology field, in particular to a kind of FPGA method for updating program and system.
Background technique
With the development of information technology, the intelligent level of Train Communication Network is continuously improved, used in Related product
FPGA it is also more and more.
Train Communication Network is mainly used for durings Train Control, Stateful Inspection, fault diagnosis, vehicle-mounted information service etc.
Data transmission, be known as being train " brain " and " nerve ".During development and application, due to demand variation or
Person is the self-defect of program in FPGA, it is often necessary to optimize update to FPGA program.
However, it is often a job very troublesome that the optimization of FPGA program, which updates, on train.This is because maintenance people
Member generally requires to disassemble the correlation module on train, utilizes the control panel and the dedicated emulation downloader of FPGA in module
The downloading for carrying out new procedures updates, and reinstalls correlation module after completing downloading and updating.Therefore, a large amount of time will disappear
Consumption is in disassembly and installation module.With the increase of FPGA application amount on train, for maintenance personnel, FPGA program is more
It will be newly undoubtedly a huge workload.
For this problem, a solution is proposed in the prior art.Referring to FIG. 1, Fig. 1 is to provide in the prior art
The schematic diagram of FPGA method for updating program by the CPU of control panel, getting target program to be written in the method
After (generally * .bin file), it is written into the flash of FPGA, so as to after control panel powers on or restarts next time,
FPGA loads new procedures from flash and realizes that optimization updates.
Although the prior art shown in FIG. 1 can to avoid a large amount of disassembly and installation work, whenever needing to update one
When the program of a FPGA, require to be operated on the control panel of the FPGA, therefore, when control panel quantity is more, work
It measures still very greatly, needs to further increase.
Summary of the invention
The application's is designed to provide a kind of FPGA method for updating program and system, to carry out FPGA simple and conveniently
Program updates, and reduces workload.
In order to solve the above technical problems, the application provides a kind of FPGA method for updating program, comprising:
Master control borad receives the target program to be written of each FPGA sent by debugging terminal；
The remote control command of the debugging terminal is received, the master control borad sends the target program to be written respectively
To the FPGA；
The program of the FPGA updates IP kernel and the target program to be written received is written in flash to carry out program
It updates, described program updates IP kernel and is set in advance in the FPGA.
Optionally, before the target program to be written is sent respectively to the FPGA by the master control borad further include:
The master control borad and the FPGA carry out handshake process；
If shaking hands success, the subsequent the step of target program to be written is sent respectively to the FPGA is executed.
Optionally, the target program to be written is sent respectively to the FPGA and includes: by the master control borad
The frame data of the target program to be written are sent to the FPGA by the master control borad；
The described program of the FPGA updates IP kernel and carries out CRC check；
The master control borad obtains the check results of the CRC check；If the check results mistake, to FPGA weight
The new frame data for sending check results mistake；If the check results are correct, continue to send to the FPGA next
Frame data, until the target program to be written of the FPGA is sent.
Optionally, the master control borad obtains the check results of the CRC check and includes:
The master control borad inquires the effective register of ack msg of the FPGA；
If non-empty, the ack msg of the FPGA is read；
If the ack msg mistake, the check results mistake；
If the ack msg is correct, the check results are correct.
Optionally, the FPGA program update IP kernel by the target program to be written received be written flash in so as to
Carrying out program update includes:
The described program of the FPGA updates IP kernel and carries out erasing operation to the flash；
Described program updates IP kernel and the frame data of the target program to be written received is written in the flash；
Described program updates the frame data being written in flash described in IP kernel readback；And judge that the frame data of the readback are
It is no consistent with frame data that are receiving；
If it is not, then the frame data received are written in the flash again；
If so, continuing the next frame data received to be written in the flash, until the target journey to be written
Sequence is written in the flash and finishes.
Present invention also provides a kind of FPGA program updating systems, comprising:
Master control borad: for receiving the target program to be written of each FPGA sent by debugging terminal；Receive the debugging
The target program to be written is sent respectively to the FPGA by the remote control command of terminal；
The FPGA: for by program update IP kernel by the target program to be written received be written flash in so as to
Program update is carried out, described program updates IP kernel and is set in advance in the FPGA.
Optionally, the master control borad is also used to:
Before the target program to be written is sent respectively to the FPGA, handshake process is carried out with the FPGA；
If shaking hands success, the subsequent the step of target program to be written is sent respectively to the FPGA is executed.
Optionally, the master control borad is specifically used for:
The frame data of the target program to be written are sent to the FPGA；It obtains the FPGA and carries out CRC check
Check results；If the check results mistake, the frame data of check results mistake are retransmitted to the FPGA；If institute
It is correct to state check results, then continues to send next frame data to the FPGA, until the target program to be written of the FPGA
It is sent；
The FPGA is specifically used for:
After receiving the frame data that the master control borad is sent, IP kernel is updated by described program and carries out the school CRC
It tests.
Optionally, the master control borad is specifically used for:
When obtaining the check results of the CRC check, the effective register of ack msg of the FPGA is inquired；If non-empty,
Then read the ack msg of the FPGA；If the ack msg mistake, the check results mistake；If the ack msg is just
Really, then the check results are correct.
Optionally, the FPGA is specifically used for:
IP kernel is updated by described program, erasing operation is carried out to the flash；
The frame data of the target program to be written received are written in the flash；
The frame data being written in flash described in readback, and judge the readback frame data whether with the frame number that receives
According to consistent；
If it is not, then the frame data received are written in the flash again；
If so, continuing the next frame data received to be written in the flash, until the target journey to be written
Sequence is written in the flash and finishes.
In FPGA method for updating program provided herein, master control borad receives each FPGA's sent by debugging terminal
Target program to be written；The remote control command of the debugging terminal is received, the master control borad is by the target program to be written
It is sent respectively to the FPGA；The program of the FPGA updates IP kernel and the target program to be written received is written in flash
To carry out program update, described program updates IP kernel and is set in advance in the FPGA.
Compared with the prior art, in FPGA method for updating program provided herein, using network by the to be written of FPGA
Enter target program and be sent to master control borad, and by Telnet, master control borad is enabled to distinguish received target program to be written
Be sent to each FPGA, by the program of FPGA update IP kernel again will received target program to be written be written in flash with
Just the update of program is carried out.The use of IP kernel is updated with program due to remotely controlling, method provided herein only need to be in net
Debugging is carried out on a debugging port in network can be completed all operations, that is, realize the update of single-point program.It can be seen that this
FPGA method for updating program provided by applying can effectively simplify to the largely program of the FPGA more new task from plate, significantly
Improve working efficiency in ground.Above-mentioned FPGA method for updating program may be implemented in FPGA program updating system provided herein, together
Sample has above-mentioned beneficial effect.
Detailed description of the invention
In order to illustrate more clearly of the technical solution in the prior art and the embodiment of the present application, below will to the prior art and
Attached drawing to be used is needed to make brief introduction in the embodiment of the present application description.Certainly, in relation to the attached drawing of the embodiment of the present application below
A part of the embodiment in only the application of description is not paying creativeness to those skilled in the art
Under the premise of labour, other attached drawings can also be obtained according to the attached drawing of offer, other accompanying drawings obtained also belong to the application
Protection scope.
Fig. 1 is the schematic diagram of provided FPGA method for updating program in the prior art；
Fig. 2 is a kind of flow chart of FPGA method for updating program provided by the embodiment of the present application；
Fig. 3 is the exemplary diagram of master control borad provided by the embodiment of the present application with the FPGA communication process from plate；
Fig. 4 is the stream that program provided by the embodiment of the present application updates that IP kernel is written into target program write-in flash
Journey exemplary diagram；
Fig. 5 is a kind of structural block diagram of FPGA program updating system provided herein；
Fig. 6 updates IP kernel communication signal for the program in a kind of FPGA program updating system provided by the embodiment of the present application
Figure；
Fig. 7 is a kind of system architecture schematic diagram of FPGA program updating system provided herein.
Specific embodiment
In order to which technical solutions in the embodiments of the present application is more clearly and completely described, below in conjunction with this Shen
Please attached drawing in embodiment, technical solutions in the embodiments of the present application is introduced.Obviously, described embodiment is only
Some embodiments of the present application, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall in the protection scope of this application.
Referring to FIG. 2, Fig. 2 is a kind of flow chart of FPGA method for updating program provided by the embodiment of the present application, mainly
The following steps are included:
Step 201: master control borad receives the target program to be written of each FPGA sent by debugging terminal.
In the FPGA method for updating program provided by the embodiment of the present application, by realizing that single-point updates institute in completion system
There is the program more new task of the FPGA from plate, to simplify entire more new task, improves working efficiency.Specifically, the master in system
Controlling plate all can access realization interconnection in network by interchanger, then the operation that single-point updates can be in a debugging of interchanger
It is realized on port.
When FPGA program updates in carry out system, it is necessary first to obtain the target journey to be written of each FPGA from plate
Sequence.Specifically, the object code to be written (generally * .bin file) of each FPGA generates it by tools chain through designer
Afterwards, it can be sent to corresponding master control borad from the debugging terminal that access switch debugs port, to carry out subsequent journey
Sequence updates operation.
Step 202: receiving the remote control command of debugging terminal, master control borad is written into target program and is sent respectively to
FPGA。
After the target program to be written for getting FPGA by step 201, master control borad can be remotely logged into；And master control
Plate is written into target and is sent respectively to corresponding FPGA, so as to each after the remote control command for receiving debugging terminal
FPGA completes the update operation of program.Specifically, it is written into before target program is sent to FPGA in master control borad, it can also be first
Handshake process is carried out, to prevent maloperation, if shaking hands success, then executes the step of sending target program to be written to FPGA.
Also, rate is forbidden to maloperation in order to further increase, can also carry out multiple handshake process, those skilled in the art can be with
It voluntarily selects and is arranged according to actual use situation, the application is not limited thereto.
It should be noted that multiple FPGA correspond to a master control borad in system, it is total by bus such as CPCI between the two
Line realizes communication, and certainly, data communication between the two will be carried out according to certain communication protocol.Fig. 3 gives in the application
A kind of preferred embodiment of communication process, detailed content just can no longer be introduced here with reference to content shown in Fig. 3.
The program of step 203:FPGA updates IP kernel and the target program to be written received is written in flash to carry out
Program updates.
By step 202, after each FPGA has received respective target program to be written, IP can be updated by program
Core (intellectual property core), by such as spi bus of the control bus between FPGA and flash, this is waited for
Write-in target program is written in flash, to power in next time or when system reboot, is automatically performed FPGA's by flash
Program updates.Certainly, the flash can be the flash inside FPGA, or FPGA plug-in flash, the application couple
This is not defined.
Program mentioned here updates IP kernel, is integration module pre-designed, that program more new function may be implemented,
And be set in advance in FPGA, it can be realized under the timing control of internal element to the configuration of flash and program write-in.
Flash must be carried out in normal work in strict accordance with the control sequential (such as spi bus timing) of flash, program
Updating in IP kernel can be set flash time-sequence control module, in two finite state machines, that is, to write flash state machine and reading
Write and read is carried out to flash under the control of flash state machine.Since the write operation of flash can only rewrite data 1 as 0, and
Data 0 can be rewritten as 1 by erasing operation.Therefore, it before each write-in program data, first has to carry out erasing behaviour to flash
Make, specified region is written as 1 entirely, is then written into again in target program write-in flash, to power on or restart in next time
When, FPGA, which loads new procedures from flash and realizes, to be updated.
As it can be seen that, by Telnet technology, enabling master control borad in FPGA method for updating program provided by the embodiment of the present application
After the target program to be written for receiving each FPGA, it is written into target program and is sent respectively to corresponding FPGA again, and
IP kernel is updated using the program being pre-configured in FPGA, is written into target program write-in flash to carry out program
It updates.It can be seen that method provided by the embodiment of the present application carry out it is each from the FPGA program of plate update when because remotely
Login techniques and program update the use of IP kernel, whole only a debugging port on switches to be needed to be operated, that is, realize
Single-point update, therefore can greatly simplify update operation, improve working efficiency.
Further, since it is each from plate FPGA by program update IP kernel complete flash in new procedures write-in, because without
It is debugged, and then can be asked to avoid timing when causing to communicate with flash because of CPU timing control shakiness using from plate CPU
Topic.Moreover, program, which updates IP kernel, is applicable not only to CPU class from plate, the slave plate of I/O class can be applicable to, so that this Shen
Please FPGA method for updating program provided by embodiment applicability it is higher.
Referring to FIG. 3, Fig. 3 is the example of master control borad provided by the embodiment of the present application with the FPGA communication process from plate
Figure.
As shown in figure 3, master control borad and from handshake process can be carried out between plate first, it may be assumed that mainboard flag0 is written in master control borad
After be sent to from plate, receive from plate after reading, if can carry out remotely updating operation, be just written from plate flag0, then by leading
It controls plate to read, then success of this time shaking hands, and is reset after being read.It can so be utilized again by master control borad and from plate respective
Flag1 and flag2 carries out handshake process twice again.If three-way handshake success, can exclude the possibility of maloperation substantially, with
Just the subsequent operation for sending target program to be written is executed.
After shaking hands successfully, master control borad the target program to be written received can be sent to as unit of frame with it is right
The slave plate FPGA answered.Specifically, master control borad is to the frame number for sending target program to be written from the buffer area DPRAM of plate FPGA
According to, and a frame data are finished to the flag bit set of register, to indicate that the frame data are sent.And this is being received from plate
After frame data, program updates IP kernel and just carries out CRC check, and updates ack msg according to check results, while ACK number is written
According to effective register, indicate that ack msg has update.Then, when the effective register of master control borad periodicity poll reading ack msg,
It can be learnt that ack msg has been updated, ack msg just is read after removing the effective register of ack msg, and judged:
If ack msg mistake, i.e. CRC check mistake, then master control borad sends the frame data to from plate again；If ack msg is correct, i.e.,
CRC check is correct, then from the flash that FPGA further is written in the frame data by plate, to carry out program update, and master control borad
Continue to send next frame data to from plate, until the program to be written is sent.It is sent out in the target program to be written of the FPGA
It send after finishing, data can all be updated the flag bit set of register by master control borad, to learn from plate.
Referring to Fig. 4, Fig. 4 is that the update IP kernel of program provided by the embodiment of the present application is written into target program write-in
Flow example figure in flash.
As shown in figure 4, program updates IP kernel during flash is written in each frame data for being written into target program,
It mainly comprises the steps that
Step 401: receiving the frame data of target program to be written.
Step 402: erasing operation is carried out to flash.
Specifically, it before being operated to flash, needs to choose the flash first, that is, drags down its chip selection signal, so
Effectively write under the idle state of flash state machine afterwards it is enabled, so as to next writing commands and data into flash.As before
It is described, before target program to be written is written, need to carry out erasing operation to flash, therefore, it is necessary to by being written to wiping
Except instruction is to execute the erasing operation to flash.
Step 403: being written into the frame data write-in flash of target program according to the control sequential of flash.
After by step 402, program, which updates IP kernel, the frame number received is written to the flash for completing erasing
According to.Specifically, it needs to undergo transmission address state and transmission two state procedures of data mode, transmission when carrying out data write-in
In address state, program updates IP kernel and frame data storage address to be written is transmitted to flash, and in transmission data mode
In, program updates IP kernel and the frame data is just written to its storage address to be written.
Step 404: the frame data in flash are written in readback.
In order to ensure being correctly written in for every frame data, after writing a frame data, can be written in flash with readback
Frame data, and compared with the frame data of target program to be written originally, the correctness of write-in content verified.
Step 405: whether frame data and the frame data to be written for comparing readback are consistent；If it is not, being then back to step
402, if so, entering step 406.
If the frame data of readback and frame data originally to be written are inconsistent, illustrate that writing process malfunctions, then can return
It is back to step 402, a series of subsequent steps such as erasing are executed, to re-write the frame data.
Step 406: judging whether target program to be written is written and finish, if it is not, being then back to step 401.
After flash is written in a frame data, it can be determined that whether target program to be written is written and finishes at this time, if not yet
It finishes, then needs to be back to step 401, continue to next frame data, and execute subsequent step, until target journey to be written
Sequence is written in flash and finishes.
FPGA program updating system provided by the embodiment of the present application is introduced below.FPGA program described below
More new system can correspond to each other reference with above-described FPGA method for updating program.
Referring to Fig. 5, Fig. 5 is a kind of structural block diagram of FPGA program updating system provided herein；Mainly include
Master control borad 501 and FPGA 502 corresponding with master control borad 501.
Master control borad 501 is mainly used for receiving the target program to be written of each FPGA 502 sent by debugging terminal；And
The remote control command for receiving debugging terminal, is written into target program and is sent respectively to FPGA 502.
Specifically, when being written into target program and being sent to FPGA 502, master control borad 501 can be specifically used for will be to be written
Enter target program and be sent to FPGA 502 as unit of frame, and by judging to write after FPGA 502 carries out CRC check to frame data
The ack msg entered, come judge the frame data whether transmission success, if it is not, then master control borad 501 be specifically used for again to FPGA 502
The frame data are sent, if so, master control borad 501 is specifically used for sending next frame data to FPGA 502, until target to be written
Program is sent.
In addition, master control borad 501 before being written into target program and being sent to FPGA 502, can be also used for and FPGA
502 carry out handshake process, to prevent maloperation.
FPGA 502 corresponding with master control borad 501 is mainly used for the target program to be written received being written in flash
To carry out program update.
Specifically, FPGA 502 can use the program that pre-sets and update IP kernel, according to the control sequential of flash,
After completing to the erasing operation of flash, the frame data for being written into target program, which are written in flash, corresponds to storage
Region.Also, in order to ensure being correctly written in for data, after writing every frame data, program updates IP kernel can readback again
The frame data having been written into, and whether judge it consistent with data originally to be written, if it is not, the frame data are then re-write,
If so, next frame data can be continued to write to, until the target program to be written of the FPGA is written in flash and finishes.
Referring to Fig. 6, Fig. 6 updates IP for the program in a kind of FPGA program updating system provided by the embodiment of the present application
Core communication scheme.
Program as shown in FIG. 6 updates in IP kernel communication scheme, between plate FPGA and master control borad, is pressed by cpci bus
It is communicated according to the interface protocol pre-set；From between plate FPGA and flash, communicated by spi bus.In order to prevent
With the maloperation in master control borad communication process, program updates IP kernel and is provided with control unit of shaking hands, for before program transportation
Handshake process is carried out with master control borad, shakes hands and successfully then carries out the transmission of target program to be written.The data that program updates IP kernel are slow
Memory cell is used to cache the frame data from the received target program to be written of master control borad, and CRC check unit is used for frame data
Reception carry out CRC check continue to transmit next frame data, otherwise transmit the frame data again if check results are correct.Shape
State feedback unit is for reading handshake process, CRC check and data readback comparison result, so that instruction generation unit generates phase
The instruction answered.Data transmission unit is used in the frame data transmission write-in flash by data buffer storage unit；Data readback is more single
Member is compared for the frame data in readback write-in flash with the former frame data in data buffer storage unit, if unanimously,
Next frame data are continued to write to, are otherwise re-write.Also, above mentioned instruction generation unit, data transmission unit sum number
It according to the work of readback comparing unit, is carried out under the timing control of flash timing control unit.
Referring to Fig. 7, Fig. 7 is a kind of system architecture schematic diagram of FPGA program updating system provided herein.
As shown in fig. 7, the master control borad in system realizes the network interconnection by interchanger, master control borad receives each from plate
After the target program to be written (i.e. * .bin file) of FPGA, can under the long-range control of debugging terminal, by cpci bus and
It is corresponding it is each communicated from plate FPGA, i.e., transmit target program to be written to FPGA.Wherein, described to be from plate
CPU class is from plate, or I/O class is from plate.It is each be provided with from plate FPGA program update IP kernel, can by spi bus,
According to the control sequential of flash, it is written into target program and is written in flash again, so as to after next time powers on or restarts,
FPGA loads new procedures from flash and realizes that optimization updates.
Each embodiment is described in a progressive manner in the application, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.For system disclosed in embodiment
Speech, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is referring to method part illustration
?.
Professional further appreciates that, method and step described in conjunction with the examples disclosed in this document, energy
The combination with electronic hardware, computer software or the two is reached to realize, in order to clearly demonstrate the interchangeable of hardware and software
Property, each exemplary composition and step are generally described according to function in the above description.These functions are actually with hard
Part or software mode execute, the specific application and design constraint depending on technical solution.Professional technician can be with
Each specific application is used different methods to achieve the described function, but this realization is it is not considered that exceed this Shen
Range please.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can directly be held with hardware, processor
The combination of capable software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
Finally, it should be noted that, in present specification, the relational terms of such as " first " and " second " etc, only
Only it is used to distinguish an entity or operation with another entity or operation, without necessarily requiring or implying this
There are any actual relationship or orders between a little entities or operation.In addition, the terms "include", "comprise" or its
His any variant, it is intended that non-exclusive inclusion is not precluded among described process, method, article or equipment etc., also
It include the element that other are not explicitly listed.
Technical solution provided herein is described in detail above.Specific case used herein is to this Shen
Principle and embodiment please is expounded, the present processes that the above embodiments are only used to help understand and its
Core concept.It should be pointed out that for those skilled in the art, in the premise for not departing from the application principle
Under, can also to the application, some improvement and modification can also be carried out, these improvement and modification also fall into the protection of the claim of this application
In range.
Claims (10)
1. a kind of FPGA method for updating program characterized by comprising
Master control borad receives the target program to be written of each FPGA sent by debugging terminal；
The remote control command of the debugging terminal is received, the target program to be written is sent respectively to institute by the master control borad
State FPGA；
The program of the FPGA updates IP kernel and the target program to be written received is written in flash to carry out program more
Newly, described program updates IP kernel and is set in advance in the FPGA.
2. FPGA method for updating program according to claim 1, which is characterized in that in the master control borad by the mesh to be written
Beacon course sequence is sent respectively to before the FPGA further include:
The master control borad and the FPGA carry out handshake process；
If shaking hands success, the subsequent the step of target program to be written is sent respectively to the FPGA is executed.
3. FPGA method for updating program according to claim 2, which is characterized in that the master control borad is by the target to be written
Program is sent respectively to the FPGA
The frame data of the target program to be written are sent to the FPGA by the master control borad；
The described program of the FPGA updates IP kernel and carries out CRC check；
The master control borad obtains the check results of the CRC check；If the check results mistake, sends out again to the FPGA
Send the frame data of check results mistake；If the check results are correct, continue to send next frame number to the FPGA
According to until the target program to be written of the FPGA is sent.
4. FPGA method for updating program according to claim 3, which is characterized in that the master control borad obtains the CRC check
Check results include:
The master control borad inquires the effective register of ack msg of the FPGA；
If non-empty, the ack msg of the FPGA is read；
If the ack msg mistake, the check results mistake；
If the ack msg is correct, the check results are correct.
5. FPGA method for updating program according to claim 3, which is characterized in that the program of the FPGA, which will update IP kernel, to be connect
Include: to carry out program update in the target program to be written write-in flash received
The described program of the FPGA updates IP kernel and carries out erasing operation to the flash；
Described program updates IP kernel and the frame data of the target program to be written received is written in the flash；
Described program updates the frame data being written in flash described in IP kernel readback；And judge the readback frame data whether with
The frame data received are consistent；
If it is not, then the frame data received are written in the flash again；
If so, continuing the next frame data received to be written in the flash, until the target program to be written exists
Write-in finishes in the flash.
6. a kind of FPGA program updating system characterized by comprising
Master control borad: for receiving the target program to be written of each FPGA sent by debugging terminal；Receive the debugging terminal
Remote control command, the target program to be written is sent respectively to the FPGA；
The FPGA: the target program to be written received is written in flash to carry out for updating IP kernel by program
Program updates, and described program updates IP kernel and is set in advance in the FPGA.
7. FPGA program updating system according to claim 6, which is characterized in that the master control borad is also used to:
Before the target program to be written is sent respectively to the FPGA, handshake process is carried out with the FPGA；If holding
Hand success, then execute the subsequent the step of target program to be written is sent respectively to the FPGA.
8. FPGA program updating system according to claim 7, which is characterized in that the master control borad is specifically used for:
The frame data of the target program to be written are sent to the FPGA；Obtain the verification that the FPGA carries out CRC check
As a result；If the check results mistake, the frame data of check results mistake are retransmitted to the FPGA；If the school
It is correct to test result, then continues to send next frame data to the FPGA, until the target program to be written of the FPGA is sent
It finishes；
The FPGA is specifically used for:
After receiving the frame data that the master control borad is sent, IP kernel is updated by described program and carries out CRC check.
9. FPGA program updating system according to claim 8, which is characterized in that the master control borad is specifically used for:
When obtaining the check results of the CRC check, the effective register of ack msg of the FPGA is inquired；If non-empty is read
Take the ack msg of the FPGA；If the ack msg mistake, the check results mistake；If the ack msg is correct,
The check results are correct.
10. FPGA program updating system according to claim 9, which is characterized in that the FPGA is specifically used for: by described
Program updates IP kernel, carries out erasing operation to the flash；Described in frame data write-in by the target program to be written received
In flash；The frame data being written in flash described in readback, and judge the readback frame data whether with the frame number that receives
According to consistent；If it is not, then the frame data received are written in the flash again；If so, continuing to receive down
One frame data is written in the flash, until the target program to be written is written in the flash and finishes.
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| CN112650518A (en) * | 2019-10-10 | 2021-04-13 | 国创新能源汽车能源与信息创新中心(江苏)有限公司 | DSP program on-line upgrading method |
| CN115840579A (en) * | 2023-02-14 | 2023-03-24 | 合肥安迅精密技术有限公司 | FPGA remote updating method, system, chip mounter and storage medium |
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