CN107870775A - A kind of update method of processor and BootLoader program - Google Patents

A kind of update method of processor and BootLoader program Download PDF

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Publication number
CN107870775A
CN107870775A CN201610851750.9A CN201610851750A CN107870775A CN 107870775 A CN107870775 A CN 107870775A CN 201610851750 A CN201610851750 A CN 201610851750A CN 107870775 A CN107870775 A CN 107870775A
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CN
China
Prior art keywords
nonvolatile memory
processor core
bootloader
controller
bootloader programs
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CN201610851750.9A
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Chinese (zh)
Inventor
周欣
周俊
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深圳市中兴微电子技术有限公司
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Priority to CN201610851750.9A priority Critical patent/CN107870775A/en
Publication of CN107870775A publication Critical patent/CN107870775A/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/60Software deployment
    • G06F8/65Updates
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/60Software deployment
    • G06F8/65Updates
    • G06F8/654Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/445Program loading or initiating

Abstract

The embodiment of the invention discloses a kind of processor, including:Processor core, controller and nonvolatile memory, processor core, for sending erasing indication signal, and the first bootload BootLoader programs in erasable nonvolatile memory to controller;It is additionally operable to receive the status signal from controller, status signal is used to indicate that nonvolatile memory is currently at writable state;Response status signals, the 2nd BootLoader programs are write into nonvolatile memory;Controller, for respond wipe indication signal, monitoring the first BootLoader programs whether erasure completion;After the first BootLoader program erasure completions are monitored, status signal is generated;Status signal is sent to processor core.The embodiment of the present invention also discloses a kind of update method of bootload BootLoader programs.

Description

A kind of update method of processor and BootLoader program

Technical field

The present invention relates to the bootload in embedded system (BootLoader) program, more particularly to a kind of processor and The update method of BootLoader programs.

Background technology

In embedded systems, BootLoader programs are the first paragraph codes that embedded system performs after power, Run before operating system nucleus operation, prepare suitable hardware environment for final call operation system kernel.Meanwhile BootLoader programs realize that different hardware platforms corresponds to different BootLoader journeys based on particular hardware platform Sequence.Thus it is guaranteed that the effective operation and upgrading of BootLoader programs are particularly important with reparation.

In the prior art, when BootLoader program storages are in Nand flash storages, embedded system updates During BootLoader programs, it is necessary to first by BootLoader program copies to random access memory (Random Access Memory, RAM) or Nor flash storages in, then BootLoader programs are write by Nand Flash storage by processor Device, renewal speed can be caused slower.

The content of the invention

In view of this, the embodiment of the present invention it is expected to provide the update method of a kind of processor and BootLoader programs, with Realize the renewal speed for accelerating BootLoader programs.

To reach above-mentioned purpose, the technical proposal of the invention is realized in this way:

In a first aspect, the embodiment of the present invention provides a kind of processor, including:Processor core, controller and non-volatile Property memory, the nonvolatile memory supports to perform in chip, operation can be written and read and can directly with the processor Core is connected, and the processor core is connected with the controller, and the controller is connected with the nonvolatile memory, its In, the processor core, for sending erasing indication signal to the controller, and wipe in the nonvolatile memory The first bootload BootLoader programs;It is additionally operable to receive the status signal from the controller, wherein, the state Signal is used to indicate that the nonvolatile memory is currently at writable state;The status signal is responded, by second BootLoader programs write the nonvolatile memory;The controller, for responding the erasing indication signal, monitoring The first BootLoader programs whether erasure completion;After the first BootLoader program erasure completions are monitored, Generate the status signal;The status signal is sent to the processor core.

Second aspect, the embodiment of the present invention provide a kind of update method of bootload BootLoader programs, are applied to Processor, wherein, the processor includes:Processor core, controller and nonvolatile memory, it is described non-volatile to deposit Reservoir is supported to perform in chip, can be written and read operation and directly can be connected with the processor core;Methods described includes:Obtain Data renewal instruction, wherein, the data more new command, non-volatile deposited for indicating that processor core renewal is described The first BootLoader programs in reservoir are the 2nd BootLoader programs;Perform the data more new command, generation erasing Indication signal;The erasing indication signal is sent to the controller, and wipes described the in the nonvolatile memory One BootLoader programs, wherein, the erasing indication signal is used to indicate first described in the monitoring control devices BootLoader programs whether erasure completion, and after the first BootLoader program erasure completions are monitored, generate shape State signal;The status signal from the controller is received, wherein, the status signal is described non-volatile for indicating Memory is currently at writable state;The status signal is responded, the 2nd BootLoader programs are write described non- Volatile memory.

The processor and the update method of BootLoader programs that the embodiment of the present invention is provided, processor include:Processing Device core, controller and nonvolatile memory, nonvolatile memory support chip in perform, can be written and read operation and Directly it can be connected with processor core.Processor core first sends erasing indication signal to controller, and erasable nonvolatile is deposited The first BootLoader programs in reservoir;Then, controller response erasing indication signal, monitors the first BootLoader programs Whether erasure completion;After the first BootLoader program erasure completions are monitored, status signal is generated, wherein, status signal For indicating that nonvolatile memory is currently at writable state, and status signal is sent to processor core;Finally, handle Device core response status signals, the 2nd BootLoader programs are write into nonvolatile memory.So, using the processor energy Enough accelerate the renewal speed of BootLoader programs.

Brief description of the drawings

Fig. 1 is the structural representation of the processor in the embodiment of the present invention;

Fig. 2 is the schematic flow sheet of the update method of the BootLoader programs in the embodiment of the present invention one;

Fig. 3 is the schematic flow sheet of the BootLoader programs of erasing the first in the embodiment of the present invention one;

Fig. 4 is the schematic flow sheet of the BootLoader programs of write-in the 2nd in the embodiment of the present invention one;

Fig. 5 is the structural representation of the system of the renewal BootLoader programs in the embodiment of the present invention two;

Fig. 6 is the schematic flow sheet of the update method of the BootLoader programs in the embodiment of the present invention three;

Fig. 7 is the structural representation of the processing unit in the embodiment of the present invention four.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes.

Embodiment one

The embodiment of the present invention provides a kind of processor, and Fig. 1 is the structural representation of the processor in the embodiment of the present invention, is joined As shown in Figure 1, the processor 10 includes:Processor core 101, controller 102 and nonvolatile memory 103;

Here, above-mentioned nonvolatile memory is supported to perform (XIP, eXecute In Place) in chip, can read Write operation and directly it can be connected with processor core, processor core is connected with controller, controller and nonvolatile memory Connection.

It should be noted that processor in the embodiment of the present invention is by processor core, controller and non-volatile deposits Reservoir is integrated in same chip, it is possible to reduce printed circuit board (PCB, Printed Circuit Board) each part cabling The coupled interference brought, increase the stability of processor.

In actual applications, processor core can be connected by the first controlling bus with controller, then pass through number respectively It is connected according to bus and address bus with nonvolatile memory, controller can be deposited by the second controlling bus with non-volatile Reservoir connects.

In actual applications, above-mentioned nonvolatile memory can be Nor flash storages, and above-mentioned processor core can Think central processing unit (CPU, Central Processing Unit) core.

With reference to the processor in above-described embodiment, the renewal to BootLoader programs provided in an embodiment of the present invention Method illustrates.

Fig. 2 is the schematic flow sheet of the update method of the BootLoader programs in the embodiment of the present invention one, referring to Fig. 2 institutes Show, this method includes:

S201:Processor core obtains data more new command;

Here, data more new command is used to indicate first in processor core renewal nonvolatile memory BootLoader programs are the 2nd BootLoader programs.

It should be noted that above-mentioned data more new command can generate according to the operation of user.Specifically, can pass through What user generated when the setting interface of terminal is configured, it can also be other feasible modes, here, the embodiment of the present invention It is not specifically limited.

S202:Processor core performs data more new command, generation erasing indication signal;

Here, processor core can perform data more new command, and generate erasing and refer to after data more new command is obtained Show signal, wherein, erasing indication signal be used for indicate the BootLoader programs of monitoring control devices the first whether erasure completion, and work as After monitoring the first BootLoader program erasure completions, status signal is generated.

S203:Processor core sends erasing indication signal, and first in erasable nonvolatile memory to controller BootLoader programs;

Here, the erasing indication signal can be sent to controller by processor core after indication signal is wiped in generation, and The first BootLoader programs in erasable nonvolatile memory.

In specific implementation process, for the first BootLoader programs in erasable nonvolatile memory, processor Core also need to first to controller send the nonvolatile memory corresponding to chip selection signal, choose the nonvolatile memory, Then, controller can control the nonvolatile memory to send the initial address of oneself, finally, processor core to processor core The heart can according to the initial address from nonvolatile memory of acquisition, to access the address space of the nonvolatile memory, And then the first BootLoader programs in erasable nonvolatile memory.

In actual applications, processor core can send nonvolatile memory to controller with the first controlling bus and correspond to Chip selection signal, controller can by the second controlling bus control nonvolatile memory send oneself to processor core Initial address, nonvolatile memory can send the initial address of oneself by address bus to processor core.

S204:Controller response erasing indication signal, monitoring the first BootLoader programs whether erasure completion;

Here, controller can start to monitor non-volatile deposit after the erasing indication signal of processor core transmission is received The first BootLoader programs in reservoir whether erasure completion.

In specific implementation process, controller can be by using the flag bit of the storage in monitoring nonvolatile memory The mode whether to change, come monitor the first BootLoader programs whether erasure completion.If monitoring control devices are to the mark Will position is changed, then can determine the first BootLoader programs erasure completion.

S205:Controller generates status signal after the first BootLoader program erasure completions are monitored;

Here, status signal is used to indicate that nonvolatile memory is currently at writable state.

Specifically, controller is in the first BootLoader program erasure completions in monitoring nonvolatile memory, Also determine nonvolatile memory and be currently at writable state, notifier processes device core nonvolatile memory can be prepared Current state.Therefore, after the first BootLoader program erasure completions in monitoring control devices to nonvolatile memory, Corresponding status signal can be generated.

S206:Controller sends status signal to processor core;

Specifically, controller can send the status signal to processor core, inform processor after status signal is generated The first BootLoader programs erasure completion in core nonvolatile memory, and the shape that nonvolatile memory is current State is writable state, can carry out write operation to nonvolatile memory.

S207:Processor core response status signals, the 2nd BootLoader programs are write into nonvolatile memory.

Here, processor core is after status signal is obtained, it is determined that the current state of nonvolatile memory is can Write state, write operation can be carried out to nonvolatile memory, second can be just write into nonvolatile memory BootLoader programs.

Specifically, first, processor core meeting response status signals, generation write-in indication signal, and write-in instruction is believed Number it is sent to controller;Then, controller can respond write-in indication signal, and control nonvolatile memory to processor core Address information is sent, wherein, address information is used for the writing address for indicating the 2nd BootLoader programs;Finally, processor core 2nd BootLoader programs are write nonvolatile memory by the heart further according to address information.

In specific implementation process, it will be write before indication signal is sent to controller in processor core, processor core The heart also need to first pass through the first controlling bus to controller resend the nonvolatile memory corresponding to chip selection signal, choose The nonvolatile memory;Then, for controller after write-in indication signal is obtained, can just be controlled by the second controlling bus should Nonvolatile memory sends address information to processor core, and the nonvolatile memory can be by address bus to processor Core sends address information;Finally, processor core can be according to address information, by data/address bus into nonvolatile memory Write the 2nd BootLoader programs.

It should be noted that address above mentioned information can be nonvolatile memory initial address or it is non-easily Lose property memory address space in other addresses, in actual applications, those skilled in the art can according to actual conditions come Set, here, the embodiment of the present invention is not specifically limited.

Further, processor core is after the address information from nonvolatile memory is obtained, it is also necessary to obtains and , then will be non-corresponding to the 2nd BootLoader program writing address information from the 2nd BootLoader programs of external memory storage The memory cell of volatile memory.

In actual applications, above-mentioned 2nd BootLoader programs can be outer to store by way of network download In portion's memory, it can also be that user directs out the data sent in portion's memory, it is, of course, also possible to be by other means Store in external memory storage, here, the embodiment of the present invention is not specifically limited.

Specifically, the update method for the BootLoader programs that the embodiment of the present invention one provides can be divided on the whole Two stages, wherein, the first stage is the process of the first BootLoader programs of erasing, and second stage is write-in second The process of BootLoader programs.

Be directed to first stage and second stage separately below, describe in detail processor core in processor, controller with And the specific interaction of nonvolatile memory.

First, illustrate that the first stage wipes the specific interaction being related to during the first BootLoader programs.

Fig. 3 is the schematic flow sheet of the BootLoader programs of erasing the first in the embodiment of the present invention one, referring to Fig. 3 institutes Show during the first BootLoader programs are wiped, mainly there are four interactions, respectively wipe indication signal, erasing, prison Survey and status signal.

When implementing erase process, processor core can send erasing indication signal to controller first, and wipe The first BootLoader programs in nonvolatile memory, then controller can respond the erasing indication signal, monitor it is non-easily Lose property memory in the first BootLoader programs whether erasure completion, and when monitor the first BootLoader programs wipe After the completion of, status signal is generated, wherein, status signal is used to indicate that nonvolatile memory is currently at writable state, most Afterwards, controller sends the status signal to processor core.In this way, the process of the first BootLoader programs of erasing is just completed .

Then, illustrate that second stage writes the specific interaction being related to during the 2nd BootLoader programs.

Fig. 4 is the schematic flow sheet of the BootLoader programs of write-in the 2nd in the embodiment of the present invention one, referring to Fig. 4 institutes Show during the 2nd BootLoader programs are write, equally also mainly there is four interactions, respectively write indication signal, Control, address information and write-in.

When implementing ablation process, processor core can send write-in indication signal, its secondary control to controller first Device processed can respond write-in indication signal, and control nonvolatile memory sends address information to processor core, wherein, address letter The writing address for indicating the 2nd BootLoader programs is ceased, then nonvolatile memory can send ground to processor core Location information, finally, processor core correspond to the 2nd BootLoader program writing address information according to the address information of acquisition Nonvolatile memory memory cell.In this way, the process of the 2nd BootLoader programs of write-in just completes.

So far, just complete and the first BootLoader programs are updated to the 2nd BootLoader programs.By the above Understand, processor provided in an embodiment of the present invention includes:Processor core, controller and nonvolatile memory, wherein, it is non- Volatile memory is supported to perform in chip, can be written and read operation and directly can be connected with processor core, processor core It is connected with controller, controller is connected with nonvolatile memory.So, BootLoader journeys can be accelerated using the processor The renewal speed of sequence.

Embodiment two

Based on previous embodiment, in actual applications, Fig. 5 is the renewal BootLoader programs in the embodiment of the present invention two System structural representation, shown in Figure 5, the system 50 includes:First equipment 501 and the second equipment 502, first sets Standby 501 are connected with the second equipment 502;

Here, above-mentioned first equipment includes external memory storage, and above-mentioned second equipment includes processor.

In actual applications, the first equipment can pass through joint test working group (JTAG, Joint Test Action Group) interface is connected with the second equipment, realizes the communication between the first equipment and the second equipment.Certainly, the first equipment can be with Come and second by other interfaces such as serial communication interface, USB (USB, Universal Serial Bus) interfaces Equipment is connected, and here, the embodiment of the present invention is not specifically limited.

Specifically, the first equipment is used to send data renewal operation to the second equipment, wherein, data renewal operation is used to refer to Show that the first BootLoader programs are updated to the 2nd BootLoader programs by the second equipment;It is additionally operable to send the to the second equipment Two BootLoader programs;Second equipment is used to perform data renewal operation, and the first BootLoader programs are updated into the Two BootLoader programs.

Specifically, the first BootLoader programs are updated to the 2nd BootLoader programs, the first equipment in order to realize Data renewal operation can be sent to the second equipment, the second equipment can perform data renewal operation, generate data manipulation instruction, processing Device can first wipe the first BootLoader journeys in the nonvolatile memory inside processor after data more new command is obtained Sequence, then the 2nd BootLoader programs are obtained from the external memory storage in the first equipment, finally by the 2nd BootLoader journeys Sequence is written in the nonvolatile memory inside processor, is updated to the first BootLoader programs in this way, just realizing 2nd BootLoader programs.

Embodiment three

Based on same inventive concept, the embodiment of the present invention three provides a kind of renewal side of bootload BootLoader programs Method, applied to the processor in said one or multiple embodiments, wherein, processor includes:Processor core, controller with And nonvolatile memory, nonvolatile memory are supported to perform in chip, can be written and read operation and can directly and processor Core connects.

Fig. 6 is the schematic flow sheet of the update method of the BootLoader programs in the embodiment of the present invention three, referring to Fig. 6 institutes Show, this method includes:

S601:Obtain data more new command;

Here, data more new command, for indicating first in processor core renewal nonvolatile memory BootLoader programs are the 2nd BootLoader programs.

S602:Perform data more new command, generation erasing indication signal;

Here, wipe indication signal be used for indicate the BootLoader programs of monitoring control devices the first whether erasure completion, and After the first BootLoader program erasure completions are monitored, status signal is generated.

S603:Erasing indication signal, and the first BootLoader in erasable nonvolatile memory are sent to controller Program;

Here, the erasing indication signal can be sent to controller by processor core after indication signal is wiped in generation, and The first BootLoader programs in erasable nonvolatile memory.

S604:Receive the status signal from controller;

Here, status signal is used to indicate that nonvolatile memory is currently at writable state.

Processor core is obtained after status signal, it is possible to which it is writable to determine the current state of nonvolatile memory State, write operation can be carried out to nonvolatile memory, second can be just write into nonvolatile memory BootLoader programs.

S605:Response status signals, the 2nd BootLoader programs are write into nonvolatile memory.

In specific implementation process, processor core meeting response status signals, first generation write-in indication signal, wherein, write Enter indication signal to be used to indicate that controller control nonvolatile memory sends address information;Then write-in indication signal is sent To controller, and the address information from nonvolatile memory is obtained, wherein, address information is used to indicate second The writing address of BootLoader programs;Finally according to address information, the 2nd BootLoader programs are write into non-volatile deposit Reservoir.

Specifically, processor can obtain and deposited from outside after the address information from nonvolatile memory is obtained 2nd BootLoader programs of reservoir, it is further according to address information, the 2nd BootLoader program writing address information is corresponding Nonvolatile memory memory cell in.

So far, just complete and the first BootLoader programs are updated to the 2nd BootLoader programs.

Example IV

Based on same inventive concept, Fig. 7 is the structural representation of the processor in the embodiment of the present invention four, referring to Fig. 7 institutes Show, the processor 70 include obtaining unit 701, execution unit 702, erasing unit 703, receiving unit 704, writing unit 705, Control unit 706 and memory cell 707.

Specifically, obtaining unit, for obtaining data more new command, wherein, data more new command, for by the storage The first BootLoader programs in unit are updated to the 2nd BootLoader programs;Execution unit, for performing data renewal Instruction, generation erasing indication signal;Unit is wiped, for sending erasing indication signal to control unit, and wipes memory cell In the first BootLoader programs, wherein, erasing indication signal be used for indicate control unit monitor the first BootLoader journeys Sequence whether erasure completion, and after the first BootLoader program erasure completions are monitored, generate status signal;Receiving unit, For receiving the status signal from control unit, wherein, status signal is used to indicate that memory cell is currently at writable shape State;Writing unit, for response status signals, by the 2nd BootLoader program write storage units.

Further, writing unit, response status signals being additionally operable to, generation writes indication signal, wherein, write-in instruction letter Number be used for indicate control unit control memory cell send address information;Write-in indication signal is sent to control unit, and obtained Access unit address information must be come from, wherein, address information is used for the writing address for indicating the 2nd BootLoader programs;Root According to address information, by the 2nd BootLoader program write storage units.

Further, writing unit, it is additionally operable to obtain the 2nd BootLoader programs from external memory storage;By second Storing sub-units in memory cell corresponding to BootLoader program writing address information.

It need to be noted that be:The description of above processor core embodiment, the description with above method embodiment are Similar, there is the beneficial effect similar with embodiment of the method, therefore do not repeat.For processor core embodiment of the present invention In the ins and outs that do not disclose, refer to the description of the inventive method embodiment and understand, to save length, therefore no longer superfluous State.

It should be understood by those skilled in the art that, embodiments of the invention can be provided as method, system or computer program Product.Therefore, the shape of the embodiment in terms of the present invention can use hardware embodiment, software implementation or combination software and hardware Formula.Moreover, the present invention can use the computer for wherein including computer usable program code in one or more to use storage The form for the computer program product that medium is implemented on (including but is not limited to magnetic disk storage and optical memory etc.).

The present invention is the flow with reference to method according to embodiments of the present invention, equipment (system) and computer program product Figure and/or block diagram describe.It should be understood that can be by every first-class in computer program instructions implementation process figure and/or block diagram Journey and/or the flow in square frame and flow chart and/or block diagram and/or the combination of square frame.These computer programs can be provided The processors of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing devices is instructed to produce A raw machine so that produced by the instruction of computer or the computing device of other programmable data processing devices for real The device for the function of being specified in present one flow of flow chart or one square frame of multiple flows and/or block diagram or multiple square frames.

These computer program instructions, which may be alternatively stored in, can guide computer or other programmable data processing devices with spy Determine in the computer-readable memory that mode works so that the instruction being stored in the computer-readable memory, which produces, to be included referring to Make the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one square frame of block diagram or The function of being specified in multiple square frames.

These computer program instructions can be also loaded into computer or other programmable data processing devices so that counted Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented processing, so as in computer or The instruction performed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one The step of function of being specified in individual square frame or multiple square frames.

The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.

Claims (10)

1. a kind of processor, it is characterised in that the processor includes:Processor core, controller and non-volatile memories Device, the nonvolatile memory are supported to perform in chip, can be written and read operation and directly can connect with the processor core Connecing, the processor core is connected with the controller, and the controller is connected with the nonvolatile memory, wherein,
The processor core, for sending erasing indication signal to the controller, and wipe the nonvolatile memory In the first bootload BootLoader programs;It is additionally operable to receive the status signal from the controller, wherein, the shape State signal is used to indicate that the nonvolatile memory is currently at writable state;The status signal is responded, by second BootLoader programs write the nonvolatile memory;
The controller, for responding the erasing indication signal, monitor whether the first BootLoader programs have wiped Into;After the first BootLoader program erasure completions are monitored, the status signal is generated;To the processor core Send the status signal.
2. processor according to claim 1, it is characterised in that the processor core, be additionally operable to obtain data renewal Instruction, wherein, the data more new command, for indicating that the processor core updates the institute in the nonvolatile memory It is the 2nd BootLoader programs to state the first BootLoader programs;The data more new command is performed, generates the wiping Except indication signal.
3. processor according to claim 1, it is characterised in that the processor core, be additionally operable to responding the shape After state signal, generation write-in indication signal;Said write indication signal is sent to the controller, and obtained from described non- The address information of volatile memory, wherein, the address information is used for the write-in for indicating the 2nd BootLoader programs Address;According to the address information, the 2nd BootLoader programs are write into the nonvolatile memory;
Correspondingly,
The controller, it is additionally operable to respond said write indication signal, controls the nonvolatile memory to the processor Core sends the address information;
The nonvolatile memory, it is additionally operable to send the address information to the processor core.
4. processor according to claim 3, it is characterised in that the processor core, be additionally operable to come from institute in acquisition After the address information for stating nonvolatile memory, the 2nd BootLoader programs from external memory storage are obtained; The 2nd BootLoader programs are write to the memory cell of the nonvolatile memory corresponding to the address information.
A kind of 5. update method of bootload BootLoader programs, it is characterised in that applied to processor, wherein, it is described Processor includes:Processor core, controller and nonvolatile memory, the nonvolatile memory are supported to hold in chip Row, operation can be written and read and directly can be connected with the processor core;
Methods described includes:
The processor core obtains data more new command, wherein, the data more new command, for indicating the processor core The first BootLoader programs that the heart is updated in the nonvolatile memory are the 2nd BootLoader programs;
The processor core performs the data more new command, generation erasing indication signal;
The processor core sends the erasing indication signal to the controller, and wipes in the nonvolatile memory The first BootLoader programs;
The controller responds the erasing indication signal, monitor the first BootLoader programs whether erasure completion;
The controller generates status signal after the first BootLoader program erasure completions are monitored, wherein, it is described Status signal is used to indicate that the nonvolatile memory is currently at writable state;
The controller sends the status signal to the processor core;
The processor core responds the status signal, non-volatile deposits the 2nd BootLoader programs write-in is described Reservoir.
6. according to the method for claim 5, it is characterised in that the processor core responds the status signal, by institute State the 2nd BootLoader programs and write the nonvolatile memory, including:
The processor core responds the status signal, generation write-in indication signal;
Said write indication signal is sent to the controller by the processor core;
The controller responds said write indication signal, controls the nonvolatile memory to be sent to the processor core Address information, wherein, the address information is used for the writing address for indicating the 2nd BootLoader programs;
The processor core non-volatile is deposited according to the address information, by the 2nd BootLoader programs write-in is described Reservoir.
A kind of 7. update method of bootload BootLoader programs, it is characterised in that applied to processor, wherein, it is described Processor includes:Processor core, controller and nonvolatile memory, the nonvolatile memory are supported to hold in chip Row, operation can be written and read and directly can be connected with the processor core;
Methods described includes:
Data more new command is obtained, wherein, the data more new command, for indicating that the processor core renewal is described non-easy The first BootLoader programs in the property lost memory are the 2nd BootLoader programs;
Perform the data more new command, generation erasing indication signal;
The erasing indication signal is sent to the controller, and wipes described first in the nonvolatile memory BootLoader programs, wherein, the erasing indication signal is used to indicate the first BootLoader described in the monitoring control devices Program whether erasure completion, and after the first BootLoader program erasure completions are monitored, generate status signal;
The status signal from the controller is received, wherein, the status signal is used to indicate described non-volatile deposit Reservoir is currently at writable state;
The status signal is responded, the 2nd BootLoader programs are write into the nonvolatile memory.
8. according to the method for claim 7, it is characterised in that the response status signal, by described second BootLoader programs write the nonvolatile memory, including:
The status signal is responded, generation writes indication signal, wherein, said write indication signal is used to indicate the controller The nonvolatile memory is controlled to send address information;
Said write indication signal is sent to the controller, and obtains the address from the nonvolatile memory Information, wherein, the address information is used for the writing address for indicating the 2nd BootLoader programs;
According to the address information, the 2nd BootLoader programs are write into the nonvolatile memory.
9. according to the method for claim 8, it is characterised in that in the institute of the acquisition from the nonvolatile memory After stating address information, methods described also includes:
Obtain the 2nd BootLoader programs from external memory storage;
Correspondingly, it is described according to the address information, the 2nd BootLoader programs are write into the non-volatile memories Device, including:
The 2nd BootLoader programs are write to the storage list of the nonvolatile memory corresponding to the address information Member.
10. a kind of processor, it is characterised in that the processor includes:Obtaining unit, execution unit, erasing unit, reception are single Member, writing unit, control unit and memory cell, wherein,
The obtaining unit, for obtaining data more new command, wherein, the data more new command, for the storage is single The first BootLoader programs in member are updated to the 2nd BootLoader programs;
The execution unit, for performing the data more new command, generation erasing indication signal;
The erasing unit, for sending the erasing indication signal to described control unit, and wipe in the memory cell The first BootLoader programs, wherein, the erasing indication signal is used to indicate described control unit monitoring described the One BootLoader programs whether erasure completion, and after the first BootLoader program erasure completions are monitored, generation Status signal;
The receiving unit, for receiving the status signal from described control unit, wherein, the status signal is used for Indicate that the memory cell is currently at writable state;
Said write unit, for responding the status signal, the 2nd BootLoader programs are write direct into described deposit Storage unit.
CN201610851750.9A 2016-09-26 2016-09-26 A kind of update method of processor and BootLoader program CN107870775A (en)

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