CN108108316B - Interface expansion method and system based on field programmable gate array - Google Patents
Interface expansion method and system based on field programmable gate array Download PDFInfo
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Abstract
The invention provides an interface expanding method and system based on a field programmable gate array, wherein the field programmable gate array (namely FPGA) is connected with a central processing unit (namely CPU) through a first type interface and is connected with a target terminal through a second type interface, a plurality of second type interfaces are arranged, different target terminals correspond to different second type interfaces, and the method further comprises the following steps: receiving data sent by the CPU through the first type interface to obtain first data information; analyzing the first data information to obtain first original data which is sent to the target terminal corresponding to the first data information by the CPU; and sending the first original data to the target terminal corresponding to the first data information through the second type interface. According to the invention, the interface expansion is realized through the FPGA, so that a single CPU can control the modules supporting a plurality of different interface protocols through one data interface, the cost is reduced, and the software adjustment is more flexible.
Description
Technical Field
The invention relates to the field of interface expansion, in particular to an interface expansion method and system based on a field programmable gate array.
Background
When a product for an internet of things scene is developed, a central processing unit (Central Processing Unit, CPU) needs to communicate with the internet of things module through a serial port, or a serial peripheral interface (Serial Peripheral Interface, SPI) or the like, but one product may need to be connected with a plurality of internet of things modules, and one CPU may not meet the requirement of the number of interfaces of the plurality of internet of things modules.
Generally, when the number of the interfaces of the CPU is insufficient, a CPU with more interfaces is replaced, or a plurality of CPUs are used, so that the product cost is increased, and meanwhile, the difficulty of stacking hardware is increased.
Disclosure of Invention
The invention aims at providing an interface expansion method and system based on a field programmable gate array, which realize interface expansion through the field programmable gate array, so that a single CPU can control modules supporting a plurality of different interface protocols through one data interface, thereby reducing the cost and realizing more flexible software adjustment.
The technical scheme provided by the invention is as follows:
an interface expansion method based on a field programmable gate array, comprising the following steps: the field programmable gate array is connected with the central processing unit through a first type interface and is connected with the target terminal through a second type interface, a plurality of second type interfaces are arranged, different target terminals correspond to different second type interfaces, and the field programmable gate array further comprises: step S100, receiving data sent by the central processing unit through the first type interface to obtain first data information; step S200, analyzing the first data information to obtain first original data of the target terminal corresponding to the first data information; step S300 is to send the first original data to the target terminal corresponding to the first data information through the second type interface.
In the technical scheme, the field programmable gate array, namely FPGA (Field Programming Gate Array), realizes interface expansion through the FPGA, so that a single CPU can control modules supporting a plurality of different interface protocols through one data interface, thereby reducing the cost; by updating FPGA software, the interface can be flexibly expanded, and interaction with a newly-added target terminal is increased.
Further, the first data information includes: the step S200 specifically includes: step S210, searching the packet header identification in the first data information; step S220, when the packet header identification is found in the first data information, the address information and the corresponding target terminal are obtained; step S230, when the header identifier is found in the first data information, obtaining first escape data of the target terminal corresponding to the first data information; step S240 performs antisense on the first data after the first escape according to a preset escape rule, so as to obtain the first original data.
In the above technical solution, a method for obtaining first original data is provided, by performing antisense on the first data after antisense, so as to accurately obtain the first original data sent by the central processing unit.
Further, the method further comprises the following steps: step S400, receiving data sent by the target terminal through a second type interface to obtain second original data; step S500, assembling the second original data to obtain second data information; step S600 sends the second data information to the central processing unit through the first type interface.
In the technical scheme, an interface interaction process in the uplink direction (from the target terminal to the FPGA and then to the CPU) is provided, so that the whole scheme is perfected.
Further, the step S500 specifically includes: step S510, when the second original data contains the escape character, escaping the escape character according to a preset escape rule to obtain second escape data; step S520 adds a header identifier and address information to the second escape data, and assembles the second data information according to an interface format between the cpu and the fpga.
In the above technical solution, a method for obtaining second data information is provided, by escaping from second original data, the false analysis of the receiving party when the packet header identifier is the same as the original data content is avoided.
Further, the header is identified as a character; the preset escape rule is as follows: two escape characters exist, wherein the character identical to the header identifier is a first escape character, a second escape character is a preset character, and the second escape character is different from the first escape character; and obtaining a byte combination consisting of two characters after the escape of one escape character, wherein a first character in the byte combination is fixed to be a second escape character, and the second character in the byte combination is calculated according to the escape character and a preset function operation formula.
In the above technical solution, an escape rule is provided.
Further, the step S600 specifically includes: step S610, caching the second data information; step S620, when there is not less than the second data information of one of the target terminals in the cache, preferentially sending the second data information of the target terminal with a higher priority to the central processing unit according to the priority of the target terminal.
In the above technical solution, a transmission scheme is newly added for the second data information to the CPU, so that the data transmission of the target terminal with high priority can be preferentially ensured.
The invention also provides a field programmable gate array comprising: the field programmable gate array is connected with the central processing unit through a first type interface and is connected with the target terminals through a second type interface, a plurality of second type interfaces are arranged, and different target terminals correspond to different second type interfaces; the field programmable gate array includes: the second receiving module is used for receiving the data sent by the central processing unit through the first type interface to obtain first data information; the analysis module is electrically connected with the second receiving module and is used for analyzing the first data information to obtain first original data of the target terminal corresponding to the first data information; the second sending module is electrically connected with the analyzing module and is used for sending the first original data to the target terminal corresponding to the first data information through the second type interface.
In the technical scheme, the interface expansion is realized through the FPGA, so that a single CPU can control the modules supporting a plurality of different interface protocols through one data interface, and the cost is reduced; by updating FPGA software, the interface can be flexibly expanded, and interaction with a newly-added target terminal is increased.
Further, the first data information includes: the packet header identification, the address information and the first escape data; the analysis module is further used for searching the packet header identification in the first data information; when the packet head identifier is found in the first data information, the address information and the corresponding target terminal are obtained; when the packet head identifier is found in the first data information, first escape data of the target terminal corresponding to the first data information are obtained; and performing antisense on the first data after the first escape according to a preset escape rule to obtain the first original data.
In the above technical solution, a method for obtaining first original data is provided, by performing antisense on the first data after antisense, so as to accurately obtain the first original data sent by the central processing unit.
Further, the second receiving module is further configured to receive, through a second type interface, data sent by the target terminal, and obtain second original data sent by the target terminal to the central processor; the analysis module is further used for assembling the second original data to obtain second data information; the second sending module is further configured to send the second data information to the central processing unit through the first type interface.
In the technical scheme, an interface interaction process in the uplink direction (from the target terminal to the FPGA and then to the CPU) is provided, so that the whole scheme is perfected.
The invention also provides an interface expansion system based on the field programmable gate array, which comprises: the field programmable gate array; further comprises: a central processing unit and a plurality of target terminals; the central processing unit is electrically connected with the field programmable gate array; each target terminal is electrically connected with the field programmable gate array; the central processing unit includes: the first sending module is used for sending the first data information to the field programmable gate array through the first type interface; the first receiving module is used for receiving the second data information from the field programmable gate array through the first type interface; each of the target terminals includes: the third sending module is used for sending the second original data to the field programmable gate array through the second type interface; and the third receiving module is used for receiving the first original data from the field programmable gate array through the second type interface.
In the technical scheme, interface interaction between a single CPU and a plurality of target terminals is realized through the field programmable gate array, the interface of the single CPU is expanded, and the cost is reduced.
The interface expansion method and the system based on the field programmable gate array provided by the invention have the following beneficial effects:
according to the invention, the interface expansion is realized through the FPGA, so that a single CPU can control a module supporting a plurality of different interface protocols through one data interface, and the cost is reduced; by updating FPGA software, the interface can be flexibly expanded, and interaction with a newly-added target terminal is increased.
Drawings
The above features, technical features, advantages and implementation manners of an interface extension method and system based on a field programmable gate array will be further described with reference to the accompanying drawings in a clear and understandable manner.
FIG. 1 is a flow chart of one embodiment of a Field Programmable Gate Array (FPGA) -based interface expansion method of the present invention;
FIG. 2 is a flow chart of another embodiment of a Field Programmable Gate Array (FPGA) -based interface expansion method of the present invention;
FIG. 3a is a flow chart of another embodiment of a Field Programmable Gate Array (FPGA) -based interface extension method of the present invention;
FIG. 3b is a partial flow chart of another embodiment of a Field Programmable Gate Array (FPGA) -based interface extension method of the present invention;
FIG. 4 is a schematic diagram of one embodiment of a field programmable gate array of the present invention;
FIG. 5 is a schematic diagram of another embodiment of a field programmable gate array of the present invention;
FIG. 6 is a schematic diagram illustrating one embodiment of a Field Programmable Gate Array (FPGA) -based interface extension system of the present invention;
FIG. 7 is a schematic diagram of the interface between the FPGA and the CPU of one embodiment of a Field Programmable Gate Array (FPGA) -based interface extension method of the present invention;
FIG. 8 is a schematic diagram of a first type of interface, a second type of interface, of one embodiment of a field programmable gate array based interface extension system of the present invention.
Reference numerals illustrate:
100. the system comprises a Central Processing Unit (CPU), a Field Programmable Gate Array (FPGA), a target terminal (300), a first transmitting module (110), a first receiving module (120), a second transmitting module (210), a second receiving module (220), a second receiving module (230), an analyzing module (240), a buffer module (310), a third transmitting module (320), a third receiving module (1), a first type interface (1), and a second type interface (2).
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
For the sake of simplicity of the drawing, the parts relevant to the present invention are shown only schematically in the figures, which do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
In one embodiment of the present invention, as shown in fig. 1, an interface extension method based on a field programmable gate array is applied to a field programmable gate array, where the field programmable gate array is connected to a central processing unit through a first type interface and connected to a target terminal through a second type interface, where the second type interface has a plurality of different target terminals corresponding to different second type interfaces; further comprises:
step S100, receiving data sent by the central processing unit through the first type interface to obtain first data information;
step S200, analyzing the first data information to obtain first original data of the target terminal corresponding to the first data information;
Step S300 is to send the first original data to the target terminal corresponding to the first data information through the second type interface.
Specifically, a field programmable gate array, FPGA (Field Programming GateArray); a central processing unit, CPU (Central Processing Unit). The first type interface is an interface between the FPGA and the CPU, the FPGA is connected with the CPU through the first type interface, the first type interface possibly only comprises one interface, and the CPU sends and receives messages through the same interface; the first type of interface may also include two interfaces, one for the CPU to send messages and one for the receive interface to receive messages sent by the CPU, independent of each other.
The second type of interface refers to an interface between the FPGA and each target terminal, for example, the FPGA is connected to 3 target terminals, and interfaces between the FPGA and the first target terminal, between the FPGA and the second target terminal, and between the FPGA and the third target terminal all belong to the second type of interface. Different target terminals correspond to different second type interfaces, for example, an interface between the FPGA and the first target terminal, an interface between the FPGA and the second target terminal, and an interface between the FPGA and the third target terminal are mutually independent and pass through different channels. All the target terminals connected to the FPGA may all have the same or may be partially the same or may be completely different. The second type of interface comprises a GPIO port, a serial port, a PCM interface, an I2C interface and an SPI interface. The FPGA software needs to be designed according to the number of connected target terminals and the interface protocol followed by each module; the communication rate of the second type of interface may also be configured according to the rate supported by the target terminal.
The FPGA receives data sent by the CPU through the first type of interface, and receives the data according to a physical interface protocol followed by the CPU-FPGA, for example, a serial port is arranged between the CPU-FPGA, and the data is received according to serial port convention, so that user data sent by the CPU, namely first data information, is obtained. The formats of the first data information are various, for example, a packet header identifier, a target terminal number, a data type and original data, the first data information needs to be analyzed according to a contracted interface format to obtain the original data, namely, the first original data of the target terminal, which is sent to the corresponding target terminal number in the first data information by the CPU; and through a second type of interface, such as an SPI interface, the first original data is sent to the target terminal corresponding to the target terminal number according to SPI interface protocol convention.
In another embodiment of the present invention, as shown in fig. 2, an interface extension method based on a field programmable gate array is applied to the field programmable gate array, where the field programmable gate array is connected to a central processing unit through a first type interface and connected to a target terminal through a second type interface, where the second type interface has a plurality of different target terminals corresponding to different second type interfaces; further comprises:
Step S100, receiving data sent by the central processing unit through the first type interface to obtain first data information;
step S200, analyzing the first data information to obtain first original data of the target terminal corresponding to the first data information;
step S300, sending the first original data to the target terminal corresponding to the first data information through the second type interface;
step S400, receiving data sent by the target terminal through a second type interface to obtain second original data;
step S500, assembling the second original data to obtain second data information;
step S600 sends the second data information to the central processing unit through the first type interface.
Specifically, compared with the previous embodiment, the uplink direction is increased, namely, the interface interaction flow from the target terminal to the FPGA to the CPU is increased. The FPGA receives data sent by the target terminal through a second type interface according to interface convention between the FPGA and the target terminal to obtain second original data; the FPGA sends the second original data to the CPU, and before the second original data is sent to the CPU, the second original data is assembled according to the interface convention of the CPU-FPGA to obtain second data information; assuming that the format of the second data information of the CPU-FPGA is that the packet header identifier, the target terminal number, the data type and the original data, then the packet header identifier, the target terminal number and the data type are added before the second original data to form the second data information; and the FPGA sends the second data information to the CPU through the first type interface.
In another embodiment of the present invention, as shown in fig. 3a and fig. 3b, an interface extension method based on a field programmable gate array is applied to a field programmable gate array, where the field programmable gate array is connected to a central processing unit through a first type of interface and is connected to a target terminal through a second type of interface, where the second type of interface has a plurality of different target terminals corresponding to different second type of interfaces; further comprises:
step S100, receiving data sent by the central processing unit through the first type interface to obtain first data information;
the first data information includes: the packet header identification, the address information and the first escape data;
step S210, searching the packet header identification in the first data information;
step S220, when the packet header identification is found in the first data information, the address information and the corresponding target terminal are obtained;
step S230, when the header identifier is found in the first data information, obtaining first escape data of the target terminal corresponding to the first data information;
step S240, performing an antisense to the first data after the first escape according to a preset escape rule, to obtain the first original data;
The step S240 specifically includes:
step S241 traverses the content of each byte in the first escape data, and judges whether at least one first byte exists or not;
the first byte is a byte with the same byte content as the first transferring character;
step S242, when at least one first byte exists, acquiring a byte combination corresponding to each first byte according to the existing first byte;
each of the byte combinations includes: a content of the first byte and a content of a next byte corresponding to the first byte;
step S243 obtains the respective corresponding escape character of each byte combination according to the preset escape rule and each byte combination;
step S244 replaces all the byte combinations in the first escape data with the corresponding escape characters, so as to obtain first original data of the target terminal corresponding to the first data information;
step S300, sending the first original data to the target terminal corresponding to the first data information through the second type interface;
step S400, receiving data sent by the target terminal through a second type interface to obtain second original data;
Step S510, when the second original data contains the escape character, escaping the escape character according to a preset escape rule to obtain second escape data;
step S520 adds a header identifier and address information before the second escape data, and assembles the second data information according to an interface format between the CPU and the FPGA;
the header mark is a character;
the preset escape rule is as follows:
two escape characters exist, wherein the character identical to the header identifier is a first escape character, a second escape character is a preset character, and the second escape character is different from the first escape character;
obtaining a byte combination consisting of two characters after the escape of one escape character, wherein a first character in the byte combination is fixed as a second escape character, and the second character in the byte combination is calculated according to the escape character and a preset function operation formula;
step S610, caching the second data information;
step S620, when there is not less than the second data information of one of the target terminals in the cache, preferentially sending the second data information of the target terminal with a higher priority to the central processing unit according to the priority of the target terminal.
Specifically, steps S210-S240 replace step S200, steps S241-S244 refine step S240, steps S510-S520 replace step S500, and steps S610-S620 replace step S600, as compared to the previous embodiment. Fig. 3a depicts the overall flow and fig. 3b depicts the antisense process in detail.
In order to avoid misunderstanding of the receiving information by the receiving end when bytes which are the same as the packet head identifiers appear in the original data, the transmitting end carries out escape on the original data content; when the FPGA sends second original data of the target terminal to the CPU, traversing a second original data packet, and when the second original data contains an escape character, escaping the escape character according to a preset escape rule to obtain second escape data; on the basis, adding a packet header identifier and address information, and assembling the second data information according to an interface format between the CPU and the FPGA; when receiving the data of the CPU, the FPGA unpacks and inverts the received first data information, so as to obtain first original data. The interface format between CPU-FPGA is assumed to be: the header identifier+address information+the escape data content is shown in fig. 7, wherein 0x7E is the header identifier, addr occupies one byte, and the meaning is shown in the following table:
| Addr | Function of |
| 0x0 | Transmitting data to target terminal 0 |
| 0x1 | Transmitting data to target terminal 1 |
| 0x2 | Transmitting data to target terminal 2 |
| 0x3 | Receiving data of target terminal 0 |
| 0x4 | Receiving data of the target terminal 1 |
| 0x5 | Receiving data of the target terminal 2 |
The escape rule is as follows:
wherein, the escape characters are 0x7E and 0x7D, wherein 0x7E is a first escape character, and the escape character is the same as the header identifier, and 0x7D is a second escape character; the escape of an escape character results in a byte combination of two characters, wherein the first character in the byte combination is 0x7D, i.e., the second escape character, and the second character in the byte combination is calculated according to a predetermined function operation formula, e.g., the above-mentioned table is calculated according to the formulaCalculated out->Representing an exclusive or operation, when x=0x7e, the second character after escape is obtained to be 0x5E; when x=0x7d, the second character after escape is found to be 0x5D. The preset function operation formula can also be in other function forms, such as +.>The above is just one embodiment。
Assume that the first data information transmitted by the CPU to the target terminal 0 is: 0x7E,0x 0, 0x1, 0x7D, 0x5E, 0x2, 0x7D, 0x5D, 0x7D, 0x5E; when the FPGA receives the first data information sent by the CPU, the first data information is analyzed, the 1 st byte 0x7E is a packet header identifier, and 0x0 is Addr, which indicates the data sent to the target terminal 0; the data after Addr is the first data after the sense, namely, 0x1, 0x7D, 0x5E, 0x2, 0x7D, 0x5D, 0x7D, 0x5E; traversing the content of each byte in the first escape data, and judging whether at least one first byte exists or not; the first byte is a byte with byte content of 0x7D, i.e. it is determined whether the first escape character 0x7D exists in the data; if the character exists, performing antisense according to a preset escape rule, namely, 0x7D5E corresponds to an escape character 0x7E, and 0x7D5D corresponds to an escape character 0x7D; in this example, after the antisense, 0x1, 0x7E,0x 2, 0x7D, 0x7E,0x 5E are obtained, which is the first raw data. And if the escape character 0x7D does not exist in the first escape data, the first escape data is the first original data. If the escape character 0x7D exists in the first escape data, but the byte combination corresponding to the first byte is neither 0x7D5E nor 0x7D5D, it indicates that there may be an error in the transmission process, and the first data information should be discarded.
When the FPGA sends the second original data of the target terminal 0 to the CPU, it is assumed that the second original data is 0x1, 0x7E, 0x2, 0x7D, 0x7E, 0x5E, and it needs to check whether the second original data has the escape character 0x7E or 0x7D; if the data exists, the escape is carried out according to a preset escape rule, namely, 0x7E corresponds to 0x7D5E,0x7D corresponds to 0x7D5D, and after escape, second escape data, namely, 0x1, 0x7D, 0x5E, 0x2, 0x7D, 0x5D, 0x7D, 0x5E and 0x5E are obtained. And adding the header identifier 0x7E to the second escape data, determining Addr to be 0x3 according to the target terminal, and adding Addr to obtain second data information, namely 0x7E, 0x3, 0x1, 0x7D, 0x5E, 0x2, 0x7D, 0x5D, 0x7D, 0x5E and 0x5E.
Possibly, a plurality of target terminals send data to the FPGA at the same time, and the FPGA sequentially receives and caches the data; when the FPGA sends the data information to the CPU, the second data information of the target terminal with high priority is sent to the CPU in a priority mode.
In another embodiment of the present invention, as shown in FIG. 4, a field programmable gate array 200 includes:
the field programmable gate array 200 is connected with the central processing unit 100 through a first type interface 1 and is connected with the target terminals 300 through a second type interface 2, wherein a plurality of second type interfaces 2 are provided, and different target terminals 300 correspond to different second type interfaces 2;
The field programmable gate array 200 includes:
a second receiving module 220, configured to receive, through the first type interface 1, data sent by the central processor 100, to obtain first data information;
the analyzing module 230 is electrically connected to the second receiving module 220, and is configured to analyze the first data information to obtain first original data sent by the central processing unit 100 to the target terminal 300 corresponding to the first data information;
the second sending module 210 is electrically connected to the parsing module 230, and is configured to send the first raw data to the target terminal 300 corresponding to the first data information through the second type interface 2.
Specifically, field programmable gate array 200, FPGA (Field Programming GateArray); the central processing unit 100, CPU (Central Processing Unit). The first type interface 1 is an interface between the FPGA and the CPU, the FPGA is connected with the CPU through the first type interface 1, the first type interface possibly only comprises one interface, and the CPU sends and receives messages through the same interface; the first type of interface may also include two interfaces, one for the CPU to send messages and one for the receive interface to receive messages sent by the CPU, independent of each other.
The second type interface 2 refers to an interface between an FPGA and each target terminal, for example, the FPGA is connected to 3 target terminals, and interfaces between the FPGA and the first target terminal, between the FPGA and the second target terminal, and between the FPGA and the third target terminal all belong to the second type interface 2. The different target terminals 300 correspond to different interfaces 2 of the second type, for example, the interface between the FPGA and the first target terminal, the interface between the FPGA and the second target terminal, and the interface between the FPGA and the third target terminal are independent of each other and pass through different channels. All the target terminals 300 connected to the FPGA may all be identical, or may be partially identical, or may be completely different. The second type of interface 2 comprises a GPIO port, a serial port, a PCM interface, an I2C interface and an SPI interface. The FPGA software needs to be designed according to the number of connected target terminals and the interface protocol followed; the communication rate of the second type interface 2 may be configured according to the rate supported by the target terminal 300.
The FPGA receives data sent by the CPU through the first type interface 1, and receives the data according to a physical interface protocol followed by the CPU-FPGA, for example, a serial port is arranged between the CPU-FPGA, and the data is received according to serial port convention, so that user data sent by the CPU, namely first data information, is obtained. The formats of the first data information are various, for example, a header identifier, a target terminal number, a data type and original data, the first data information needs to be analyzed according to a agreed interface format to obtain the original data, namely, the first original data of the target terminal 300, which is sent to the corresponding target terminal number in the first data information by the CPU; the first original data is sent to the target terminal corresponding to the number of the target terminal 300 according to the protocol convention of the SPI interface through a second type of interface 2, such as the SPI interface.
In another embodiment of the present invention, as shown in FIG. 4, a field programmable gate array 200 includes:
the field programmable gate array 200 is connected with the central processing unit 100 through a first type interface 1 and is connected with the target terminals 300 through a second type interface 2, wherein a plurality of second type interfaces 2 are provided, and different target terminals 300 correspond to different second type interfaces 2;
the field programmable gate array 200 includes:
a second receiving module 220, configured to receive, through the first type interface 1, data sent by the central processor 100, to obtain first data information;
the parsing module 230 is electrically connected to the second receiving module 220, and is configured to parse the first data information to obtain first original data of the target terminal 300 corresponding to the first data information;
the second sending module 210 is electrically connected to the parsing module 230, and is configured to send the first original data to the target terminal 300 corresponding to the first data information through the second type interface 2;
the second receiving module 220 is further configured to receive, through the second type interface 2, data sent by the target terminal, and obtain second original data sent by the target terminal 300 to the central processor 100;
The parsing module 230 is further configured to assemble the second original data to obtain second data information;
the second sending module 210 is further configured to send the second data information to the central processor 100 through the first type interface 1.
Specifically, compared with the previous embodiment, the uplink direction is increased, namely, the interface interaction flow from the target terminal to the FPGA to the CPU is increased. The FPGA receives data sent by the target terminal 300 through the second type interface 2 according to interface convention between the FPGA and the target terminal to obtain second original data; the FPGA sends the second original data to the CPU, and before the second original data is sent to the CPU, the second original data is assembled according to the interface convention of the CPU-FPGA to obtain second data information; assuming that the format of the second data information of the CPU-FPGA is that the packet header identifier, the target terminal number, the data type and the original data, then the packet header identifier, the target terminal number and the data type are added before the second original data to form the second data information; the FPGA sends the second data information to the CPU through the first type interface 1.
In another embodiment of the present invention, as shown in FIG. 5, a field programmable gate array 200 includes:
The field programmable gate array 200 is connected with the central processing unit 100 through a first type interface 1 and is connected with the target terminals 300 through a second type interface 2, wherein a plurality of second type interfaces 2 are provided, and different target terminals 300 correspond to different second type interfaces 2;
the field programmable gate array 200 includes:
a second receiving module 220, configured to receive, through the first type interface 1, data sent by the central processor 100, to obtain first data information;
the parsing module 230 is electrically connected to the second receiving module 220, and is configured to parse the first data information to obtain first original data of the target terminal 300 corresponding to the first data information;
the second sending module 210 is electrically connected to the parsing module 230, and is configured to send the first original data to the target terminal 300 corresponding to the first data information through the second type interface 2;
the first data information includes: the packet header identification, the address information and the first escape data;
the parsing module 230 is further configured to find the header identifier in the first data information; and when the packet header identifier is found in the first data information, obtaining the address information and the corresponding target terminal 300; and when the packet header identifier is found in the first data information, obtaining first escape data of the target terminal 300 corresponding to the first data information; performing antisense on the first data after the first escape according to a preset escape rule to obtain the first original data;
The parsing module 230 is further configured to traverse the content of each byte in the first escape data, and determine whether at least one first byte exists; the first byte is a byte with the same byte content as the first transferring character; when at least one first byte exists, acquiring a byte combination corresponding to each first byte according to the existing first byte; each of the byte combinations includes: a content of the first byte and a content of a next byte corresponding to the first byte; according to a preset escape rule and each byte combination, obtaining each corresponding escape character of each byte combination; and replacing all byte combinations in the first escape data with the corresponding escape characters to obtain first original data sent by the central processing unit 100 to the target terminal 300 corresponding to the first data information;
the second receiving module 220 is further configured to receive, through the second type interface 2, data sent by the target terminal 300, so as to obtain second original data sent by the target terminal 300 to the central processor 100;
The parsing module 230 is further configured to assemble the second original data to obtain second data information;
the second sending module 210 is further configured to send the second data information to the central processor 100 through the first type interface 1;
the parsing module 230 is further configured to, when the second original data includes an escape character, escape the escape character according to a preset escape rule, so as to obtain second escape data; and adding a header identifier and address information to the second escape data, and assembling the second data information according to an interface format between the central processing unit 100 and the field programmable gate array 200;
the header mark is a character;
the preset escape rule is as follows:
two escape characters exist, wherein the character identical to the header identifier is a first escape character, a second escape character is a preset character, and the second escape character is different from the first escape character;
obtaining a byte combination consisting of two characters after the escape of one escape character, wherein a first character in the byte combination is fixed as a second escape character, and the second character in the byte combination is calculated according to the escape character and a preset function operation formula;
The buffer module 240 is electrically connected to the parsing module 230, and is configured to buffer the second data information;
the second sending module 210 is further configured to send, when there is not less than the second data information of one target terminal 300 in the cache, the second data information of the target terminal with a higher priority to the central processor 100 according to the priority of the target terminal 300.
Specifically, in order to avoid misunderstanding of the receiving information by the receiving end when bytes identical to the packet header identification appear in the original data, the transmitting end performs escape on the original data content; when the FPGA sends second original data of the target terminal 300 to the CPU, traversing a second original data packet, and when the second original data contains an escape character, escaping the escape character according to a preset escape rule to obtain second escape data; on the basis, adding a packet header identifier, and assembling the second data information according to an interface format between the CPU and the FPGA; when receiving the data of the CPU, the FPGA unpacks and inverts the received first data information, so as to obtain first original data. The interface format between CPU-FPGA is assumed to be: the header identifier+address information+the escape data content is shown in fig. 7, wherein 0x7E is the header identifier, addr occupies one byte, and the meaning is shown in the following table:
| Addr | Function of |
| 0x0 | Transmitting data to target terminal 0 |
| 0x1 | Transmitting data to target terminal 1 |
| 0x2 | Transmitting data to target terminal 2 |
| 0x3 | Receiving data of target terminal 0 |
| 0x4 | Receiving data of the target terminal 1 |
| 0x5 | Receiving data of the target terminal 2 |
The escape rule is as follows:
wherein, the escape characters are 0x7E and 0x7D, wherein 0x7E is a first escape character, and the escape character is the same as the header identifier, and 0x7D is a second escape character; the escape of an escape character results in a byte combination of two characters, wherein the first character in the byte combination is 0x7D, i.e., the second escape character, and the second character in the byte combination is calculated according to a predetermined function operation formula, e.g., the above-mentioned table is calculated according to the formulaCalculated out->Representing an exclusive or operation, when x=0x7e, the second character after escape is obtained to be 0x5E; when x=0x7d, the second character after escape is found to be 0x5D. The preset function operation formula can also be in other function forms, such as +.>The above onlyIs one embodiment.
Assume that the first data information transmitted by the CPU to the target terminal 0 is: 0x7E,0x 0, 0x1, 0x7D, 0x5E, 0x2, 0x7D, 0x5D, 0x7D, 0x5E; when the FPGA receives the first data information sent by the CPU, the first data information is analyzed, the 1 st byte 0x7E is a packet header identifier, and 0x0 is Addr, which indicates the data sent to the target terminal 0; the data after Addr is the first data after the sense, namely, 0x1, 0x7D, 0x5E, 0x2, 0x7D, 0x5D, 0x7D, 0x5E; traversing the content of each byte in the first escape data, and judging whether at least one first byte exists or not; the first byte is a byte with byte content of 0x7D, i.e. it is determined whether the first escape character 0x7D exists in the data; if the character exists, performing antisense according to a preset escape rule, namely, 0x7D5E corresponds to an escape character 0x7E, and 0x7D5D corresponds to an escape character 0x7D; in this example, after the antisense, 0x1, 0x7E,0x 2, 0x7D, 0x7E,0x 5E are obtained, which is the first raw data. And if the escape character 0x7D does not exist in the first escape data, the first escape data is the first original data. If the escape character 0x7D exists in the first escape data, but the byte combination corresponding to the first byte is neither 0x7D5E nor 0x7D5D, it indicates that there may be an error in the transmission process, and the first data information should be discarded.
When the FPGA sends the second original data of the target terminal 0 to the CPU, it is assumed that the second original data is 0x1, 0x7E, 0x2, 0x7D, 0x7E, 0x5E, and it needs to check whether the second original data has the escape character 0x7E or 0x7D; if the data exists, the escape is carried out according to a preset escape rule, namely, 0x7E corresponds to 0x7D5E,0x7D corresponds to 0x7D5D, and after escape, second escape data, namely, 0x1, 0x7D, 0x5E, 0x2, 0x7D, 0x5D, 0x7D, 0x5E and 0x5E are obtained. And adding the header identifier 0x7E to the second escape data, determining Addr to be 0x3 according to the target terminal, and adding Addr to obtain second data information, namely 0x7E, 0x3, 0x1, 0x7D, 0x5E, 0x2, 0x7D, 0x5D, 0x7D, 0x5E and 0x5E.
Possibly, a plurality of target terminals 300 send data to the FPGA at the same time, and the FPGA sequentially receives and caches the data; when the FPGA transmits to the CPU, the second data information of the target terminal 300 having a high priority is preferentially transmitted to the CPU.
In another embodiment of the present invention, as shown in fig. 6, an interface expansion system based on a field programmable gate array 200, includes: the field programmable gate array 200 described in any of the embodiments above; further comprises: a central processing unit 100, a plurality of target terminals 300; the central processing unit 100 is electrically connected with the field programmable gate array 200; each of the target terminals 300 is electrically connected to the field programmable gate array 200;
The central processing unit 100 includes:
a first sending module 110, configured to send the first data information to the field programmable gate array 200 through the first type interface 1;
a first receiving module 120, configured to receive the second data information from the field programmable gate array 200 through the first type interface 1;
each of the target terminals 300 includes:
a third sending module 310, configured to send the second raw data to the field programmable gate array 200 through the second type interface 2;
a third receiving module 320, configured to receive the first raw data from the field programmable gate array 200 through the second type interface 2.
Specifically, the field programmable gate array 200 may be connected to a plurality of target terminals 300, and fig. 6 depicts two target terminals 300 for illustration only.
The interface between the FPGA and the CPU is a first type of interface 1, as shown in fig. 8, and is illustrated by using the interface between the FPGA and the CPU as a serial port. The CPU comprises a first sending module and a first receiving module, and performs information interaction with the FPGA through a first type interface 1.
The direct interfaces of the FPGA and the plurality of target terminals 300 are the second type of interfaces 2, as shown in fig. 8, and the interfaces between the FPGA and the target terminals are indicated as SPI ports. Each target terminal 300 comprises a third sending module and a third receiving module, and performs information interaction with the FPGA through the second type interface 2. Interface interaction between a single CPU and a plurality of target terminals 300 is realized through the FPGA, the interface of the single CPU is expanded, and the cost is reduced.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (7)
1. An interface expansion method based on a field programmable gate array is characterized in that:
the field programmable gate array is connected with the central processing unit through a first type interface and is connected with the target terminal through a second type interface, a plurality of second type interfaces are arranged, different target terminals correspond to different second type interfaces, and the field programmable gate array further comprises:
step S100 receives, through the first type interface, data sent by the central processing unit, to obtain first data information, where the first data information includes: the packet header identification, the address information and the first escape data;
step S200, analyzing the first data information to obtain first original data of the target terminal corresponding to the first data information;
step S300, sending the first original data to the target terminal corresponding to the first data information through the second type interface;
The step S200 specifically includes:
step S210, searching the packet header identification in the first data information;
step S220, when the packet header identification is found in the first data information, the address information and the corresponding target terminal are obtained;
step S230, when the header identifier is found in the first data information, obtaining first escape data of the target terminal corresponding to the first data information;
step S240 performs antisense on the first data after the first escape according to a preset escape rule, so as to obtain the first original data.
2. The field programmable gate array (fpga) -based interface extension method of claim 1, further comprising:
step S400, receiving data sent by the target terminal through a second type interface to obtain second original data;
step S500, assembling the second original data to obtain second data information;
step S600, sending the second data information to the central processing unit through the first type interface;
the step S500 specifically includes:
step S510, when the second original data contains the escape character, escaping the escape character according to a preset escape rule to obtain second escape data;
Step S520 adds a header identifier and address information to the second escape data, and assembles the second data information according to an interface format between the cpu and the fpga.
3. The field programmable gate array-based interface extension method according to claim 1 or 2, wherein:
the header mark is a character;
the preset escape rule is as follows:
two escape characters exist, wherein the character identical to the header identifier is a first escape character, a second escape character is a preset character, and the second escape character is different from the first escape character;
and obtaining a byte combination consisting of two characters after the escape of one escape character, wherein a first character in the byte combination is fixed to be a second escape character, and the second character in the byte combination is calculated according to the escape character and a preset function operation formula.
4. The method for expanding an interface based on a field programmable gate array according to claim 2, wherein the step S600 specifically comprises:
step S610, caching the second data information;
step S620, when there is not less than the second data information of one of the target terminals in the cache, preferentially sending the second data information of the target terminal with a higher priority to the central processing unit according to the priority of the target terminal.
5. A field programmable gate array, characterized by:
the field programmable gate array is connected with the central processing unit through a first type interface and is connected with the target terminals through a second type interface, a plurality of second type interfaces are arranged, and different target terminals correspond to different second type interfaces;
the field programmable gate array includes:
the second receiving module is configured to receive, through the first type interface, data sent by the central processing unit, and obtain first data information, where the first data information includes: the packet header identification, the address information and the first escape data;
the analysis module is electrically connected with the second receiving module and is used for analyzing the first data information to obtain first original data of the target terminal corresponding to the first data information;
the analysis module is further used for searching the packet header identification in the first data information; when the packet head identifier is found in the first data information, the address information and the corresponding target terminal are obtained; when the packet head identifier is found in the first data information, first escape data of the target terminal corresponding to the first data information are obtained; performing antisense on the first data after the first escape according to a preset escape rule to obtain the first original data;
The second sending module is electrically connected with the analyzing module and is used for sending the first original data to the target terminal corresponding to the first data information through the second type interface.
6. The field programmable gate array of claim 5, wherein:
the second receiving module is further configured to receive data sent by the target terminal through a second type interface, so as to obtain second original data sent by the target terminal to the central processing unit;
the analysis module is further configured to assemble the second original data to obtain second data information, and when the second original data includes an escape character, escape the escape character according to a preset escape rule to obtain second escape data; adding a packet header identifier and address information in front of the second escape data, and assembling the second data information according to an interface format between the central processing unit and the field programmable gate array;
the second sending module is further configured to send the second data information to the central processing unit through the first type interface.
7. An interface expansion system based on a field programmable gate array, which is characterized in that,
Comprising the following steps:
the field programmable gate array of claim 6;
further comprises: a central processing unit and a plurality of target terminals;
the central processing unit is electrically connected with the field programmable gate array;
each target terminal is electrically connected with the field programmable gate array;
the central processing unit includes:
the first sending module is used for sending the first data information to the field programmable gate array through the first type interface;
the first receiving module is used for receiving the second data information from the field programmable gate array through the first type interface;
each of the target terminals includes:
the third sending module is used for sending the second original data to the field programmable gate array through the second type interface;
and the third receiving module is used for receiving the first original data from the field programmable gate array through the second type interface.
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