CN202838306U - Field programmable gata array (FPGA) configuration system based on microprocessor - Google Patents
Field programmable gata array (FPGA) configuration system based on microprocessor Download PDFInfo
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Abstract
The utility model discloses a field programmable gata array (FPGA) configuration system based on a microprocessor. The FPGA configuration system based on the microprocessor is used for configurating FPGA chips in an embedded system. The configuration system comprises the microprocessor and a main FPGA chip. The microprocessor is connected with the main FPGA chip. The microprocessor is used for conveying layout data to the main FPGA chip to configurate the main FPGA chip. The existing microprocessor in the configuration system is connected with the FPGA chip, the storage layout data of a memorizer of the microprocessor configurate the FPGA chip, a special configuration chip programmable read only memory (PROM) is left out, and therefore circuit structure is simplified, and system costs are saved.
Description
Technical field
The utility model relates to electronic technology field, is specifically related to a kind of FPGA configuration-system based on microprocessor.
Background technology
FPGA (Field Programmable Gate Array, field programmable gate array) chip at first needs to be configured before the use that at every turn powers on.In the prior art, the configuration mode of FPGA device is with the configurator after the process compiling mostly, adopt JTAG (Joint Test Action Group, combined testing action group) configuring chip PROM (the Programmable Read-only Memory of FPGA special use is downloaded and be burned onto to interface, programmable read only memory) in, after FPGA powered at every turn, the configuration data that is kept among the PROM transferred to FPGA, finished the configuration effort to FPGA.Referring to shown in Figure 1, be that FPGA uses PROM to carry out from the circuit theory diagrams of string configuration mode in the prior art.The FPGA that links to each other with PROM is main FPGA device, the configuration data of preserving among the PROM transfers to the input DIN port of main FPGA, finish the configuration to main device, configuration data is exported the serial transmission of DOUT mouth to the input DIN port from the FPGA device through it again, finish the configuration from device, the mode of this daisy chain can be finished the configuration to multiple FPGA.
But, all will be configured it after this configuration mode FPGA powers at every turn, but himself not having nonvolatile storage space, configuration data must be kept in the special-purpose configuring chip, has increased system cost.In addition, configurator is kept among the configuring chip PROM, finishes the configuration to FPGA, can't realize the Configuration Online of FPGA.
The utility model content
In view of this, fundamental purpose of the present utility model provides a kind of on-site programmable gate array FPGA configuration-system based on microprocessor, FPGA does not have self nonvolatile storage space in the solution prior art, FPGA is configured the problem that must use the specialized configuration chip.
For addressing the above problem, the technical scheme that the utility model provides is as follows:
A kind of on-site programmable gate array FPGA configuration-system based on microprocessor, described system comprises:
Microprocessor and main fpga chip;
Described microprocessor links to each other with described main fpga chip;
Described microprocessor is used for configuration data is transferred to described main fpga chip, to dispose described main fpga chip.
Accordingly, described system also comprises:
One or more pieces are from fpga chip;
Described main fpga chip and described one or more pieces link to each other from serial between the fpga chip;
Described microprocessor links to each other respectively from fpga chip with described one or more pieces;
Described microprocessor be used for configuration data transfer to described one or more pieces from fpga chip, with dispose described one or more pieces from fpga chip.
Accordingly, the first IO interface of described microprocessor links to each other with the series arrangement data input pin of described main fpga chip;
The second IO interface of described microprocessor links to each other with the low level asynchronous reset pin of described main fpga chip;
The 3rd IO interface of described microprocessor links to each other with the initialization pin of described main fpga chip;
The 4th IO interface of described microprocessor links to each other with the configuration successful sign pin of described main fpga chip;
The 5th IO interface of described microprocessor links to each other with the clock pins of described main fpga chip.
Accordingly, the series arrangement data output pin of described main fpga chip links to each other with the described series arrangement data input pin from fpga chip of the first order;
Described series arrangement data output pin from fpga chip links to each other with the described series arrangement data input pin from fpga chip of next stage;
The second IO interface of described microprocessor links to each other respectively with whole described low level asynchronous reset pins from fpga chip;
The 3rd IO interface of described microprocessor links to each other respectively with whole described initialization pins from fpga chip;
The 4th IO interface of described microprocessor links to each other respectively with whole described configuration mode base pin selections from fpga chip;
The 5th IO interface of described microprocessor links to each other respectively with whole described clock pins from fpga chip.
Accordingly, described system also comprises:
The first resistance, a plurality of configuration mode base pin selections of described main fpga chip link to each other with an end of described the first resistance respectively, and the other end of described the first resistance links to each other with low-tension supply.
Accordingly, described system also comprises:
One or more the second resistance, each described a plurality of configuration mode base pin selection from fpga chip links to each other with an end of described second resistance respectively, and the other end of each described the second resistance links to each other with low-tension supply.
Accordingly, described system also comprises:
The 3rd resistance, the 4th resistance and the 5th resistance;
One end of described the 3rd resistance is connected on the line between the low level asynchronous reset pin of the second IO interface of described microprocessor and described main fpga chip, and the other end of described the 3rd resistance links to each other with low-tension supply;
One end of described the 4th resistance is connected on the line between the initialization pin of the 3rd IO interface of described microprocessor and described main fpga chip, and the other end of described the 4th resistance links to each other with low-tension supply;
One end of described the 5th resistance is connected on the line between the configuration successful sign pin of the 4th IO interface of described microprocessor and described main fpga chip, and the other end of described the 5th resistance links to each other with low-tension supply.
Accordingly, described system also comprises:
Host computer links to each other with described microprocessor, transfers to described microprocessor for generation of described configuration data and with serial ports or the Ethernet interface of described configuration data by described microprocessor.
Accordingly, described microprocessor also is used for storing described configuration data.
Accordingly, the first IO interface of described microprocessor is used for the series arrangement data input pin by described main fpga chip, exports described configuration data to described main fpga chip;
The second IO interface of described microprocessor is used for by described main fpga chip or described low level asynchronous reset pin from fpga chip, to described main fpga chip or described from fpga chip output low level asynchronous reset signal;
The 3rd IO interface of described microprocessor is used for by described main fpga chip or described initialization pin from fpga chip, inputs described main fpga chip or the described initializing signal that sends from fpga chip;
The 4th IO interface of described microprocessor is used for by described main fpga chip or described configuration successful sign pin from fpga chip, inputs described main fpga chip or the described configuration successful signal that sends from fpga chip;
The 5th IO interface of described microprocessor is used for by described main fpga chip or described clock pins from fpga chip, to described main fpga chip or described from the fpga chip clock signal;
The series arrangement data output pin of described main fpga chip is used for exporting described configuration data to the first order is described from fpga chip by the described series arrangement data input pin from fpga chip of the first order;
Described series arrangement data output pin from fpga chip is used for exporting described configuration data to next stage is described from fpga chip by the described series arrangement data input pin from fpga chip of next stage.
This shows, the utlity model has following beneficial effect:
In Embedded System Design, utilize that existing microprocessor is connected with fpga chip in the system, microprocessor has erasable nonvolatile memory, utilize the store configuration data of the storer that microprocessor carries, with the configuration fpga chip, saved special-purpose PROM, circuit structure is simplified, saved system cost, can also use host computer to pass through serial ports or Ethernet interface real-time update transmission configuration data, FPGA has been realized Configuration Online.
Description of drawings
Fig. 1 is the circuit theory diagrams that use PROM configuration FPGA in the prior art;
Fig. 2 is that the utility model is realized the structural representation based on the FPGA configuration-system of microprocessor;
Fig. 3 is that the utility model is realized a kind of physical circuit connection diagram based on the FPGA configuration-system of microprocessor;
Fig. 4 is the required pin sequential chart of the utility model configuration fpga chip.
Embodiment
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments the utility model embodiment is described in further detail.
The utility model is based on the on-site programmable gate array FPGA configuration-system of microprocessor, not have self nonvolatile storage space for FPGA in the prior art, FPGA is configured the problem that to use the specialized configuration chip, configuration data with microprocessor stores FPGA is proposed, the PROM of instead of dedicated finishes the configuration to fpga chip.
Based on above-mentioned thought, referring to shown in Figure 2, the utility model comprises based on the on-site programmable gate array FPGA configuration-system of microprocessor:
Simultaneously, native system can also comprise:
One or more pieces are from fpga chip 3; Main fpga chip and one or more pieces link to each other from serial between the fpga chip; Microprocessor links to each other respectively from fpga chip with one or more pieces; Microprocessor is used for configuration data is transferred to one or more pieces from fpga chip, to dispose one or more pieces from fpga chip.
Wherein, microprocessor can be selected the single-chip microcomputer of STM32f103ZET6 model, the integrated cortex kernel of this model microprocessor, simultaneously integrated abundant peripheral functional modules.Main fpga chip and can to select model from fpga chip be the FPGA device of XC3S400, this chip belongs to Spartan3 series a of Xilinx company, high-performance, low-power consumption, can unlimitedly programme, the equivalent gate number reaches 400,000, can adopt main string, from string, main also, from also, the mode such as JTAG is configured.
Referring to shown in Figure 3, be system when comprising microprocessor, main fpga chip and a slice from fpga chip, adopt from the circuit connection diagram of string mode to the fpga chip configuration.
First IO interface (PA1) of microprocessor 1 links to each other with the series arrangement data input pin (DIN) of main fpga chip 2; Second IO interface (PA2) of microprocessor 1 reaches from the low level asynchronous reset pin (PROG_B) of fpga chip 3 with main fpga chip 2 and links to each other; The 3rd IO interface (PA3) of microprocessor 1 reaches from the initialization pin (INIT_B) of fpga chip 3 with main fpga chip 2 and links to each other; The 4th IO interface (PG3) of microprocessor 1 reaches from the configuration successful sign pin (DONE) of fpga chip 3 with main fpga chip 2 and links to each other; The 5th IO interface (PF0) of microprocessor 1 reaches from the clock pins (CCLK) of fpga chip 3 with main fpga chip 2 and links to each other; The series arrangement data output pin (DOUT) of main fpga chip 2 links to each other with series arrangement data input pin (DIN) from fpga chip 3.
More than system comprises a slice from fpga chip the time, the series arrangement data output pin (DOUT) of main fpga chip 2 need to be linked to each other with the series arrangement data input pin (DIN) of the first order from fpga chip 3; Link to each other with the series arrangement data input pin (DIN) of next stage from fpga chip 3 from the series arrangement data output pin (DOUT) of fpga chip 3; Second IO interface (PA2) of microprocessor 1 and main fpga chip 2 and all link to each other respectively from the low level asynchronous reset pin (PROG_B) of fpga chip 3; The 3rd IO interface (PA3) of microprocessor 1 and main fpga chip 2 and all link to each other respectively from the initialization pin (INIT_B) of fpga chip 3; The 4th IO interface (PG3) of microprocessor 1 and main fpga chip 2 and all link to each other respectively from the configuration mode base pin selection (DONE) of fpga chip 3; The 5th IO interface (PF0) of microprocessor 1 and main fpga chip 2 and all link to each other respectively from the clock pins (CCLK) of fpga chip 3.
In addition, the FPGA configuration-system can also comprise: the first resistance (R1), one or more the second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4) and the 5th resistance (R5), play the effect that keeps the pin high level.
Wherein, a plurality of configuration mode base pin selections (M0, M1, M2) of main fpga chip 2 link to each other with an end of the first resistance (R1) respectively, and the other end of the first resistance (R1) links to each other with low-tension supply;
Each a plurality of configuration mode base pin selection (M0, M1, M2) from fpga chip 3 links to each other with an end of second resistance (R2) respectively, and the other end of each the second resistance (R2) links to each other with low-tension supply;
One end of the 3rd resistance (R3) is connected on the line between the low level asynchronous reset pin (PROG_B) of second IO interface (PA2) of microprocessor 1 and main fpga chip 2, and the other end of the 3rd resistance (R3) links to each other with low-tension supply;
One end of the 4th resistance (R4) is connected on the line between the initialization pin (INIT_B) of the 3rd IO interface (PA3) of microprocessor 1 and main fpga chip 2, and the other end of the 4th resistance (R4) links to each other with low-tension supply;
One end of the 5th resistance (R5) is connected on the line between the configuration successful sign pin (DONE) of the 4th IO interface (PG3) of microprocessor 1 and main fpga chip 2, and the other end of the 5th resistance (R5) links to each other with low-tension supply.
Preferably, the resistance of the first resistance (R1), the second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4) is 4.7k Ω, the resistance of the 5th resistance (R5) is 330 Ω, and the low-tension supply that is connected with R1, R2, R3, R4, R5 is 2.5V.
In addition, the voltage interface of microprocessor (VCC) can link to each other with the 3.3V low-tension supply, and microprocessor, main fpga chip reach earth terminal (GND) ground connection from fpga chip.
When employing was used microprocessor configuration principal and subordinate FPGA from string mode, the pin function of used fpga chip was as follows:
Configuration mode base pin selection (M[2:0]) is used for configuration mode and selects, and M2, M1, M0 all connect and draw resistance (R1 or R2), i.e. M[2:0]=' 111 ' Shi Weicong goes here and there configuration mode;
Series arrangement data input pin (DIN) is used for the input of series arrangement data, and the configuration data bit stream is through this pin input FPGA;
Low level asynchronous reset pin (PROG_B) is used for low level asynchronous reset FPGA internal logic, and after the FPGA internal logic was resetted fully, this pin can be indicated high level, when this pin when being high, could dispose FPGA;
Initialization pin (INIT_B), rising edge is effective, during to the high level saltus step, the sampling configuration mode is M[2:0 by low level] value, determine configuration mode; If occur configuration error in the layoutprocedure, INIT_B will present low level;
Configuration successful sign pin (DONE) is low level when resetting, if configuration successful then is high level;
Clock pins (CCLK) is used for configurable clock generator, and external clock is provided by microprocessor, and rising edge is effective;
Series arrangement data output pin (DOUT) is used for serial data output, and this pin links to each other with the DIN pin of next stage FPGA, is used for daisy-chained configuration.
In microprocessor STM32f103ZET6, most of pins all are multi-functional pins, can select pin function by the port arrangement register, and its universal input and output port can be configured to input, output and specific function, the read-write register corresponding positions just is equivalent to reading or writing respective pins.
First IO interface (PA1) of microprocessor is used for the series arrangement data input pin (DIN) by main fpga chip, to main fpga chip output configuration;
Second IO interface (PA2) of microprocessor is used for by main fpga chip or from the low level asynchronous reset pin (PROG_B) of fpga chip, to main fpga chip or from fpga chip output low level asynchronous reset signal;
The 3rd IO interface (PA3) of microprocessor is used for by main fpga chip or from the initialization pin (INIT_B) of fpga chip, inputs main fpga chip or from the initializing signal of fpga chip transmission;
The 4th IO interface (PG3) of microprocessor is used for by main fpga chip or from the configuration successful sign pin (DONE) of fpga chip, inputs main fpga chip or from the configuration successful signal of fpga chip transmission;
The 5th IO interface (PF0) of microprocessor is used for by main fpga chip or from the clock pins (CCLK) of fpga chip, to main fpga chip or from the fpga chip clock signal;
The series arrangement data output pin (DOUT) of main fpga chip is used for by the series arrangement data input pin (DIN) of the first order from fpga chip, to the first order from the fpga chip output configuration;
From the series arrangement data output pin (DOUT) of fpga chip, be used for by the series arrangement data input pin (DIN) of next stage from fpga chip, to next stage from the fpga chip output configuration.
The principle of work that native system is configured FPGA is to utilize the configuration sequential of the universal input/output interface simulation fpga chip of microprocessor, referring to shown in Figure 4, that the needed concrete configuration sequential of fpga chip is from the configuration sequential chart of string mode configuration FPGA:
After system powers on, with the PROG_B pin drag down for low level with the FPGA internal logic that resets, reconfigure FPGA, behind the internal logic that fully resets (about 2 μ s), the PROG_B pin set high be high level;
The INIT_B pin keeps low level, after the PROG_B pin sets high greater than 2ms, the INIT_B pin is set high, in INIT_B pin moment of saltus step from low to high, sampling configuration mode base pin selection M[2:0], as M[2:0]=' 111 ' time, system adopts from the string configuration mode;
Behind the sampling configuration mode, microprocessor just can be given FPGA configurable clock generator CCLK and configuration data DIN, and at each rising edge of CCLK pin, every (bit) data are imported into the DIN pin, if make a mistake in the layoutprocedure, then the INIT_B pin presents low level;
All configuration datas transmit and finish, and CRC check is errorless, and then the DONE pin presents high level, otherwise is low level, dispose unsuccessfully, reconfigure; After the DONE pin is height, discharge the overall situation ternary (GTS), activate pin, discharge whole set, reset signal; It is effective that global write enables (GWE), begins to carry out the logic in the configuring area, and configuration is finished.
Therefore, can carry out conversion process to the PROM configuration file, produce configuration data, and after system program compiles together, with the configuration data programming and be kept in the microprocessor, by microprocessor fpga chip is configured.Also can by host computer with configuration data by microprocessor serial ports or after Ethernet interface transfers to microprocessor, by microprocessor fpga chip is configured.Concrete, the workflow of finishing the configuration fpga chip can be:
Step 101: by the PROG_B pin of fpga chip, to fpga chip output low level asynchronous reset signal, putting the PROG_B pin is low level 2 μ s, and putting P ROG_B pin is high level 2ms;
Step 102: by the INIT_B pin of fpga chip, the initializing signal that the input fpga chip sends judges whether the INIT_B pin status is high, if so, enters step 103, if not, returns step 102;
Step 103: get configuration data, by the CCLK pin of fpga chip, to the fpga chip clock signal, when CCLK pin rising edge, the DIN pin by fpga chip writes the DIN pin with the configuration data step-by-step;
Step 104: judge whether configuration data takes, and if so, enters step 105, if not, returns step 103;
Step 105: by the DONE pin of fpga chip, the configuration successful signal that the input fpga chip sends judges whether the DONE pin is high level, and if so, configuration successful if not, is returned step 101, again fpga chip is configured.
Like this, utilize that existing microprocessor is connected with fpga chip in the system, microprocessor has erasable nonvolatile memory, utilize the store configuration data of the storer that microprocessor carries, after system powers at every turn, by microprocessor configuration data is write FPGA in the mode of serial, with the configuration fpga chip, employing is from the configuration mode of string, only need five signal wires to connect, saved FPGA specialized configuration chip PROM, wiring is easy, circuit structure is simplified, and has saved system cost and volume.
In addition, but FPGA has the dirigibility of repeated configuration, in embedded system, can use the long-range data transfer that is configured of host computer by serial ports or Ethernet interface, need not carry out erasable to microprocessor, to FP GA Configuration Online, the reconfiguration system function is for device intelligence on-line maintenance function upgrading provides possibility.
Need to prove that each embodiment adopts the mode of going forward one by one to describe in this instructions, what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For the disclosed system of embodiment or device, because it is corresponding with the disclosed method of embodiment, so description is fairly simple, relevant part partly illustrates referring to method and gets final product.
Also need to prove, in this article, relational terms such as the first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint and have the relation of any this reality or sequentially between these entities or the operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby not only comprise those key elements so that comprise process, method, article or the equipment of a series of key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.Do not having in the situation of more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
The method of describing in conjunction with embodiment disclosed herein or the step of algorithm can directly use the software module of hardware, processor execution, and perhaps the combination of the two is implemented.Software module can place the storage medium of any other form known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or the technical field.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the utility model.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation that does not break away from spirit or scope of the present utility model, realize in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. on-site programmable gate array FPGA configuration-system based on microprocessor is characterized in that described system comprises:
Microprocessor and main fpga chip;
Described microprocessor links to each other with described main fpga chip;
Described microprocessor is used for configuration data is transferred to described main fpga chip, to dispose described main fpga chip.
2. system according to claim 1 is characterized in that, described system also comprises:
One or more pieces are from fpga chip;
Described main fpga chip and described one or more pieces link to each other from serial between the fpga chip;
Described microprocessor links to each other respectively from fpga chip with described one or more pieces;
Described microprocessor be used for configuration data transfer to described one or more pieces from fpga chip, with dispose described one or more pieces from fpga chip.
3. system according to claim 2 is characterized in that,
The first IO interface of described microprocessor links to each other with the series arrangement data input pin of described main fpga chip;
The second IO interface of described microprocessor links to each other with the low level asynchronous reset pin of described main fpga chip;
The 3rd IO interface of described microprocessor links to each other with the initialization pin of described main fpga chip;
The 4th IO interface of described microprocessor links to each other with the configuration successful sign pin of described main fpga chip;
The 5th IO interface of described microprocessor links to each other with the clock pins of described main fpga chip.
4. system according to claim 2 is characterized in that,
The series arrangement data output pin of described main fpga chip links to each other with the described series arrangement data input pin from fpga chip of the first order;
Described series arrangement data output pin from fpga chip links to each other with the described series arrangement data input pin from fpga chip of next stage;
The second IO interface of described microprocessor links to each other respectively with whole described low level asynchronous reset pins from fpga chip;
The 3rd IO interface of described microprocessor links to each other respectively with whole described initialization pins from fpga chip;
The 4th IO interface of described microprocessor links to each other respectively with whole described configuration mode base pin selections from fpga chip;
The 5th IO interface of described microprocessor links to each other respectively with whole described clock pins from fpga chip.
5. system according to claim 1 is characterized in that, described system also comprises:
The first resistance, a plurality of configuration mode base pin selections of described main fpga chip link to each other with an end of described the first resistance respectively, and the other end of described the first resistance links to each other with low-tension supply.
6. system according to claim 2 is characterized in that, described system also comprises:
One or more the second resistance, each described a plurality of configuration mode base pin selection from fpga chip links to each other with an end of described second resistance respectively, and the other end of each described the second resistance links to each other with low-tension supply.
7. system according to claim 2 is characterized in that, described system also comprises:
The 3rd resistance, the 4th resistance and the 5th resistance;
One end of described the 3rd resistance is connected on the line between the low level asynchronous reset pin of the second IO interface of described microprocessor and described main fpga chip, and the other end of described the 3rd resistance links to each other with low-tension supply;
One end of described the 4th resistance is connected on the line between the initialization pin of the 3rd IO interface of described microprocessor and described main fpga chip, and the other end of described the 4th resistance links to each other with low-tension supply;
One end of described the 5th resistance is connected on the line between the configuration successful sign pin of the 4th IO interface of described microprocessor and described main fpga chip, and the other end of described the 5th resistance links to each other with low-tension supply.
8. each described system is characterized in that according to claim 1-7, and described system also comprises:
Host computer links to each other with described microprocessor, transfers to described microprocessor for generation of described configuration data and with serial ports or the Ethernet interface of described configuration data by described microprocessor.
9. each described system according to claim 8 is characterized in that, described microprocessor also is used for storing described configuration data.
10. according to claim 3 or 4 described systems, it is characterized in that,
The first IO interface of described microprocessor is used for the series arrangement data input pin by described main fpga chip, exports described configuration data to described main fpga chip;
The second IO interface of described microprocessor is used for by described main fpga chip or described low level asynchronous reset pin from fpga chip, to described main fpga chip or described from fpga chip output low level asynchronous reset signal;
The 3rd IO interface of described microprocessor is used for by described main fpga chip or described initialization pin from fpga chip, inputs described main fpga chip or the described initializing signal that sends from fpga chip;
The 4th IO interface of described microprocessor is used for by described main fpga chip or described configuration successful sign pin from fpga chip, inputs described main fpga chip or the described configuration successful signal that sends from fpga chip;
The 5th IO interface of described microprocessor is used for by described main fpga chip or described clock pins from fpga chip, to described main fpga chip or described from the fpga chip clock signal;
The series arrangement data output pin of described main fpga chip is used for exporting described configuration data to the first order is described from fpga chip by the described series arrangement data input pin from fpga chip of the first order;
Described series arrangement data output pin from fpga chip is used for exporting described configuration data to next stage is described from fpga chip by the described series arrangement data input pin from fpga chip of next stage.
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| CN106201629A (en) * | 2016-07-22 | 2016-12-07 | 北京广利核系统工程有限公司 | A kind of method and apparatus to the programming of multi-disc target FPGA |
| CN106569858A (en) * | 2016-10-31 | 2017-04-19 | 锐捷网络股份有限公司 | Method for updating configuration files and circuit board |
| CN106569858B (en) * | 2016-10-31 | 2019-08-20 | 锐捷网络股份有限公司 | A kind of update method and circuit board of configuration file |
| CN108227607A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method of simplified circuit board arrangement circuit |
| CN108227607B (en) * | 2016-12-14 | 2020-06-30 | 中国航空工业集团公司西安航空计算技术研究所 | Method for simplifying circuit configuration circuit of circuit board |
| CN110008172A (en) * | 2019-04-02 | 2019-07-12 | 广东高云半导体科技股份有限公司 | A kind of system on chip |
| CN112650543A (en) * | 2020-12-21 | 2021-04-13 | 北京神州飞航科技有限责任公司 | FPGA dynamic configuration method |
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