CN110008172A - A kind of system on chip - Google Patents
A kind of system on chip Download PDFInfo
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- CN110008172A CN110008172A CN201910263327.0A CN201910263327A CN110008172A CN 110008172 A CN110008172 A CN 110008172A CN 201910263327 A CN201910263327 A CN 201910263327A CN 110008172 A CN110008172 A CN 110008172A
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- control unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
Abstract
The application provides a kind of system on chip, which includes micro-control unit and field programmable gate array；Wherein, micro-control unit includes: micro-control unit kernel circuitry；First input/output port couples micro-control unit kernel circuitry；Wherein, field programmable gate array includes: the second input/output port, the first input/output port is coupled, for coupling resource outside piece；Usb interface unit couples micro-control unit kernel circuitry.The application realizes the system on chip that MCU and FPGA is formed, and improves the interface capability of software and hardware interconnection, and can support USB interface, realizes the diversification of function.
Description
Technical field
The disclosed embodiment of the application is related to field of circuit technology, and more specifically, is related to a kind of system on chip.
Background technique
With the rapid development of information technology, general processor be increasingly difficult in calculated performance with meet it is increasingly huge,
Diversified data processing needs, while tradition FPGA (Field Programmable Gate Array, field programmable gate
Array) and CPU (Central Processing Unit, central processing unit) as discrete device function and performance increasingly
It is difficult to meet increasingly huge, diversified data processing needs.
Summary of the invention
To solve the above problems, the application proposes a kind of system on chip, the system on chip that MCU and FPGA is formed is realized,
The interface capability of software and hardware interconnection is improved, and can support USB interface, realizes the diversification of function.
The technical solution that the application uses is: providing a kind of system on chip, which includes micro-control unit
And field programmable gate array；Wherein, micro-control unit includes: micro-control unit kernel circuitry；First input/output port, coupling
Connect micro-control unit kernel circuitry；Wherein, field programmable gate array includes: the second input/output port, the first input of coupling
Output port, for coupling resource outside piece；Usb interface unit couples micro-control unit kernel circuitry.
Wherein, usb interface unit includes: APB bus expansion interface, couples micro-control unit kernel circuitry；USB interface control
Circuit processed couples APB bus expansion interface；USB interface couples usb control circuit.
Wherein, usb control circuit includes: APB bus slave management sub-circuit, couples APB bus expansion interface；
APB bridges sub-circuit, and coupling APB bus slave manages sub-circuit；Coding/decoding sub-circuit, coupling APB bridge joint sub-circuit and
USB interface.
Wherein, the first input/output port includes: UART interface, passes through APB bus and micro-control unit kernel circuitry coupling
It connects, for realizing the interaction of resource outside micro-control unit kernel circuitry and piece；GPIO interface passes through ahb bus and microcontroller list
First kernel circuitry coupling, for realizing the interaction of resource outside micro-control unit kernel circuitry and piece.
Wherein, system on chip further includes first selector and second selector, and field programmable gate array further includes first
Phase inverter；First input/output port includes input port, output port, multiplexing port and enable port, input port and
The first input end of the coupling of two input/output ports, output port and first selector couples, the second input of first selector
Recovery selection signal, control terminal and multiplexing port is terminated to couple, the first input end of enable port and second selector couples,
Second input terminal of second selector receives multiplexing selection signal, control terminal and multiplexing port and couples, first selector and second
The output end of selector is coupled with the input terminal of the first phase inverter and control terminal respectively, the output end of the first phase inverter and second defeated
Enter output port coupling.
Wherein, field programmable gate array further include: clock and reset circuit are coupled with micro-control unit kernel circuitry,
For providing clock and reset signal to micro-control unit kernel circuitry；And/or memory, with micro-control unit kernel circuitry coupling
It connects, is used for storage system program.
Wherein, clock and reset circuit include: selector, for receiving two clock signals, and in response to selection signal and
Export one in two clock signals；The output end of latch, first input end and selector couples, output end with it is micro-
The coupling of control unit kernel circuitry, is supplied to micro-control unit kernel circuitry for one in two clock signals.
Wherein, clock and reset circuit further include: electrification reset pin, receive power-on reset signal, and with microcontroller list
First kernel circuitry electric coupling, for providing power-on reset signal to micro-control unit kernel circuitry；System reset pin receives system
Unite reset signal, and with micro-control unit kernel circuitry electric coupling, for give micro-control unit kernel circuitry provide system reset
Signal；And second phase inverter, the second input terminal thermocouple of input terminal and electrification reset pin electric coupling, output end and latch
It connects.
Wherein, memory includes read-only memory and random access memory；Wherein, read-only memory and arbitrary access are deposited
Reservoir is coupled by ahb bus and micro-control unit kernel circuitry.
Wherein, read-only memory includes read-only storage control, passes through ahb bus and micro-control unit kernel circuitry coupling
It connects, for realizing interaction and read operation with micro-control unit kernel circuitry, write operation and erasing operation；Random access memory
Device includes random access memory controller, is coupled by ahb bus and micro-control unit kernel circuitry, for realizing with microcontroller
The interaction and read operation of unit kernel circuitry and write operation.
The beneficial effect of the application has: micro-control unit kernel circuitry passes through the first input/output port and field-programmable
The system on chip that MCU adds FPGA is realized in gate array coupling, improves the interface capability of software and hardware interconnection, and field programmable gate
Second input/output port of array can couple the outer resource of piece of outside, realize and expand to external interface, and outside realization and piece
In addition the interaction of resource also achieves the extension of USB interface, can meet huge, diversified data processing needs.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.Wherein:
Fig. 1 is the structural schematic diagram of system on chip first embodiment provided by the present application；
Fig. 2 is the structural schematic diagram of system on chip second embodiment provided by the present application；
Fig. 3 is the structural schematic diagram of APB bus expansion interface and usb control circuit in Fig. 2；
Fig. 4 is the structural schematic diagram of system on chip 3rd embodiment provided by the present application；
Fig. 5 is the connection schematic diagram of first the second input/output port of input/output port in Fig. 4；
Fig. 6 is the structural schematic diagram of system on chip fourth embodiment provided by the present application；
Fig. 7 is the structural schematic diagram of micro-control unit kernel circuitry and clock and reset circuit in Fig. 6.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description.It is understood that specific embodiment described herein is only used for explaining the application, rather than to the limit of the application
It is fixed.It also should be noted that illustrating only part relevant to the application for ease of description, in attached drawing and not all knot
Structure.Based on the embodiment in the application, obtained by those of ordinary skill in the art without making creative efforts
Every other embodiment, shall fall in the protection scope of this application.
Term " first ", " second " in the application etc. be for distinguishing different objects, rather than it is specific suitable for describing
Sequence.In addition, term " includes " and " having " and their any deformations, it is intended that cover and non-exclusive include.Such as comprising
The process, method, system, product or equipment of a series of steps or units are not limited to listed step or unit, and
It is optionally further comprising the step of not listing or unit, or optionally further comprising for these process, methods, product or equipment
Intrinsic other step or units.
Referenced herein " embodiment " is it is meant that a particular feature, structure, or characteristic described can wrap in conjunction with the embodiments
It is contained at least one embodiment of the application.Each position in the description occur the phrase might not each mean it is identical
Embodiment, nor the independent or alternative embodiment with other embodiments mutual exclusion.Those skilled in the art explicitly and
Implicitly understand, embodiment described herein can be combined with other embodiments.
Refering to fig. 1, Fig. 1 is the structural schematic diagram of system on chip first embodiment provided by the present application, the system on chip 10
Including micro-control unit (Microcontroller Unit, MCU) 11 and field programmable gate array (FPGA) 12.
Wherein, micro-control unit 11 includes micro-control unit kernel circuitry 111 and the first input/output port 112, scene
Programmable gate array 12 includes the second input/output port 121 and usb interface unit 122.First input/output port 112 with it is micro-
Control unit kernel circuitry 111 couples, and the second input/output port 121 and the first input/output port 112 couple, and are used for coupling
The outer resource of contact pin.USB (Universal Serial Bus) interface unit 122 and micro-control unit kernel circuitry 111 couple, and use
In connection micro-control unit kernel circuitry 111 and external USB interface device.
Optionally, usb interface unit 122 therein specifically can be USB Type-C interface, can be used for and external electrical
Source is coupled to carry out data interaction.
In the present embodiment, micro-control unit kernel circuitry 111 passes through the first input/output port 112 and field-programmable
Gate array 12 couples, and realizes the system on chip that MCU adds FPGA, improves the interface capability of software and hardware interconnection, and field-programmable
Gate array 12 includes the second input/output port 121 and usb interface unit 122, wherein the first input/output port 112 can be with
Second input/output port 121 forms coupling, carries out data interaction, and the second input/output port 121 can couple outside external piece
Resource is realized and expands to external interface, and the interaction of realization and the outer resource of piece, can meet huge, diversified data processing
Demand.
It is different from the prior art, in the present embodiment, micro-control unit kernel circuitry is by the first input/output port and now
The system on chip that MCU adds FPGA is realized in field programmable gate array coupling, improves the interface capability of software and hardware interconnection, and scene
Second input/output port of programmable gate array can couple the outer resource of external piece, realize and expand to external interface, and is real
Now with the interaction of resource outside piece, the extension of USB interface is in addition also achieved, huge, diversified data processing needs can be met.
Referring to Fig.2, Fig. 2 is the structural schematic diagram of system on chip second embodiment provided by the present application, the system on chip 10
Including micro-control unit (Microcontroller Unit, MCU) 11 and field programmable gate array (FPGA) 12.
Wherein, micro-control unit 11 includes micro-control unit kernel circuitry 111 and the first input/output port 112, scene
Programmable gate array 12 includes the second input/output port 121 and usb interface unit 122.First input/output port 112 with it is micro-
Control unit kernel circuitry 111 couples, and the second input/output port 121 and the first input/output port 112 couple, and are used for coupling
The outer resource of contact pin.Usb interface unit 122 and micro-control unit kernel circuitry 111 couple, for connecting nuclear power in micro-control unit
Road 111 and external USB interface device.
In the present embodiment, usb interface unit 122 includes that APB (Advanced Peripheral Bus) bus extension connects
Mouth 1221, usb control circuit 1222 and usb 1 223.
Wherein, APB bus expansion interface 1221 couples micro-control unit kernel circuitry 111, usb control circuit 1222
APB bus expansion interface 1221 is coupled, usb 1 223 couples usb control circuit 1222.
As shown in figure 3, Fig. 3 is the structural schematic diagram of APB bus expansion interface and usb control circuit in Fig. 2, one
In optional embodiment, usb control circuit 1222 includes APB bus slave management sub-circuit 1222a, APB bridge joint
Circuit 1222b and coding/decoding sub-circuit 1222c.
Wherein, APB bus slave management sub-circuit 1222a couples APB bus expansion interface 1221, APB bridge joint electricity
Road 1222b couples APB bus slave and manages sub-circuit 1222a, and coding/decoding sub-circuit 1222c couples APB and bridges sub-circuit
1222b and usb 1 223.
Specifically, APB bus expansion interface 1221 includes multiple pins, is respectively as follows: clock signal, reset signal, address
Signal writes that enabled, write data bus, bus strobe, bus be enabled, end mark position, read data bus, these pins distinguish coupling
It is connected to usb control circuit 1222, can specifically be coupled to APB bus slave management sub-circuit 1222a.
Specifically, usb control circuit 1222 includes multiple pins, is respectively as follows: 1 transmitting terminal of channel, channel 1 receives
End, channel 1 control signal, 1 colonel's resistance of channel, the lower school resistance in channel 1, the control of 1 voltage of channel, 2 transmitting terminal of channel, channel 2
Receiving end, channel 2 control signal, 2 colonel's resistance of channel, the lower school resistance in channel 2, the control of 2 voltage of channel, these pins can divide
It is not coupled to usb 1 223.
It is the structural schematic diagram of system on chip 3rd embodiment provided by the present application, the system on chip 10 refering to Fig. 4, Fig. 4
Including micro-control unit (Microcontroller Unit, MCU) 11 and field programmable gate array (FPGA) 12.
Wherein, micro-control unit 11 includes micro-control unit kernel circuitry 111 and the first input/output port 112, scene
Programmable gate array 12 includes the second input/output port 121 and usb interface unit 122.First input/output port 112 with it is micro-
Control unit kernel circuitry 111 couples, and the second input/output port 121 and the first input/output port 112 couple, and are used for coupling
The outer resource of contact pin.Usb interface unit 122 and micro-control unit kernel circuitry 111 couple, for connecting nuclear power in micro-control unit
Road 111 and external USB interface device.
Optionally, in the present embodiment, the first input/output port 112 includes UART (Universal
Asynchronous Receiver/Transmitter, universal asynchronous receiving-transmitting transmission) interface 1121 and GPIO (General
Purpose Input Output, universal input/output) interface 1122.
UART interface 1121 passes through APB (Advanced Peripheral Bus) bus and micro-control unit kernel circuitry
Coupling, for realizing the interaction of resource outside micro-control unit kernel circuitry and piece；GPIO interface 1122 passes through AHB (Advanced
High Performance Bus) bus and micro-control unit kernel circuitry couple, for realizing micro-control unit kernel circuitry
With the interaction of resource outside piece.
Micro-control unit kernel circuitry 111 sends chip selection signal, with select UART interface 1121 or GPIO interface 1122 with
The second input/output port 121 in field programmable gate array 12, so it is defeated with second in field programmable gate array 12
Enter the outer resource interaction of piece of 121 electric couplings of output port.
As shown in figure 5, Fig. 5 is the connection schematic diagram of first the second input/output port of input/output port in Fig. 4.
In the present embodiment, the first input/output port 112 includes that the input of input and output bridgt circuit 112a and first is defeated
Outgoing interface 112b, wherein input and output bridgt circuit 112a may include multiple pins, is respectively as follows: clock signal, resets letter
Number, chip selection signal, read address signal, write enable signal, preparatory signal, writing address signal, preparation output signal, answer signal.
Optionally, system on chip 10 further includes first selector 13, second selector 14 and the first phase inverter 15.First is defeated
Enter output interface 112b and passes through first selector 13 and second selector 14 and the first phase inverter 15 and programmable gate array 12
The coupling of the second input/output port 121, i.e., the coupling of the first input/output port 112 with FPGA is realized using the resource of FPGA
Relationship, and then realize the interaction of MCU kernel circuitry 110 and the outer resource of piece.
For in the first input/output port 112 UART interface 1121 and GPIO interface 1122 for, first input it is defeated
Outgoing interface 112b includes input port, output port, multiplexing port and enable port.That is, 1121 He of UART interface
GPIO interface 1122 all has input port, output port, multiplexing port and enable port.In other embodiments, first is defeated
Entering output interface 112b further includes interruptive port.
Specifically, the first input end of output port and first selector 13 couples, the second input of first selector 13
It terminates recovery selection signal, control terminal and multiplexing port to couple, the first input end coupling of enable port and second selector 14
It connects, the second input terminal of second selector 14 receives multiplexing selection signal, control terminal and multiplexing port and couples, first selector 13
Coupled respectively with the input terminal of the first phase inverter 15 and control terminal with the output end of second selector 14, the first phase inverter 15 it is defeated
Outlet and the second input/output port 121 couple.
It is the structural schematic diagram of system on chip fourth embodiment provided by the present application, the system on chip 10 refering to Fig. 6, Fig. 6
Including micro-control unit 11 and field programmable gate array 12.
Wherein, micro-control unit 11 includes micro-control unit kernel circuitry 111 and the first input/output port 112, scene
Programmable gate array 12 includes the second input/output port 121 and usb interface unit 122.First input/output port 112 with it is micro-
Control unit kernel circuitry 111 couples, and the second input/output port 121 and the first input/output port 112 couple, and are used for coupling
The outer resource of contact pin.Usb interface unit 122 and micro-control unit kernel circuitry 111 couple, for connecting nuclear power in micro-control unit
Road 111 and external USB interface device.
In the present embodiment, field programmable gate array 12 further includes clock and reset circuit 123 and memory 124.
Wherein, clock and reset circuit 123 and 111 electric coupling of micro-control unit kernel circuitry, for micro-control unit
Kernel circuitry 111 provides clock and reset signal.
In the present embodiment, the clock of micro-control unit kernel circuitry 111 is provided by field programmable gate array 12
With reset signal, i.e., using FPGA realize MCU clock system, improve simultaneously using FPGA and MCU application flexibility with
Upgradability.
As shown in fig. 7, Fig. 7 is the structural schematic diagram of micro-control unit kernel circuitry and clock and reset circuit in Fig. 6.
Clock and reset circuit 123 include selector 1231.The selector 1231 is rung for receiving two clock signals
It answers selection signal and exports one in two clock signals.In one example, when one in two clock signals is external
Clock signal, another be internal clock signal.
Clock and reset circuit 123 further include oscillator 1232, and the oscillator 1232 is for generating the internal clock signal.
Clock and reset circuit 123 further include latch 1233.The first input end and selector 1231 of latch 1233
Output end coupling, output end and micro-control unit kernel circuitry 111 couple, one in two clock signals is supplied to
Micro-control unit kernel circuitry 111.
In the present embodiment, clock and reset circuit 123 provide two clocks to micro-control unit kernel circuitry 111 and believe
Number, it can choose clock signal of system of any one clock signal as micro-control unit kernel circuitry 111, meet difference and answer
With the clock demand of scene, increase the flexibility of system design.
Further, clock and reset circuit 123 further include electrification reset pin (not indicating) and system reset pin (not
Mark).Wherein electrification reset pin receive power-on reset signal, and with 111 electric coupling of micro-control unit kernel circuitry, for giving
Micro-control unit kernel circuitry 111 provides power-on reset signal.System reset pin receives systematic reset signal, and and microcontroller
111 electric coupling of unit kernel circuitry, for providing systematic reset signal to micro-control unit kernel circuitry 111.In one example,
Electrification reset pin and system reset pin can be coupled with a key respectively, when pressing the key, electrification reset pin or
System reset pin receives power-on reset signal or systematic reset signal, then, provides one to micro-control unit kernel circuitry 111
A clock signal, to start to work.
Clock and reset circuit 123 further include the second phase inverter 1234.The input terminal of second phase inverter 1234 with power on
Second input terminal electric coupling of reset pin electric coupling, output end and latch 1233.
In the present embodiment, the storage of system program is realized by the memory 124 of field programmable gate array 12, i.e.,
Memory is realized using FPGA, improves while using the flexibility and upgradability of the application of FPGA and MCU.
Optional memory 124 includes read-only memory (ROM) and random access memory (RAM), wherein read-only storage
Device and random access memory pass through ahb bus respectively and micro-control unit kernel circuitry 111 couples.
Optionally, read-only memory includes read-only storage control, passes through ahb bus and micro-control unit kernel circuitry
111 couplings, for realizing interaction and read operation with micro-control unit kernel circuitry 111, write operation and erasing operation.
Optionally, random access memory includes random storage controller, passes through ahb bus and micro-control unit kernel circuitry
111 coupling, for realizing with micro-control unit kernel circuitry 111 interaction and read operation and write operation.
It should be noted that it will be understood by those skilled in the art that read-only storage control or random access memory further include
Several storage crystal grain (die).
Those skilled in the art is apparent from, and can make while keeping the teachings of the application to device and method
Many modifications and variation.Therefore, above disclosure should be considered as only being limited by the range of appended claim.
Claims (10)
1. a kind of system on chip, which is characterized in that including micro-control unit and field programmable gate array；
Wherein, the micro-control unit includes:
Micro-control unit kernel circuitry；
First input/output port couples the micro-control unit kernel circuitry；
Wherein, the field programmable gate array includes:
Second input/output port couples first input/output port, for coupling resource outside piece；
Usb interface unit couples the micro-control unit kernel circuitry.
2. system on chip according to claim 1, which is characterized in that
The usb interface unit includes:
APB bus expansion interface couples the micro-control unit kernel circuitry；
Usb control circuit couples the APB bus expansion interface；
USB interface couples the usb control circuit.
3. system on chip according to claim 2, which is characterized in that
The usb control circuit includes:
APB bus slave manages sub-circuit, couples the APB bus expansion interface；
APB bridges sub-circuit, couples the APB bus slave management sub-circuit；
Coding/decoding sub-circuit couples the APB bridge joint sub-circuit and the USB interface.
4. system on chip according to claim 1, which is characterized in that
First input/output port includes:
UART interface is coupled by APB bus and the micro-control unit kernel circuitry, for realizing in the micro-control unit
The interaction on nuclear power road and the outer resource of piece；
GPIO interface is coupled by ahb bus and the micro-control unit kernel circuitry, for realizing in the micro-control unit
The interaction on nuclear power road and the outer resource of piece.
5. system on chip according to claim 4, which is characterized in that
The system on chip further includes first selector and second selector, and the field programmable gate array further includes first anti-
Phase device；
First input/output port includes input port, output port, multiplexing port and enable port, the input port
It is coupled with second input/output port, the first input end of the output port and the first selector couples, described
Second input terminal of first selector receives multiplexing selection signal, control terminal and the multiplexing port and couples, the enable port
It is coupled with the first input end of the second selector, the second input terminal of the second selector receives the multiplexing selection letter
Number, control terminal and the multiplexing port couple, the output end of the first selector and the second selector respectively with it is described
The input terminal and control terminal of first phase inverter couple, the output end of first phase inverter and the second input/output port coupling
It connects.
6. system on chip according to claim 1, which is characterized in that
The field programmable gate array further include:
Clock and reset circuit are coupled with the micro-control unit kernel circuitry, for the micro-control unit kernel circuitry
Clock and reset signal are provided；And/or
Memory is coupled with the micro-control unit kernel circuitry, is used for storage system program.
7. system on chip according to claim 6, which is characterized in that
The clock includes: with reset circuit
Selector for receiving two clock signals, and exports in response to selection signal one in two clock signals；
The output end of latch, first input end and the selector couples, output end and the micro-control unit kernel
Circuit coupling, is supplied to the micro-control unit kernel circuitry for one in described two clock signals.
8. system on chip according to claim 7, which is characterized in that
The clock and reset circuit further include:
Electrification reset pin, receives power-on reset signal, and with the micro-control unit kernel circuitry electric coupling, for described
Micro-control unit kernel circuitry provides the power-on reset signal；
System reset pin, receives systematic reset signal, and with the micro-control unit kernel circuitry electric coupling, for described
Micro-control unit kernel circuitry provides the systematic reset signal；And
Second input terminal of the second phase inverter, input terminal and the electrification reset pin electric coupling, output end and the latch
Electric coupling.
9. system on chip according to claim 6, which is characterized in that
The memory includes read-only memory and random access memory；
Wherein, the read-only memory and the random access memory pass through nuclear power in ahb bus and the micro-control unit
Road coupling.
10. system on chip according to claim 9, which is characterized in that
The read-only memory includes read-only storage control, is coupled by ahb bus and the micro-control unit kernel circuitry,
For realizing the interaction and read operation, write operation and erasing operation with the micro-control unit kernel circuitry；
The random access memory includes random access memory controller, passes through ahb bus and the micro-control unit kernel
Circuit coupling, for realizing with the micro-control unit kernel circuitry interaction and read operation and write operation.
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| CN201910263327.0A CN110008172A (en) | 2019-04-02 | 2019-04-02 | A kind of system on chip |
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| CN201910263327.0A CN110008172A (en) | 2019-04-02 | 2019-04-02 | A kind of system on chip |
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| CN110765066A (en) * | 2019-10-22 | 2020-02-07 | 广东高云半导体科技股份有限公司 | System on chip |
| CN110765065A (en) * | 2019-09-09 | 2020-02-07 | 广东高云半导体科技股份有限公司 | System on chip |
| CN111090556A (en) * | 2019-12-18 | 2020-05-01 | 广东高云半导体科技股份有限公司 | System on chip and USB physical layer test method |
| CN112256616A (en) * | 2020-10-22 | 2021-01-22 | 广东高云半导体科技股份有限公司 | System-level chip supporting USB and GPIO conversion and communication method |
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