CN109783416A - SPI shares method, circuit and the electronic equipment of GPIO from equipment and I2C from equipment - Google Patents
SPI shares method, circuit and the electronic equipment of GPIO from equipment and I2C from equipment Download PDFInfo
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Abstract
A kind of SPI shares method, circuit and the electronic equipment of GPIO from equipment and I2C from equipment, this method comprises: judging to need mode bus to be used for I2C mode bus or spi bus mode according to reading and writing data request；If it is I2C mode bus, by first interface to the I2C from equipment tranmitting data register signal, and pass through second interface and the I2C from equipment transmission data；If it is spi bus mode, by the first interface to the SPI from equipment tranmitting data register signal, and by the second interface to the SPI from equipment write-in data, and/or passes through third interface and read data from the SPI from equipment.Above-mentioned method and electronic equipment requests to determine by reading and writing data needs mode bus to be used, first interface and second interface are shared to save the quantity of input/output interface, the switching and mutual exclusion for realizing I2C bus and spi bus mode, have the advantages that input/output interface line is few.
Description
Technical field
The invention belongs to bus communication technical fields, and in particular to a kind of SPI shares GPIO's from equipment and I2C from equipment
Method and electronic equipment.
Background technique
Only there is provided disclose relevant background technical information to the present invention for the statement of this part, it is not necessary to so constitute first
Technology.
SPI (Serial Peripheral Interface Serial Peripheral Interface (SPI)) is a kind of serial synchronous communication agreement, by
One main equipment and one or more are formed from equipment, and main equipment starts one and the synchronous communication from equipment, to complete number
According to exchange.SPI interface is by SDI (serial date transfer), SDO (serial data output), SCK (serial shift clock), CS (from
Enable signal) four kinds of signals constitute, and CS determines the slave equipment uniquely communicated with main equipment, does not have CS signal such as, then can only
There are one from equipment, main equipment initiates to communicate by generating shift clock.When communication, data are exported by SDO, SDI input,
Data rise or fall clock signal along being exported by SDO, are read on back to back down or up edge by SDI, are passed through in this way
The transmission of 8/16 data is completed in the change for crossing 8/16 clock.
I2C uses two interface communications, wherein one is serial data interface (SDA), a serial clock interface (SCL),
Realize the synchronous data transmission of duplex.I2C interface line is few, and control mode is simple, in master-slave communication, can there is multiple I2C
Bus device is connected in I2C bus simultaneously, identifies communication object by address.But transmission rate is limited, is not suitable for transmission
Mass data.
During existing bus communication, need respectively using the input/output interface of different processors to be separately connected
I2C is from equipment and SPI from equipment, and the input/output interface for resulting in the need for configuration is excessive, and the structure of electronic equipment is complex.
Summary of the invention
In view of the foregoing, it is necessary to provide that a kind of SPI is from equipment and I2C shares the method for GPIO from equipment and electronics is set
It is standby, input/output interface can be shared to connect SPI from equipment and I2C and connect from equipment to reduce the input and output needed to configure
Mouthful.
A kind of method that SPI shares GPIO from equipment from equipment and I2C, comprising the following steps:
Bus determines step: according to reading and writing data request judge need mode bus to be used for I2C mode bus or
Spi bus mode；
I2C communication steps: the mode bus used if necessary is I2C mode bus, then by first interface to described
I2C transmits number from equipment by second interface and the I2C from equipment tranmitting data register signal, and the cooperation clock signal
According to；
SPI communication step: the mode bus used if necessary be spi bus mode, then by the first interface to
The SPI from equipment tranmitting data register signal, and the cooperation clock signal by the second interface to the SPI from equipment
Data are written, and/or data are read from the SPI from equipment by third interface.
Preferably, the SPI communication step further include:
Mode bus if necessary to use is spi bus mode, further includes being sent out by the 4th interface to the SPI equipment
Enable signal is sent to control the SPI equipment and enter working condition.
Preferably, before the I2C communication steps and SPI communication step, further includes: bus state judgment step, packet
It includes:
Determine that bus flag bit is first state or the second state；
If the bus flag bit is first state, be delayed waiting；
If the bus flag bit is the second state, it is first state that total line index, which is arranged, and,
The I2C transmitting step further include: with the I2C after equipment transmission data, the bus flag bit is set
For first state；
The SPI transmitting step further include: with the SPI after equipment reading data and write-in data, described in setting
Bus flag bit is first state.
Preferably, the I2C communication steps further include:
If bus ID is SPI mark, the bus ID is set for I2C mark, and be arranged described first and connect
Mouth and second interface are output mode and export low level, and the first interface is then arranged and second interface is input pattern
Afterwards, clock signal is transmitted by the first interface and data is transmitted by the second interface；
The SPI communication step further include:
If bus ID is I2C mark, the bus ID is set for SPI mark, and be arranged described first and connect
Mouth and second interface are output mode, then by the first interface tranmitting data register signal, and pass through the second interface
Data are written to the SPI from equipment and/or data are read from the SPI from equipment by third interface.
Preferably, the clock signal in the I2C communication steps or the SPI communication step is set according to clock frequency
Frequency transmits the read or write speed of data to be arranged.
Preferably, before the judgment step, further includes:
Initialization step: being arranged the first interface and second interface is output mode, and it is defeated that the third interface, which is arranged,
Enter mode and the 4th interface is output mode.
A kind of SPI shares the circuit of GPIO from equipment and I2C from equipment, comprising:
Processor, including first interface, second interface and third interface；
For I2C from equipment, the I2C connects the first interface from the clock interface of equipment, data-interface connection described the
Two interfaces, when needing mode bus to be used is I2C mode, when being sent by the first interface to the I2C from equipment
Clock signal, and the cooperation clock signal by the second interface and the I2C from equipment transmission data；
SPI connects the first interface from the clock interface of equipment from equipment, the SPI, and Data Input Interface connects institute
It states second interface and data output interface connects the third interface；The mode bus to be used is being needed to be SPI mode
When, then by the first interface to the SPI from equipment tranmitting data register signal, and the cooperation clock signal is described in
Second interface is written data to the SPI from equipment and/or reads data from the SPI from equipment by third interface.
Preferably, the processor further includes the 4th interface,
4th interface connects enable end of the SPI from equipment, and the mode bus to be used is being needed to be SPI mould
When formula, enable signal is sent to the SPI equipment by the 4th interface and enters working condition to control the SPI equipment.
Preferably, the SPI is flash memory from equipment, and the I2C is read-write memory from equipment, and the first interface passes through
First pull-up resistor connects power supply and the second interface and connects the power supply by the second pull-up resistor.
A kind of electronic equipment, including above-mentioned circuit.
Compared to the prior art, above-mentioned SPI is from equipment and I2C shares the method for GPIO from equipment and electronic equipment passes through
Reading and writing data request, which determines, needs mode bus to be used, shares first interface and second from equipment and I2C from equipment using SPI
Interface realizes the switching and mutual exclusion of I2C bus and spi bus mode to save the quantity of input/output interface, have input it is defeated
The advantages of outgoing interface line is few, and control mode simplifies, and device packing forms are small, and traffic rate improves.
Detailed description of the invention
Technical solution in order to illustrate the embodiments of the present invention more clearly, below will be to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the structural schematic diagram for the circuit that SPI shares GPIO from equipment and I2C from equipment.
Fig. 2 is that SPI from equipment and I2C from equipment shares the flow chart of the method for GPIO in one embodiment.
Fig. 3 is that SPI from equipment and I2C from equipment shares the flow chart of the method for GPIO in another embodiment.
Main element symbol description
The present invention that the following detailed description will be further explained with reference to the above drawings.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention will be described in detail.It should be noted that in the absence of conflict, presently filed embodiment and reality
The feature applied in mode can be combined with each other.Many details are explained in the following description in order to fully understand this hair
Bright, described embodiment is only some embodiments of the invention, rather than whole embodiments.Based on the present invention
In embodiment, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Mode shall fall within the protection scope of the present invention.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.
In the various embodiments of the invention, it is not intended to limit the present invention for ease of description, present patent application specification
And term used in claims " connection " is not limited to physics or mechanical connection, but may include electricity
Property connection, it is either direct or indirectly.
Fig. 1 is the structural schematic diagram for the circuit that SPI shares GPIO from equipment 30 and I2C from equipment 20.As shown in Figure 1, should
Circuit includes processor 10, I2C from equipment 20 and SPI from equipment 30.
Processor 10 is including but not limited to central processing unit (Central Processing Unit, CPU), microcontroller list
First (Micro Controller Unit, MCU), single-chip microcontroller etc. are instructed for interpretive machine and are handled in computer software
Data device.Processor 10 have multiple universal input/output interfaces (General Purpose Input Output,
GPIO).Input/output interface is also known as bus extender, simplifies I/O mouthfuls using industrial standard I2C, SMBus or SPI interface
Extension, each GPIO port can be each configured to input or be exported by software.In one or more embodiments, processor
10 include first interface 11, second interface 12, third interface 13 and the 4th interface 14, which is
The GPIO interface of processor 10 is configured to input interface or output interface in internal processes operation.
I2C can be by I2C bus and 10 interaction data of processor from equipment 20, i.e., processor 10 can be to I2C from setting
Standby 20 write-in data can also read data from I2C from equipment 20.In present embodiment, which can be read-write from equipment 20
Memory (EEPROM) passes through the electronic equipment that communicates with processor 10 of I2C bus but it is also possible to be other, the application to this not
It is restricted.There are two communication interfaces: serial data interface 21 (SDA) and serial clock interface 22 (SCL) from the tool of equipment 20 by I2C.
Serial data interface 21 is the bidirectional interface of I2C data-signal, is used for transmission or receives all I2C bus datas.When serial
Clock interface 22 (SCL) is used to receive the clock signal of the I2C from processor 10.In one or more embodiments, serially
Clock interface 22 connects the first interface 11 of processor 10, and serial data interface 21 connects the second interface 12 of processor 10, and
And serial clock interface 22 and serial data interface 21 are connected serially to power supply by pull-up resistor.
SPI can be by spi bus and 10 interaction data of processor from equipment 30, i.e., processor 10 can be to SPI from setting
Standby 30 write-in data can also read data from SPI from equipment 30.In one or more embodiments, which can from equipment 30
To be that flash memory (flash) passes through the electronic equipment that I2C bus is communicated with processor 10 but it is also possible to be other, the application is to this
With no restriction.There are four communication interfaces from the tool of equipment 30 by SPI: serial data clock interface 31 (SCLK), serial date transfer connect
32 (SDI) of mouth, serial data output interface 33 (SDO), enabled interface 34 (CS).
In some embodiments, the first interface 11 of serial data clock interface 31 (SCLK) connection processor 10, is used
In the clock signal for receiving the generation of processor 10.The second interface 12 of serial date transfer interface 32 (SDI) and processor 10 connects
It connects, the data of the output for receiving processor 10.The third interface 13 of serial data output interface 33 (SDO) and processor 10
Connection is used for 10 output data of processor.Enabled interface 34 (CS) is connect with the 4th interface 14 of processor 10, for receiving
Determine whether the control signal chosen by processor 10, that is to say, that only enabled interface 34 (CS) receives prespecified make
Can signal when (high potential or low potential) make SPI enter working condition from equipment 30, processor 10 is to this SPI from equipment 30
Operation is just effective, this just makes it possible to connect multiple SPI in same bus from equipment 30.
In addition, having SPI involved in above embodiment from 30 He of equipment present invention also provides a kind of electronic equipment
I2C shares the circuit of GPIO from equipment 20.
SPI described in detail below shares the embodiment of the method for GPIO from equipment 30 and I2C from equipment 20.
Fig. 2 is that SPI from equipment 30 and I2C from equipment 20 shares the flow chart of the method for GPIO in one embodiment.Such as
Shown in Fig. 2, SPI from equipment 30 and I2C from the method that equipment 20 shares GPIO include step S201~S203.
Step S201 (bus determines step): judge to need mode bus to be used total for I2C according to reading and writing data request
Ray mode or spi bus mode；
Step S202 (I2C communication steps): the mode bus used if necessary is I2C mode bus, then passes through first
Interface 11 to the I2C from 20 tranmitting data register signal of equipment, and the cooperation clock signal by the second interface 12 and
The I2C transmits data from equipment 20；
Step S203 (SPI communication step): the mode bus used if necessary is spi bus mode, then by described
First interface 11 passes through the second interface to the SPI from 30 tranmitting data register signal of equipment, and the cooperation clock signal
12 are written data to the SPI from equipment 30, and/or read data from the SPI from equipment 30 by third interface 13.
Above-mentioned SPI shares the method for GPIO from equipment 20 from equipment 30 and I2C and electronic equipment is asked by reading and writing data
Asking determining needs mode bus to be used, shares first interface 11 and second interface from equipment 30 and I2C from equipment 20 using SPI
12, to save the quantity of input/output interface, realize the switching and mutual exclusion of I2C bus and spi bus mode, have use it is defeated
It is few to enter output interface, control mode simplify, device packing forms are small, traffic rate improve the advantages of.
Fig. 3 is that SPI from equipment 30 and I2C from equipment 20 shares the flow chart of the method for GPIO in another embodiment.
As shown in figure 3, the SPI from equipment 30 and I2C from the method that equipment 20 shares GPIO include step
Step S301 (initialization step): being arranged the first interface 11 and second interface 12 is output mode, and institute is arranged
State that third interface 13 is input pattern and the 4th interface 14 is output mode.In this step, further including may include that setting is total
Linear state is identified as the second state (i.e. idle state), sets I2C mode for bus ID, first interface 11 and second are connect
Mouth 12 is set as input pattern, sets high level output for the 4th interface 14.
Step S302: clock frequency of the setting first interface 11 under I2C mode bus and spi bus mode.This step
In, can be configured by configuring delay function first interface 11 output clock signal frequency, thus it is adjustable or
Change the speed that data are read and write under I2C mode bus and spi bus mode, specifically can according to the resource of processor 10 (such as
The factors such as computing capability, memory) come be arranged first interface 11 output clock signal frequency.
Step S303:(bus determines step): judge to need mode bus to be used total for I2C according to reading and writing data request
Ray mode or spi bus mode, if it is determined that be I2C mode bus, then enter step S310 (I2C communication steps), otherwise
Enter step S320 (SPI communication step).
Step S310 (bus state judgment step): judge that bus state mark is first state or the second state.This
In embodiment, first state is busy state (busy), and the second state is idle state (idle).If it is determined that bus state
Mark is first state, then enters step S311 delay and wait, return to step S310 after waiting time satisfaction.If it is determined that
Bus state mark is the second state, then enters step S312.
Step S312: it is first state (busy) that total line index, which is arranged, to prevent from being interrupted this by other data transfer requests
Secondary data transmission.
Step S313: the bus ID of last time data transmission setting is judged for I2C or SPI, if the bus ID is
SPI then enters step S314；If the bus ID is I2C, S316 is entered step.
Step S314: it is I2C that total line index, which is arranged, and configuring first interface 11 and second interface 12 is output mode, first
Interface 11 and second interface 12 export low level.
Step S315: configuring first interface 11 and second interface 12 is input pattern, sends the stop signal of I2C to I2C
From equipment 20.
Step S316: by first interface 11 to the I2C from 20 tranmitting data register signal of equipment, and cooperate the clock
Signal transmits data from equipment 20 by the second interface 12 and I2C.
Step S317: after output is transmitted, it is the second state (idle) that total line index, which is arranged,.
Above-mentioned step S310~S317 is the communication steps needed using under I2C mode bus, and being described below in detail needs
To use the communication steps under spi bus mode.
Step S320:(bus state judgment step): judge that bus state mark is first state or the second state.This
In embodiment, first state is busy state (busy), and the second state is idle state (idle).If it is determined that bus state
Mark is first state, then enters step S321 delay and wait, return to step S320 after waiting time satisfaction.If it is determined that
Bus state mark is the second state, then enters step S322.
Step S322: it is first state (busy) that total line index, which is arranged, to prevent from being interrupted this by other data transfer requests
Secondary data transmission.
Step S323: the bus ID of last time data transmission setting is judged for I2C or SPI, if the bus ID is
I2C then enters step S324；If bus ID is SPI, S327 is entered step.
Step S324: it is SPI that total line index, which is arranged, and configuring first interface 11 and second interface 12 is output mode, first
Interface 11 and second interface 12 export low level.
Step S325: configuring first interface 11 and second interface 12 is output mode.
Step S326: high level or low level are exported from the mode setting first interface 11 of equipment 30 according to SPI.Specifically
For, it can be configured according to SPI from the mode on the databook of equipment 30.In some embodiments, if SPI from
The mode flags (mode) of equipment 30 are 0, then first interface 11 is arranged and exports low level, if mode flags (mode) are 3,
First interface 11 is set and exports high level.
Step S327: the 4th interface 14 of setting exports low level, so that the SPI is selected from equipment 30, can be read
Write operation carries out data transmission with SPI from equipment 30.
Step S328: after output is transmitted, it is the second state (idle) that total line index, which is arranged,.
Above-mentioned SPI shares the method for GPIO from equipment 20 from equipment 30 and I2C and electronic equipment is asked by reading and writing data
Ask and determine and need mode bus to be used, realize GPIO to I2C from equipment 20 and SPI from the timesharing read-write operation of equipment 30, and
It is independent of each other, shares first interface 11 and second interface 12 from equipment 30 and I2C from equipment 20 using SPI to save input and output
The quantity of interface realizes the switching and mutual exclusion of I2C mode bus and spi bus mode, solves the GPIO mouth of processor 10 not
Enough problems have the input/output interface used few, and control mode simplifies, and device packing forms are small, and traffic rate improves
The advantages of.
In several specific embodiments provided by the present invention, it should be understood that disclosed system and method, it can be with
It realizes by another way.It is obvious to a person skilled in the art that the present invention is not limited to the above exemplary embodiments
Details, and without departing from the spirit or essential characteristics of the present invention, this hair can be realized in other specific forms
It is bright.Therefore, of the invention in all respects, the present embodiments are to be considered as illustrative and not restrictive
Range is indicated by the appended claims rather than the foregoing description, it is intended that by fall in the equivalent requirements of the claims meaning and
All changes in range are included in the present invention.It should not treat any reference in the claims as involved in limitation
Claim.Furthermore, it is to be understood that one word of " comprising " does not exclude other units or steps, odd number is not excluded for plural number.System claims
The multiple units or device of middle statement can also be implemented through software or hardware by the same unit or device.The first, the
Second-class word is used to indicate names, and is not indicated any particular order.
Embodiment of above is only used to illustrate the technical scheme of the present invention and not to limit it, although referring to the above preferable embodiment party
Formula describes the invention in detail, those skilled in the art should understand that, it can be to technical solution of the present invention
It modifies or equivalent replacement should not all be detached from the spirit and scope of technical solution of the present invention.
Claims (10)
1. a kind of method that SPI shares GPIO from equipment from equipment and I2C, which comprises the following steps:
Bus determines step: judging to need mode bus to be used total for I2C mode bus or SPI according to reading and writing data request
Ray mode；
I2C communication steps: the mode bus used if necessary be I2C mode bus, then by first interface to the I2C from
Equipment tranmitting data register signal, and the cooperation clock signal pass through second interface and the I2C from equipment transmission data；
SPI communication step: the mode bus used if necessary is spi bus mode, then by the first interface to described
SPI is written by the second interface to the SPI from equipment from equipment tranmitting data register signal, and the cooperation clock signal
Data, and/or data are read from the SPI from equipment by third interface.
2. the method that SPI as described in claim 1 shares GPIO from equipment from equipment and I2C, which is characterized in that the SPI
Communication steps further include:
Mode bus if necessary to use is spi bus mode, further includes being made by the 4th interface to SPI equipment transmission
Energy signal enters working condition to control the SPI equipment.
3. the method that SPI as described in claim 1 shares GPIO from equipment from equipment and I2C, which is characterized in that described
Before I2C communication steps and SPI communication step, further includes: bus state judgment step, comprising:
Determine that bus flag bit is first state or the second state；
If the bus flag bit is first state, be delayed waiting；
If the bus flag bit is the second state, it is first state that total line index, which is arranged, and,
The I2C transmitting step further include: with the I2C after equipment transmission data, it is that the bus flag bit, which is arranged,
One state；
The SPI transmitting step further include: with the SPI after equipment reading data and write-in data, the bus is set
Flag bit is first state.
4. the method that SPI as described in claim 1 shares GPIO from equipment from equipment and I2C, which is characterized in that the I2C
Communication steps further include:
If bus ID be SPI mark, be arranged the bus ID be I2C identify, and be arranged the first interface with
Second interface is output mode and to export low level, the first interface is then arranged and after second interface is input pattern,
Clock signal is transmitted by the first interface and data are transmitted by the second interface；
The SPI communication step further include:
If bus ID be I2C mark, be arranged the bus ID be SPI identify, and be arranged the first interface with
Second interface is output mode, then by the first interface tranmitting data register signal, and by the second interface to institute
SPI is stated data are written from equipment and/or read data from the SPI from equipment by third interface.
5. the method that SPI as described in claim 1 shares GPIO from equipment from equipment and I2C, which is characterized in that according to clock
The frequency of I2C communication steps described in set of frequency or the clock signal in the SPI communication step transmits the reading of data to be arranged
Writing rate.
6. the method that SPI as claimed in claim 2 shares GPIO from equipment from equipment and I2C, which is characterized in that sentence described
Before disconnected step, further includes:
Initialization step: being arranged the first interface and second interface is output mode, and the third interface is arranged as input mould
Formula and the 4th interface are output mode.
7. the circuit that a kind of SPI shares GPIO from equipment and I2C from equipment characterized by comprising
Processor, including first interface, second interface and third interface；
I2C connects the first interface from the clock interface of equipment from equipment, the I2C, and data-interface connection described second connects
Mouthful, when needing mode bus to be used is I2C mode, believed by the first interface to the I2C from equipment tranmitting data register
Number, and the cooperation clock signal by the second interface and the I2C from equipment transmission data；
For SPI from equipment, the SPI connects the first interface from the clock interface of equipment, Data Input Interface connection described the
Two interfaces and data output interface connect the third interface；When needing the mode bus to be used is SPI mode,
Then by the first interface to the SPI from equipment tranmitting data register signal, and the cooperation clock signal passes through described the
Two interfaces are written data to the SPI from equipment and/or read data from the SPI from equipment by third interface.
8. the circuit that SPI as claimed in claim 7 shares GPIO from equipment and I2C from equipment, which is characterized in that the processing
Device further includes the 4th interface,
4th interface connects enable end of the SPI from equipment, and the mode bus to be used is being needed to be SPI mode
When, enable signal is sent to the SPI equipment by the 4th interface and enters working condition to control the SPI equipment.
9. the circuit that SPI as claimed in claim 7 shares GPIO from equipment and I2C from equipment, which is characterized in that the SPI
It is flash memory from equipment, the I2C is read-write memory from equipment, and the first interface connects power supply by the first pull-up resistor,
And the second interface connects the power supply by the second pull-up resistor.
10. a kind of electronic equipment, which is characterized in that including the described in any item circuits of claim 7-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910005189.6A CN109783416A (en) | 2019-01-03 | 2019-01-03 | SPI shares method, circuit and the electronic equipment of GPIO from equipment and I2C from equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910005189.6A CN109783416A (en) | 2019-01-03 | 2019-01-03 | SPI shares method, circuit and the electronic equipment of GPIO from equipment and I2C from equipment |
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| CN109783416A true CN109783416A (en) | 2019-05-21 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110928813A (en) * | 2019-11-18 | 2020-03-27 | 珠海运控电机有限公司 | System and method for outputting low-frequency synchronous signal based on double SPI |
| CN112069103A (en) * | 2020-09-07 | 2020-12-11 | 歌尔科技有限公司 | Method and system for communication between multiple modules and host |
| CN112817895A (en) * | 2021-01-28 | 2021-05-18 | 广州安凯微电子股份有限公司 | Communication method based on GPIO |
| CN114415935A (en) * | 2021-12-02 | 2022-04-29 | 深圳市乐升半导体有限公司 | Data transmission chip, method and electronic equipment |
| CN115033520A (en) * | 2022-07-11 | 2022-09-09 | 深圳市金科泰通信设备有限公司 | IIC data transmission method and device, single chip microcomputer equipment and storage medium |
| CN115098428A (en) * | 2022-07-11 | 2022-09-23 | 深圳市金科泰通信设备有限公司 | SPI data transmission method and device, electronic equipment and storage medium |
| WO2023208161A1 (en) * | 2022-04-28 | 2023-11-02 | 苏州元脑智能科技有限公司 | Communication link switching control circuit, communication link and server |
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| CN110928813A (en) * | 2019-11-18 | 2020-03-27 | 珠海运控电机有限公司 | System and method for outputting low-frequency synchronous signal based on double SPI |
| CN110928813B (en) * | 2019-11-18 | 2021-04-30 | 珠海运控电机有限公司 | System and method for outputting low-frequency synchronous signal based on double SPI |
| CN112069103A (en) * | 2020-09-07 | 2020-12-11 | 歌尔科技有限公司 | Method and system for communication between multiple modules and host |
| CN112817895A (en) * | 2021-01-28 | 2021-05-18 | 广州安凯微电子股份有限公司 | Communication method based on GPIO |
| CN114415935A (en) * | 2021-12-02 | 2022-04-29 | 深圳市乐升半导体有限公司 | Data transmission chip, method and electronic equipment |
| CN114415935B (en) * | 2021-12-02 | 2024-03-12 | 深圳市乐升半导体有限公司 | Data transmission chip, method and electronic equipment |
| WO2023208161A1 (en) * | 2022-04-28 | 2023-11-02 | 苏州元脑智能科技有限公司 | Communication link switching control circuit, communication link and server |
| CN115033520A (en) * | 2022-07-11 | 2022-09-09 | 深圳市金科泰通信设备有限公司 | IIC data transmission method and device, single chip microcomputer equipment and storage medium |
| CN115098428A (en) * | 2022-07-11 | 2022-09-23 | 深圳市金科泰通信设备有限公司 | SPI data transmission method and device, electronic equipment and storage medium |
| CN115033520B (en) * | 2022-07-11 | 2023-08-08 | 深圳市金科泰通信设备有限公司 | IIC data transmission method and device, singlechip equipment and storage medium |
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Application publication date: 20190521 |