CN115033520A - IIC data transmission method and device, single chip microcomputer equipment and storage medium - Google Patents
IIC data transmission method and device, single chip microcomputer equipment and storage medium Download PDFInfo
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- CN115033520A CN115033520A CN202210808332.7A CN202210808332A CN115033520A CN 115033520 A CN115033520 A CN 115033520A CN 202210808332 A CN202210808332 A CN 202210808332A CN 115033520 A CN115033520 A CN 115033520A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to an IIC data transmission method and device, single-chip microcomputer equipment and a storage medium. The IIC data transmission method comprises the following steps: closing the data transmission register according to the received data transmission instruction; determining corresponding basic parameters of the IIC transmission mode according to the IIC transmission mode selection instruction in the data transmission instruction; the basic parameters corresponding to the IIC transmission mode comprise a read-write command, state parameters, a speed mode and high and low level parameters; the state parameters include the disabled states and addresses of the master device and the slave device; setting a control register parameter corresponding to the IIC transmission mode based on the basic parameter corresponding to the IIC transmission mode to select two GPIO ports to form an IIC serial port and enter the IIC transmission mode; and starting a data transmission register, and carrying out IIC data transmission on the data to be transmitted based on the control register parameters.
Description
Technical Field
The present application relates to the field of data transmission technologies, and in particular, to an IIC data transmission method and apparatus, a single chip microcomputer device, and a storage medium.
Background
With the development of science and technology, in order to make the functions that the singlechip can realize more various, people have proposed the multiplexing technology to singlechip pin. The multiplexing method of the singlechip interface in the market at present mostly uses a limited GPIO interface to be multiplexed into an SPI interface or an IIC interface, and the multiplexing method improves the utilization rate of the singlechip interface to a certain extent. However, the number of interfaces of the single chip microcomputer is fixed, and the multiplexing method has a limited effect on improving the functional diversity of the single chip microcomputer.
Therefore, in order to meet market demands, the multiplexing method of the single chip microcomputer interface gradually develops towards more flexible multiplexing direction, namely a limited GPIO (general purpose input/output) port is used, and the multiplexing can be selected as an SPI (serial peripheral interface) or an IIC (inter-integrated circuit) interface. Although the flexible multiplexing method can enable the single chip microcomputer to realize more functions, the multiplexed data transmission method is also more complicated, and therefore the data transmission efficiency is reduced.
Disclosure of Invention
The application provides an IIC data transmission method, an IIC data transmission device, a single chip microcomputer device and a storage medium, and aims to provide a simpler and more reliable IIC data transmission method and improve data transmission efficiency.
In a first aspect, the present application provides an IIC data transmission method, which is applied to a single chip microcomputer device, where the single chip microcomputer device supports an SPI transmission mode, an IIC transmission mode, and a GPIO transmission mode to be switched, and the method includes:
closing the data transmission register according to the received data transmission instruction;
determining corresponding basic parameters of the IIC transmission mode according to the IIC transmission mode selection instruction in the data transmission instruction; the basic parameters corresponding to the IIC transmission mode comprise a read-write command, state parameters, a speed mode and high and low level parameters; the state parameters include the disabled states and addresses of the master device and the slave device;
setting a control register parameter corresponding to the IIC transmission mode based on the basic parameter corresponding to the IIC transmission mode to select two GPIO ports to form an IIC serial port and enter the IIC transmission mode;
and starting a data transmission register, and carrying out IIC data transmission on the data to be transmitted based on the control register parameters.
By applying the method, the IIC transmission mode can be selectively entered through the selection instruction in the data transmission instruction, the basic parameters corresponding to the IIC transmission mode are determined, so that two GPIO ports can be selected to form an IIC serial port by setting the control registers corresponding to the basic parameters, the data to be transmitted can be transmitted in the IIC transmission mode, and the transmission efficiency is improved.
Optionally, when the read-write command is a write command, the starting of the data transmission register and the IIC data transmission of the data to be transmitted based on the parameter of the control register include:
writing a first sending instruction and the data to be transmitted into a data register;
and transmitting the data to be transmitted to a data transmission object by utilizing an FIFO memory according to the first sending instruction.
When the read-write command is a write command, the FIFO memory may be used to transmit the data to be transmitted in the data register to the data transmission object according to the first sending instruction. By additionally arranging the FIFO memory as a data cache region, the waste of CPU resources can be avoided.
Optionally, when the read-write command is a read command, the starting of the data transmission register and the IIC data transmission of the data to be transmitted based on the parameter of the control register include:
writing a second send instruction into the data register;
and reading data from the data transfer object by using a FIFO memory according to the second sending instruction.
When the read-write command is a read command, the data in the data transmission object can be cached in the FIFO memory by additionally arranging the FIFO memory as a data cache region, so that the waste of CPU resources is avoided.
Optionally, the basic parameters corresponding to the IIC transmission mode further include: a full interrupt threshold;
the method further comprises the following steps:
setting a full interrupt trigger condition based on a full interrupt threshold of the FIFO memory;
triggering one-time full interrupt when the data volume in the FIFO memory meets the full interrupt triggering condition;
the reading data from the data transfer object by using the FIFO memory according to the second sending instruction includes:
and according to the second sending instruction, when the full interrupt is triggered by the data amount in the FIFO memory, responding to the full interrupt, and reading data from the data transmission object.
By setting full interrupt and enabling full interrupt trigger conditions, the main device can actively request the CPU to transmit data in the FIFO memory once, so that CPU resources can be saved.
Optionally, the basic parameters corresponding to the IIC transmission mode further include: an air break threshold for the FIFO memory;
the method further comprises the following steps:
setting a null interrupt trigger condition based on a null interrupt threshold of the FIFO memory;
triggering one-time idle interruption when the data volume in the FIFO memory meets the idle interruption triggering condition;
the starting of the data transmission register, based on the control register parameter, carries out IIC data transmission on data to be transmitted, and comprises the following steps:
and starting a data transmission register, responding to the idle interruption based on the control register parameter, and performing IIC data transmission on the data to be transmitted.
By setting the null interrupt and enabling the null interrupt trigger condition, the CPU can determine whether the FIFO memory is empty in response to the null interrupt, thereby learning whether the data has been transferred.
Optionally, the method further includes:
inquiring whether the transmission of the sending command is finished or not based on the basic parameters of the IIC transmission mode; the sending instruction comprises the first sending instruction and the second sending instruction;
if the sending instructions are transmitted completely, continuously inquiring whether the main device is idle;
and if the master device is in an idle state, closing the data transmission register and finishing data transmission.
By judging whether the sending instructions are sent completely and inquiring whether the main device is in an idle state, the data to be transmitted can be ensured to be transmitted completely, data loss is avoided, and if the main device is in the idle state, the data transmission is completed, and the transmission can be finished.
Optionally, the starting of the data transmission register and the IIC data transmission of the data to be transmitted based on the parameter of the control register include:
and when the data transmission register is started, emptying all data and instructions in the data register, and carrying out IIC data transmission on the data to be transmitted based on the control register parameters.
When the data transmission register is started, all data and instructions in the data register are emptied, so that the influence of the left sending instruction and the data to be transmitted in the last data register on the data transmission can be avoided, and the data error received by a slave device is avoided.
The IIC transmission mode can be selectively entered through a selection instruction in the data transmission instruction, the basic parameters corresponding to the IIC transmission mode are determined, and therefore two GPIO ports can be selected to form an IIC serial port by setting the control registers corresponding to the basic parameters, data to be transmitted can be transmitted in the IIC transmission mode, and transmission efficiency is improved.
In a second aspect, the present application provides an IIC data transmission device, which is applied to a single chip microcomputer device, wherein the single chip microcomputer device supports an SPI transmission mode, an IIC transmission mode, and a GPIO transmission mode to be switched, and the device includes:
the transmission instruction receiving module is used for closing the data transmission register according to the received data transmission instruction;
the basic parameter determining module is used for determining corresponding basic parameters of the IIC transmission mode according to the IIC transmission mode selection instruction in the data transmission instruction; the basic parameters corresponding to the IIC transmission mode comprise a read-write command, state parameters, a speed mode and high and low level parameters; the state parameters include the disabled states and addresses of the master device and the slave device;
the register parameter setting module is used for setting control register parameters corresponding to the IIC transmission mode based on basic parameters corresponding to the IIC transmission mode so as to select two GPIO ports to form an IIC serial port and enter the IIC transmission mode;
and the data transmission module is used for starting the data transmission register and carrying out IIC data transmission on the data to be transmitted based on the control register parameter.
Optionally, when the read-write command is a write command, the data transmission module is specifically configured to:
writing a first sending instruction and the data to be transmitted into a data register;
and transmitting the data to be transmitted to a data transmission object by utilizing an FIFO memory according to the first sending instruction.
Optionally, when the read-write command is a read command, the data transmission module is specifically configured to:
writing a second send instruction into the data register;
and reading data from the data transmission object by using a FIFO memory according to the second sending instruction.
Optionally, the basic parameters corresponding to the IIC transmission mode further include: a full interrupt threshold;
the device further comprises: a full interrupt determination module to:
setting a full interrupt trigger condition based on a full interrupt threshold of the FIFO memory;
triggering full interruption once when the data amount in the FIFO memory meets the full interruption triggering condition;
when the data transmission module reads data from the data transmission object by using the FIFO memory according to the second sending instruction, the data transmission module is specifically configured to:
and according to the second sending instruction, when the full interrupt is triggered by the data amount in the FIFO memory, responding to the full interrupt, and reading data from the data transmission object.
Optionally, the basic parameters corresponding to the IIC transmission mode further include: an air break threshold for the FIFO memory;
the device further comprises: an idle interrupt determination module to:
setting an idle interrupt trigger condition based on an idle interrupt threshold of the FIFO memory;
triggering one-time idle interruption when the data volume in the FIFO memory meets the idle interruption triggering condition;
when the data transmission module starts the data transmission register and performs IIC data transmission on data to be transmitted based on the control register parameter, the data transmission module is specifically configured to:
and starting a data transmission register, responding to the idle interruption based on the control register parameter, and performing IIC data transmission on the data to be transmitted.
Optionally, the apparatus further comprises: an instruction query module to:
inquiring whether the transmission of the sending instruction is finished or not based on the basic parameters of the IIC transmission mode; the sending instruction comprises the first sending instruction and the second sending instruction;
if the sending instructions are transmitted completely, continuously inquiring whether the main device is idle;
and if the master device is in an idle state, closing the data transmission register and finishing data transmission.
Optionally, the data transmission module is specifically configured to:
and when the data transmission register is started, emptying all data and instructions in the data register, and carrying out IIC data transmission on the data to be transmitted based on the control register parameters.
In a third aspect, the present application provides a single chip microcomputer device, including: four GPIO ports, a memory and a processor;
the four GPIO ports are used for carrying out GPIO communication, or selecting any three multiplexing as SPI ports from the GPIO ports to carry out SPI communication, or selecting any two multiplexing as IIC ports from the GPIO ports to carry out IIC communication;
the memory has stored thereon a computer program that can be loaded by the processor and that executes the method according to any of the first aspects.
In a fourth aspect, the present application provides a computer readable storage medium storing a computer program capable of being loaded by a processor and performing the method according to any of the first aspects.
By the method, the IIC transmission mode can be selectively entered through the selection instruction in the data transmission instruction, the basic parameters corresponding to the IIC transmission mode are determined, so that two GPIO ports can be selected to form an IIC serial port by setting the control registers corresponding to the basic parameters, data to be transmitted can be transmitted in the IIC transmission mode, and transmission efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic view of an application scenario provided in an embodiment of the present application;
fig. 2 is a flowchart of an IIC data transmission method according to an embodiment of the present application;
fig. 3 is a flowchart of another IIC data transmission method according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an IIC data transmission device according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a single chip microcomputer device provided in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship, unless otherwise specified.
The embodiments of the present application will be described in further detail with reference to the drawings attached hereto.
Fig. 1 is a schematic view of an application scenario provided in the present application, in which data to be transmitted needs to be transmitted between a master device and a slave device. Because the singlechip equipment volume of using this application is limited, and the quantity of singlechip pin is limited, in order to make limited pin can realize more transmission mode in the volume of certain size, the multiplexing technology of singlechip pin develops towards more nimble direction, is striven for to use limited a pin to realize more multiplexing functions. Therefore, the inventor is dedicated to research that the limited common GPIO port can be selected to be multiplexed as an SPI serial port and can also be selected to be multiplexed as an IIC serial port. In this case, it is important to ensure that the transmission process after multiplexing can be performed normally.
When a common GPIO port on a singlechip is multiplexed as an IIC serial port, in order to ensure that the transmission process can be normally carried out and the transmission process is simpler and more convenient, the method of the application ensures that the data to be transmitted can be transmitted between the master device and the slave device. Specifically, the IIC data transmission method can be deployed in a single chip microcomputer, when data to be transmitted exist, the single chip microcomputer executes the method, the IIC data transmission method is used for the data to be transmitted, the transmission process can be carried out normally, the transmission process is simpler and more convenient, and the transmission efficiency is more efficient.
The following embodiments can be referred to for the implementation of the specific processing procedure of the single chip microcomputer.
Fig. 2 is a flowchart of an IIC data transmission method according to an embodiment of the present application. The method of the embodiment is used for improving the transmission efficiency when the IIC interface is used for transmitting data to be transmitted, can be applied to single chip microcomputer equipment, supports SPI transmission mode, IIC transmission mode and GPIO transmission mode switching, and can also be applied to other electronic equipment with four GPIO interfaces and computing capacity. As shown in fig. 2, the method of the present embodiment includes:
s201, closing the data transmission register according to the received data transmission instruction.
The data transmission register is used for controlling whether the single chip microcomputer can transmit data at the moment.
Specifically, after a data transmission instruction is received, the data transmission register is closed, and at the moment, the single chip microcomputer cannot transmit data, so that the parameters of the control register can be conveniently set subsequently.
In some embodiments, the data transfer command may be an input command from a user, and the data transfer register is turned off after the user inputs a request through the input device.
S202, determining corresponding basic parameters of an IIC transmission mode according to an IIC transmission mode selection instruction in the data transmission instruction; the basic parameters corresponding to the IIC transmission mode comprise a read-write command, state parameters, a speed mode and high and low level parameters; the status parameters include the disabled status and addresses of the master and slave devices.
The speed mode refers to that when the data transmission mode is the IIC transmission mode, the data to be transmitted can be transmitted at different speeds, and each transmission speed corresponds to one speed mode. In some embodiments, the speed transmission mode includes a standard mode and a high speed mode. The high-low level parameter refers to an effective value of a high-low level of the clock line when the data transmission mode is the IIC transmission mode.
Specifically, since the present embodiment may be applied to a single chip microcomputer device, the single chip microcomputer device supports switching between an SPI transmission mode, an IIC transmission mode, and a GPIO transmission mode, the data transmission instruction may include any one of three selection instructions (an SPI transmission mode selection instruction, an IIC transmission mode selection instruction, and a GPIO transmission mode selection instruction), and when the selection instruction in the data transmission instruction is the IIC transmission mode selection instruction, the data transmission mode may be determined to be the IIC transmission mode according to the IIC transmission mode selection instruction, so as to determine corresponding basic parameters of the IIC transmission mode.
In some embodiments, the data transmission command may be an input command of a user, and when the user inputs a requirement of the user, the data transmission command is generated, and correspondingly, the selection command may be generated according to a selection of the data transmission mode of the user in the input process. In some implementations, the selection instruction may present three selection instructions, namely an SPI transmission mode selection instruction, an IIC transmission mode selection instruction, and a GPIO transmission mode selection instruction, as three options to a user in a pop-up manner, and is selected by the user, and when the user selects the IIC transmission mode, the IIC transmission mode selection instruction may be generated, thereby determining the corresponding basic parameters of the IIC transmission mode.
In other implementation manners, the data transmission instruction may be generated according to the data to be transmitted, when the single chip microcomputer detects that the data storage area receives the data, the data transmission instruction is generated, and correspondingly, the selection instruction may be generated according to a high level or a low level triggered by the data to be transmitted. For example, when a high level is toggled, an SPI transmission mode selection command may be generated, and when a low level is toggled, an IIC transmission mode selection command may be generated, and thus, when data to be transmitted is toggled to a low level, an IIC transmission mode selection command may be generated, thereby determining a corresponding basic parameter of the IIC transmission mode.
S203, setting control register parameters corresponding to the IIC transmission mode based on the basic parameters corresponding to the IIC transmission mode, so as to select two GPIO ports to form an IIC serial port and enter the IIC transmission mode.
Specifically, the basic parameters corresponding to the IIC transmission mode are determined, and include a read-write command, a state parameter, a speed mode, and a high-low level parameter, and based on these basic parameters, parameters of corresponding control registers may be set, that is, values of the control registers corresponding to these basic parameters are assigned, and through assigning values to the control registers, two GPIO ports may be selected to form an IIC serial port, and it is ensured that data to be transmitted may be transmitted using the IIC transmission mode.
In some specific implementations, the SLAVE device may be turned off by setting the IC _ SLAVE _ DISABLE register; starting a MASTER device by setting an IC _ MASTER _ MOOD register; setting addresses of a MASTER device and a SLAVE device respectively by setting an IC _10 BITDDR _ MASTER register and an IC _0 BITDDR _ SLAVE register; setting high and low level parameters of a clock line by setting an IC _ SS _ HCNT register and an IC _ SS _ LCNT register; the SPEED mode of data transfer is set by setting the IC _ MAX _ SPEED _ MOOD register.
And S204, starting a data transmission register, and carrying out IIC data transmission on the data to be transmitted based on the control register parameters.
Specifically, after the parameters of the control register are determined, the data transmission register can be started, the data transmission function of the single chip microcomputer is recovered, and the data to be transmitted can be subjected to IIC data transmission between the master device and the slave device based on the parameters of the control register.
The IIC transmission mode can be selectively entered through a selection instruction in the data transmission instruction, the basic parameters corresponding to the IIC transmission mode are determined, and therefore two GPIO ports can be selected to form an IIC serial port by setting the control registers corresponding to the basic parameters, data to be transmitted can be transmitted in the IIC transmission mode, and transmission efficiency is improved.
In some embodiments, when the read-write command is a write command, the IIC data transmission process for data to be transmitted includes: writing a first sending instruction and the data to be transmitted into a data register; and transmitting the data to be transmitted to a data transmission object by utilizing an FIFO memory according to the first sending instruction.
The data register refers to a register storing data to be transmitted.
Specifically, when the read-write command is a write command, the data transmission register is opened, so that the single chip microcomputer device of the embodiment can realize a data transmission function, the first sending instruction and the data to be transmitted are written into the data register, and the data to be transmitted are transmitted based on the parameter of the control register according to the first sending instruction. In the transmission process, because the mode that the CPU directly transmits the data in the data memory to the data transmission object is word-by-word extraction and word-by-word transmission, the resource of the CPU is greatly wasted by the mode, therefore, the FIFO memory can be used as a data buffer area in the transmission process, and the data in the buffer area is transmitted to the data transmission object. In some implementations, data to be transmitted may be stored in a FIFO memory and then transmitted to a data transfer object in the form of data frames.
When the read-write command is a write command, the FIFO memory is additionally arranged to serve as a data buffer area of the IIC transmission mode, so that the data buffered in the data buffer area is transmitted to a data transmission object, the data transmission of the CPU word by word can be avoided, and the waste of CPU resources is avoided.
In other embodiments, when the read/write command is a read command, the IIC data transmission process for data to be transmitted includes: writing a second send instruction into the data register; and reading data from the data transmission object by using a FIFO memory according to the second sending instruction.
Specifically, when the read-write command is a read command, the data transmission register is started, a second sending instruction is written into the data register, and the data to be transmitted is transmitted according to the second sending instruction and the parameter of the control register. During transmission, the FIFO memory can be used as a data buffer area, and the data of the data transmission object to be read is buffered in the data buffer area of the FIFO memory, so that the buffered data is read from the data buffer area, and the purpose of saving CPU resources is achieved.
In some embodiments, the basic parameters corresponding to the IIC transmission mode further include: a full interrupt threshold; the data transmission process comprises the following steps: setting a full interrupt trigger condition based on a full interrupt threshold of the FIFO memory; triggering full interruption once when the data amount in the FIFO memory meets the full interruption triggering condition; the reading data from the data transfer object by using the FIFO memory according to the second sending instruction includes: and according to the second sending instruction, when the full interrupt is triggered by the data amount in the FIFO memory, responding to the full interrupt, and reading data from the data transmission object.
Specifically, when a data buffer is provided for the IIC transfer mode using the FIFO memory, a full interrupt threshold of the FIFO memory may be set. And setting a full interrupt trigger condition according to the full interrupt threshold value, and enabling the full interrupt trigger condition by setting a corresponding control register. And according to the second sending instruction, when the data volume in the FIFO memory reaches the triggering condition of full interruption and the full interruption is triggered, responding to the full interruption, and transmitting the data to be transmitted by the CPU, so that the main device can read the data from the data transmission object to finish the data transmission of IIC.
By setting the full interrupt and enabling the full interrupt trigger condition, the main device can actively request the CPU to transmit the data in the FIFO memory once, thereby saving the CPU resource.
In some implementations, the full interrupt threshold of the FIFO memory may be set to 7. According to the second sending instruction, when the data amount in the FIFO memory is more than or equal to 7+1, the full interrupt of the IIC data transmission is triggered, and in response to the full interrupt, the CPU enables the data to be transmitted, so that the main device can read the data from the data transmission object, and one-time IIC data transmission is completed.
In other embodiments, the basic parameters corresponding to the IIC transmission mode further include: an air break threshold for the FIFO memory; the data transmission process comprises the following steps: setting a null interrupt trigger condition based on a null interrupt threshold of the FIFO memory; triggering one-time idle interruption when the data volume in the FIFO memory meets the idle interruption triggering condition; the starting of the data transmission register, based on the control register parameter, carries out IIC data transmission on data to be transmitted, and comprises the following steps: and starting a data transmission register, responding to the idle interruption based on the control register parameter, and performing IIC data transmission on the data to be transmitted.
Specifically, when a data buffer is provided for the IIC transmission mode using the FIFO memory, an air break threshold of the FIFO memory may be set. And setting an idle interrupt trigger condition according to an idle interrupt threshold value, and enabling the idle interrupt trigger condition by setting a corresponding control register. In the IIC data transmission process, when the data volume in the FIFO memory meets the trigger condition of the idle interrupt, the idle interrupt is triggered once, and in response to the idle interrupt, the CPU can process other instructions, so that the CPU resource is saved.
In some specific implementations, the air break threshold of the FIFO memory may be set to 2. When the amount of data in the FIFO memory is less than 2, an air break in the IIC data transfer is triggered, in response to which the CPU may process other instructions, according to a first send instruction.
In some embodiments, to avoid data loss, the sending instruction and the idle state of the master device may be queried, where the querying includes: inquiring whether the transmission of the sending command is finished or not based on the basic parameters of the IIC transmission mode; the sending instruction comprises the first sending instruction and the second sending instruction; if the sending instructions are transmitted completely, continuously inquiring whether the main device is idle; and if the master device is in an idle state, closing the data transmission register and finishing data transmission.
Specifically, if the air break of the FIFO memory is continuously triggered, it is considered that the data to be transmitted is completely transmitted, and at this time, whether the transmission of the sending instruction is completed may be queried based on the basic parameter of the IIC transmission mode. If the sending instruction is transmitted, the data to be transmitted is transmitted. And at the moment, whether the main device is idle or not is continuously inquired, if the main device is in an idle state, the data to be transmitted corresponding to the last sending instruction is transmitted, at the moment, the data transmission register can be closed, and the data transmission is finished.
By judging whether the sending instructions are sent completely and inquiring whether the main device is in an idle state, the data to be transmitted can be ensured to be transmitted completely, data loss is avoided, and if the main device is in the idle state, the data transmission is completed, and the transmission can be finished.
In some embodiments, the transmission process of IIC includes: and when the data transmission register is started, emptying all data and instructions in the data register, and carrying out IIC data transmission on the data to be transmitted based on the control register parameters.
Specifically, when the data transmission register is started, all data and instructions in the data register can be cleared, and the influence of the sending instruction left in the data register and the data to be transmitted on the data transmission is avoided, so that the data error received from the device is avoided. And on the basis, IIC data transmission is carried out on the data to be transmitted based on the control register parameters.
In other embodiments, after the data register is closed, the parameter of the control register may be cleared by setting the parameter of the control register corresponding to the IIC transmission mode, so as to avoid interference of the default configuration parameter or the last configuration parameter on the data transmission, thereby avoiding a data error received from the device. And on the basis, IIC data transmission is carried out on the data to be transmitted based on the set parameters of the control register.
In some scenarios, the single chip microcomputer device using the method of the present embodiment may use the IIC interface to externally connect the temperature detection device under the condition that the GPIO interface is multiplexed as the IIC interface, so that the temperature data detected by the temperature detection device can be read by the master device through the IIC data transmission method of the present embodiment.
In some embodiments, as shown in fig. 3, the data transmission flow using the IIC transmission mode refers to the following steps:
1. write 0 to IC _ ENABLE register, disable DW _ apb _ i2 c;
2. writing an address of an IC _ CON register setting speed mode, 7bits or 10 bits; ensuring that IC _ SLAVE _ DISABLE is 1; MASTER _ MODE is 1;
3. writing the slave address to the IC _ TAR register;
4. writing a high count and a low count to control the I2C clock rate;
5. configuring a fifo threshold (maximum 8);
6. write 1 to the IC _ ENABLE register, ENABLE DW _ apb _ i2 c;
7. then writing DATA and commands to the IC _ DATA _ CMD register, the DATA and commands written before the IC _ ENABLE is turned on will be cleared while the IC _ ENABLE is turned on;
note that: 1. it is recommended to clear the control register before use to avoid interference from default configuration or last configuration.
2 i2c, the first write operation initiated while in the idle state will automatically send the slave address.
3. When data needs to be written, the cmd register is configured to be written, and the data is written in the data register, so that transmission can be started; note that initiating the transfer requires writing the data address of the operation first, and then writing the data. All write data will be stored in fifo, and the empty-full condition of fifo will be checked.
Fig. 4 is a schematic structural diagram of an IIC data transmission device provided in an embodiment of the present application, and as shown in fig. 4, the IIC data transmission device is applied to a single chip microcomputer device, where the single chip microcomputer device supports switching of an SPI transmission mode, an IIC transmission mode, and a GPIO transmission mode, and the data transmission device 400 of the embodiment includes:
a transmission instruction receiving module 401, configured to close the data transmission register according to the received data transmission instruction;
a basic parameter determining module 402, configured to determine a basic parameter corresponding to an IIC transmission mode according to an IIC transmission mode selection instruction in the data transmission instruction; the basic parameters corresponding to the IIC transmission mode comprise a read-write command, state parameters, a speed mode and high and low level parameters; the state parameters include the disabled states and addresses of the master device and the slave device;
a register parameter setting module 403, configured to set a control register parameter corresponding to the IIC transmission mode based on the basic parameter corresponding to the IIC transmission mode, so as to select two GPIO ports to form an IIC serial port, and enter the IIC transmission mode;
and the data transmission module 404 is configured to start a data transmission register, and perform IIC data transmission on data to be transmitted based on the control register parameter.
Optionally, when the read-write command is a write command, the data transmission module 404 is specifically configured to:
writing a first sending instruction and the data to be transmitted into a data register;
and transmitting the data to be transmitted to a data transmission object by utilizing a FIFO memory according to the first sending instruction.
Optionally, when the read-write command is a read command, the data transmission module 404 is specifically configured to:
writing a second send instruction into the data register;
and reading data from the data transmission object by using a FIFO memory according to the second sending instruction.
Optionally, the basic parameters corresponding to the IIC transmission mode further include: a full interrupt threshold;
the method further comprises the following steps: a full interrupt determination module 405, configured to:
setting a full interrupt trigger condition based on a full interrupt threshold of the FIFO memory;
triggering one-time full interrupt when the data volume in the FIFO memory meets the full interrupt triggering condition;
the data transmission module 404 reads data from the data transmission object by using a FIFO memory according to the second sending instruction, and is specifically configured to:
and according to the second sending instruction, when the full interrupt is triggered by the data amount in the FIFO memory, responding to the full interrupt, and reading data from the data transmission object.
Optionally, the basic parameters corresponding to the IIC transmission mode further include: an air break threshold for the FIFO memory;
the method further comprises the following steps: an air break determination module 406, configured to:
setting a null interrupt trigger condition based on a null interrupt threshold of the FIFO memory;
triggering one-time idle interruption when the data volume in the FIFO memory meets the idle interruption triggering condition;
when the data transmission module 405 starts the data transmission register and performs IIC data transmission on the data to be transmitted based on the control register parameter, the data transmission module is specifically configured to:
and starting a data transmission register, responding to the idle interruption based on the control register parameter, and performing IIC data transmission on the data to be transmitted.
Optionally, the method further includes: an instruction query module 407 for
Inquiring whether the transmission of the sending instruction is finished or not based on the basic parameters of the IIC transmission mode; the sending instruction comprises the first sending instruction and the second sending instruction;
if the sending instructions are transmitted completely, continuously inquiring whether the main device is idle;
and if the master device is in an idle state, closing the data transmission register and finishing data transmission.
Optionally, the data transmission module 404 is specifically configured to:
and when the data transmission register is started, emptying all data and instructions in the data register, and carrying out IIC data transmission on the data to be transmitted based on the control register parameters.
The apparatus of this embodiment may be configured to perform the method of any of the above embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.
Fig. 5 is a schematic structural diagram of a single chip microcomputer device provided in an embodiment of the present application, and as shown in fig. 5, the single chip microcomputer device 500 of the present embodiment may include: four GPIO ports 501, memory 502, and processor 503.
The four GPIO ports 501 are used for carrying out GPIO communication, or selecting any three multiplexing interfaces as SPI interfaces from the GPIO ports to carry out SPI communication, or selecting any two multiplexing interfaces as IIC interfaces from the GPIO ports to carry out IIC communication;
the memory 502 has stored thereon a computer program that can be loaded by the processor 503 and executed to perform the method in the above-described embodiments.
The processor 503 is coupled to the memory 502, such as via a bus.
Optionally, the single chip device 500 may further include a transceiver. It should be noted that, in practical applications, the transceiver is not limited to one, and the structure of the single chip microcomputer device 500 does not constitute a limitation to the embodiment of the present application.
The Processor 503 may be a CPU (Central Processing Unit), a general-purpose Processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other Programmable logic device, transistor logic, hardware components, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor 602 may also be a combination of computing functions, e.g., comprising one or more microprocessors, a combination of a DSP and a microprocessor, or the like.
A bus may include a path that transfers information between the above components. The bus may be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The Memory 502 may be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical Disc storage, optical Disc storage (including Compact Disc, laser Disc, optical Disc, digital versatile Disc, blu-ray Disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to these.
The memory 502 is used for storing application program codes for executing the scheme of the application, and the execution is controlled by the processor 503. The processor 503 is configured to execute the application program code stored in the memory 502 to implement the content shown in the foregoing method embodiments.
The electronic device to which the present application is applied includes, but is not limited to: mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., car navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. But also a server, etc. The single chip microcomputer device shown in fig. 5 is only an example, and should not bring any limitation to the function and the application range of the embodiment of the present application.
The single chip microcomputer device of this embodiment may be configured to execute the method of any one of the above embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.
The present application also provides a computer readable storage medium storing a computer program that can be loaded by a processor and executed to perform the method as in the above embodiments.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Claims (10)
1. An IIC data transmission method is applied to single chip microcomputer equipment, the single chip microcomputer equipment supports an SPI transmission mode, an IIC transmission mode and a GPIO transmission mode to be switched, and the method comprises the following steps:
closing the data transmission register according to the received data transmission instruction;
determining corresponding basic parameters of the IIC transmission mode according to the IIC transmission mode selection instruction in the data transmission instruction; the basic parameters corresponding to the IIC transmission mode comprise a read-write command, state parameters, a speed mode and high and low level parameters; the state parameters include the disabled states and addresses of the master device and the slave device;
setting a control register parameter corresponding to the IIC transmission mode based on the basic parameter corresponding to the IIC transmission mode to select two GPIO ports to form an IIC serial port and enter the IIC transmission mode;
and starting a data transmission register, and carrying out IIC data transmission on the data to be transmitted based on the parameters of the control register.
2. The method of claim 1, wherein when the read/write command is a write command, the starting of the data transfer register and the IIC data transfer of the data to be transferred based on the control register parameter comprise:
writing a first sending instruction and the data to be transmitted into a data register;
and transmitting the data to be transmitted to a data transmission object by utilizing an FIFO memory according to the first sending instruction.
3. The method of claim 1, wherein when the read/write command is a read command, the turning on the data transfer register performs IIC data transfer on data to be transferred based on the control register parameter, and the method comprises:
writing a second send instruction into the data register;
and reading data from the data transmission object by using a FIFO memory according to the second sending instruction.
4. The method of claim 3, wherein the basic parameters corresponding to the IIC transmission mode further comprise: a full interrupt threshold;
the method further comprises the following steps:
setting a full interrupt trigger condition based on a full interrupt threshold of the FIFO memory;
triggering one-time full interrupt when the data volume in the FIFO memory meets the full interrupt triggering condition;
the reading data from the data transfer object by using the FIFO memory according to the second sending instruction includes:
and according to the second sending instruction, when the full interrupt is triggered by the data amount in the FIFO memory, responding to the full interrupt, and reading data from the data transmission object.
5. The method according to claim 2 or 3, wherein the basic parameters corresponding to the IIC transmission mode further comprise: an air break threshold for the FIFO memory;
the method further comprises the following steps:
setting a null interrupt trigger condition based on a null interrupt threshold of the FIFO memory;
triggering one-time idle interruption when the data volume in the FIFO memory meets the idle interruption triggering condition;
the starting of the data transmission register, the IIC data transmission of the data to be transmitted based on the control register parameter, comprises the following steps:
and starting a data transmission register, responding to the idle interrupt based on the control register parameter, and carrying out IIC data transmission on the data to be transmitted.
6. The method according to any one of claims 2-4, further comprising:
inquiring whether the transmission of the sending command is finished or not based on the basic parameters of the IIC transmission mode; the sending instruction comprises the first sending instruction and the second sending instruction;
if the sending instructions are transmitted completely, continuously inquiring whether the main device is idle;
and if the master device is in an idle state, closing the data transmission register and finishing data transmission.
7. The method as claimed in any one of claims 1 to 3, wherein starting the data transfer register and performing IIC data transfer on the data to be transferred based on the control register parameter comprises:
and when the data transmission register is started, emptying all data and instructions in the data register, and carrying out IIC data transmission on the data to be transmitted based on the control register parameters.
8. The IIC data transmission device is applied to single chip microcomputer equipment, the single chip microcomputer equipment supports SPI transmission mode, IIC transmission mode and GPIO transmission mode switching, and the IIC data transmission device comprises:
the transmission instruction receiving module is used for closing the data transmission register according to the received data transmission instruction;
the basic parameter determining module is used for determining corresponding basic parameters of the IIC transmission mode according to the IIC transmission mode selection instruction in the data transmission instruction; the basic parameters corresponding to the IIC transmission mode comprise a read-write command, state parameters, a speed mode and high and low level parameters; the state parameters include the disabled states and addresses of the master device and the slave device;
the register parameter setting module is used for setting control register parameters corresponding to the IIC transmission mode based on the basic parameters corresponding to the IIC transmission mode so as to select two GPIO ports to form an IIC serial port and enter the IIC transmission mode;
and the data transmission module is used for starting the data transmission register and carrying out IIC data transmission on the data to be transmitted based on the control register parameter.
9. A single chip microcomputer device is characterized by comprising: four GPIO ports, a memory and a processor;
the four GPIO ports are used for carrying out GPIO communication, or selecting any three multiplexing as SPI ports from the GPIO ports to carry out SPI communication, or selecting any two multiplexing as IIC ports from the GPIO ports to carry out IIC communication;
the memory to store program instructions;
the processor, which is used to call and execute the program instructions in the memory, executes the method of any one of claims 1-7.
10. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium; the computer program, when executed by a processor, implements the method of any one of claims 1-7.
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