KR101041838B1 - Mobile storage control device and method - Google Patents

Abstract

The present invention relates to a storage control device and method for mobile. The mobile storage control apparatus according to the present invention includes a storage processor for controlling functions and storage by a request from a host processor, a communication between the host processor and the storage processor, and a first storage unit and a host processor temporarily storing programs and data. Or a second storage unit storing a program and data used by the storage processor, wherein the first storage unit communicates between the host processor and the storage processor and the volatile memory unit temporarily storing a mobile operating system program to be used by the host processor. It includes a DP memory unit for transmitting and receiving instructions or data for. According to the present invention, when performing the function of the mobile device, there is an effect of improving the system performance by controlling the low-speed storage medium at high speed.

Mobile, storage, storage processor, host processor

Description

MOBILE STORAGE CONTROL DEVICE AND METHOD}

The present invention relates to a storage control device and method for a mobile device, and more particularly, to a mobile storage control device and method effective for improving system performance by controlling a low-speed storage medium at high speed when performing a mobile function.

Multimedia services such as movies, games, and the Internet using mobile devices are becoming more common and multimedia functions are increasing. Accordingly, a system for managing and operating storage media (storage, storage) at low power and high speed is required.

The prior art can be largely divided into two. First, the first generation technology is a structure in which DRAM (Dynamic-Random-Access-Memory) and NAND (NAND structured nonvolatile memory) are directly attached to a host processor. In this structure, the processor operates NAND-Flash-Controller (NFC) and Flash-Translation-Layer (FTL) for direct NAND memory operation. This is a burden on the host processor has a disadvantage in that the performance is degraded. In addition, each time a new process NAND memory is used, the NFC or FTL must be modified, resulting in reduced production efficiency.

Another technology is the second generation, in which the host processor is equipped with a dedicated controller for mobile DRAM and NAND memory. This is unlike the first generation technology, where NAND memory does not attach directly to the host processor. This structure can reduce the burden on the host processor to process the NAND memory compared to the first generation technology. However, there is a disadvantage that performance decreases when transmitting and receiving large data due to the small buffer capacity of the NAND dedicated controller. In addition, hardware connection requires two circuit connections: a double-data-rate (DDR) interface for DRAM connectivity and a secure-digital / multi-media card (SD / MMC) interface for NAND memory connectivity. There is a need for a simple interface and improved methods for processing large amounts of data.

The present invention provides a storage control device for a mobile device such that the host processor controls the low-speed storage medium at high speed when performing a mobile function.

In addition, the present invention is to provide a mobile storage control device for reducing the share of the host processor when performing a mobile function, compared to the prior art.

In addition, the present invention is to provide a mobile storage control device that provides a simple hardware interface.

In addition, the present invention is to provide a mobile storage control device that can reduce power consumption compared to the prior art.

According to an embodiment of the present invention, a storage processor for controlling functions and storage by a request from a host processor, a communication between the host processor and the storage processor, a first storage unit for temporarily storing programs and data, and a host processor or storage And a second storage unit storing a program and data used by the processor, wherein the first storage unit includes instructions for communication between the host processor and the storage processor and a volatile memory unit temporarily storing a mobile operating system program to be used by the host processor. Provided is a mobile storage control device comprising a DP memory unit for transmitting and receiving data.

The host processor may include a baseband processor that performs communication, and an application processor that performs application and multimedia functions.

The storage processor may include an ARM family of microprocessors.

The volatile memory unit may include a first DRAM and a second DRAM. The first DRAM temporarily stores programs and data used by the storage processor stored in the second storage unit. The second DRAM temporarily stores programs and data used by the host processor stored in the second storage unit.

The DP memory may be SRAM or DRAM memory with dual ports.

The second storage unit is a nonvolatile memory. In addition, the second storage unit may further include an external memory supported by USB, Secure Digital (SD), or Multi-Media Card (MMC).

The connection between the host processor, the storage processor, and the first storage unit may be connected by a mobile high speed DDR interface.

The connection between the storage processor and the second storage unit may be connected by a high speed interface for nonvolatile memory.

According to another embodiment of the present invention, (a) the DP memory to store the instructions and data received from the host processor, (b) the DP memory generates an interrupt signal to pass to the storage processor, (c) A storage processor is provided, the method comprising: receiving a command or data stored in a DP memory by a storage processor; and (d) performing an operation corresponding to the received command by the storage processor.

After step (d), (e) the storage processor may further include checking whether there are other instructions after the operation is completed.

In step (e), if there are no other instructions, (f) the storage processor may include transmitting a completion signal to the host processor through the DP memory. If another command exists, steps (c) to (e) may be repeatedly performed until it is confirmed in step (e) that no other command exists.

According to the mobile storage control apparatus and method of the present invention, when performing a mobile function, the host processor can control the low-speed storage medium at high speed, thereby improving the system performance.

In addition, according to the present invention, since the host processor enters the sleep mode after data transfer, power consumption may be reduced.

In addition, according to the present invention, since the share of the host processor is reduced, there is an effect of improving the performance of the mobile device.

Further, according to the present invention, the use of the mobile high speed interface simplifies the configuration of the mobile system, thereby reducing the area and reducing the cost.

In addition, according to the present invention, there is an effect that enhanced security is possible than before.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description.

Hereinafter, embodiments of a mobile storage control apparatus and method according to the present invention will be described in detail with reference to the accompanying drawings, and in the following description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals. And duplicate description thereof will be omitted.

1 is a block diagram of a mobile storage control apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the mobile storage control device 100 includes a storage processor 101, a first storage unit 102, and a second storage unit 103.

Mobile storage control device 100 is configured to include the storage of the mobile, is a device for integrally controlling the storage of the mobile.

The storage processor 101 controls the storage included in the mobile storage control device 100. That is, the storage processor 101 performs an operation such as reading, writing, or deleting a program or data in the storage according to the received signal.

Storage included in the mobile storage control device 100 may be largely divided into a first storage unit 102 and a second storage unit 103.

The first storage unit 102 is mainly composed of volatile memory capable of high speed operation. That is, the main function of the first storage unit 102 is a cache memory function for temporarily storing data and programs, and a communication function between the host processor (200 of FIG. 2) and the storage processor 101.

The second storage unit 103 is mainly composed of a nonvolatile memory. That is, the main function of the second storage unit 103 stores a program or data used by the host processor (200 of FIG. 2) and the storage processor 101. In addition, the second storage 103 may include not only a nonvolatile memory included in the mobile device but also an external nonvolatile memory supporting USB or Secure Digital (SD) and MMC (multi-Media Card) formats.

2 is a block diagram illustrating a mobile storage system according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a mobile storage system may be largely classified into a host processor 200 and a mobile storage control device 210.

The host processor 200 executes the communication, application, and multimedia functions of the mobile. The host processor 200 includes a baseband processor 201 and an application & multimedia processor (AP / MP) 202. One of the baseband processor 201 and the AP / MP 202 may constitute the host processor 200, or the host processor 200 may be included in a single structure in which two processors are integrated into one.

The baseband processor 201 is a processor in charge of the communication function of the mobile. The baseband processor 201 is responsible for functions such as transmission and reception communication signal processing, signal compression processing, error correction, and communication system control. The communication signal is transmitted in compressed / modulated form. When the baseband processor 201 receives a communication signal, the baseband processor 201 performs a demodulation / decoder function, and performs functions such as error correction and communication control that occur during transmission.

The AP / MP 202 is a processor that performs mobile application and multimedia functions. The AP / MP 202 implements digital music, digital cameras, video, DVD movies, 2D / 3D functions, game GPS, mobile TV and web browsing.

As described with reference to FIG. 1, the mobile storage control device 210 is configured to include storage of a mobile and is an apparatus for integrally controlling the storage of a mobile.

The mobile storage control device 210 includes a first storage unit 102 (FIG. 1), a second storage unit 103 (FIG. 1), and a storage processor (101, 211 of FIG. 1).

The first storage unit 102 of FIG. 1 temporarily stores communication, programs, and data between the host processor 200 and the mobile storage control device 210. The first storage unit 102 of FIG. 1 includes a volatile memory capable of high speed operation, such as a first DRAM 212, a second DRAM 213, and a dual-port (DP) memory 214.

The first DRAM 212 is a DDR DRAM memory for data processing of the storage processor 211. That is, programs and data used by the storage processor 211 stored in the second storage unit 103 of FIG. 1 are temporarily stored. Firmware software used by the storage processor 211 after initial booting is temporarily stored in the first DRAM 212.

The second DRAM 213 is a DDR DRAM memory for data processing of the host processor 200. That is, programs and data used by the host processor 200 stored in the second storage unit 103 of FIG. 1 are temporarily stored. When the mobile system is booted, an OS (operating system) program stored in the second storage (103 of FIG. 1) is temporarily stored in the second DRAM 213 and used by the host processor 200.

The dual-port memory 214 is responsible for transmitting and receiving instructions or data for communication between the host processor 200 and the storage processor 211. Communication between the host processor 200 and the storage processor 211 is controlled by firmware stored in the second storage unit 103 (in FIG. 1) and a mobile operating system program. That is, communication of the DP memory may be controlled by firmware temporarily stored in the first DRAM 212 or a mobile operating system program temporarily stored in the second DRAM 213.

The DP memory 214 is composed of SRAM or DRAM with two inputs and outputs. The DP memory 214 may generate and control an interrupt or flag signal for predetermined protocol communication between processors in addition to the functions of a general dual-port SRAM or DRAM.

The second storage unit 103 of FIG. 1 stores programs and data used in the host processor 200 or the storage processor 211. The second storage unit 103 of FIG. 1 includes a nonvolatile memory that is an external memory that supports a flash memory 215, a USB 216, or an SD / MMC 217 format.

The flash memory 215 is a nonvolatile memory that stores programs and data used by the host processor 200 and the storage processor 211. The flash memory 215 is divided into a hidden area and a user area. Hidden areas are areas that use only FTL. The hidden area stores a table for operating an FTL, a log block for merging a flash memory block, and firmware for implementing a protocol between processors. Access to the hidden area is not possible in the operating system file system. The user area is the area operated by the file system of the host processor. Various user data and system data are stored in the user area by the file system, and logical addresses are mapped to physical addresses. In order to execute the program stored in the flash memory 215, the program is executed after moving to the first DRAM or the second DRAM.

The storage processor 211 controls the performance of performance and storage at the request of the host processor 200. The storage processor 211 may be a microprocessor of an ARM series (ARM7, ARM9, ARM10, ARM11, Cotex-A8 / 9, etc.). The instruction processing method of the storage processor 211 may be a reduced instruction set computer (RISC). This is an embedded system processor instruction method suitable for mobile devices with low power consumption and small chip size. However, the command processing method of the storage processor 211 is not limited to RISC. That is, the instruction processing method of the storage processor 211 may be easily changed by those skilled in the art.

The first bus 221 is a bus BUS connected to the host processor 200. Instructions from the host processor 200 are transmitted to the DP memory 214 through the first bus 221. In addition, data is transferred from the host processor 200 to the second DRAM 213 through the first bus 221, or the result of a program processed by the storage controller 210 for mobile is transmitted to the host in the DP memory 214. Transmitted to the processor 200.

The second bus 222 is a bus connecting the first DRAM 212 and the DP memory 214 to the storage processor 211. Through the second bus 212, data and programs may be transmitted and received between the first DRAM 212 and the storage processor 211.

The third bus 223 is a bus connecting the storage processor 211 and the flash memory 215. Data and programs stored in the flash memory 215 are transmitted to the storage processor 211 through the third bus 223. In addition, result values of data and programs processed by the storage processor 211 may be transmitted to the flash memory 223 through the third bus 223. The third bus 223 may be connected not only to the storage processor 211 and the flash memory 215 but also to an interface supporting the USB 216 and SD / MMC 217 formats. That is, the third bus 223 may be configured with two or more channels, and two or more ways according to the flash memory 215, the USB 216, and the SD / MMC 217 to be connected to each channel. Way) can have a structure. For example, if you have two channels and four flash memories connected to each channel, you have a two-channel two-way bus structure.

The first bus 221 and the second bus 222 may be implemented with a mobile high speed memory interface. For example, the mobile high speed memory interface implementing the first bus 221 and the second bus 222 may be a double-data-rate DRAM interface bus that satisfies the JEDEC DDR interface standard. The third bus 223 may be implemented as a high speed interface for nonvolatile memory. For example, the high speed interface for the nonvolatile memory implementing the third bus 223 may be a Flash interface through an ARM-AMBA (Advanced-Microcontroller-Bus-Architecture) bus. The first bus 221 and the second bus 222 may be implemented as one of DDR, DDR2, and DDR3 interfaces according to the performance of the mobile system, and may be selected and used among x16, x32, and x64 data bus sizes.

3 is a flowchart illustrating a method for controlling storage for mobile according to an embodiment of the present invention.

Referring to FIG. 3, a host processor first transmits an instruction and data to a DP memory (S301).

When the DP memory receives an instruction and data from the host processor, the DP memory generates an interrupt signal (S302).

The DP memory transmits the generated interrupt signal to the storage processor (S303).

When the storage processor receives the interrupt signal, the storage processor requests an instruction and data corresponding to the interrupt signal from the DP memory (S304).

The DP memory receiving the command and data request signal from the storage processor transmits the command and data stored in the DP memory to the storage processor (S305).

The storage processor interprets the received command and then performs a corresponding operation. (S306) For example, the command may be a request for writing data to a flash memory. The storage processor interprets the command and writes the data received from the DP memory to the flash memory.

After the storage processor performs an operation corresponding to the received command, the storage processor checks whether there is another command (S307). The storage processor may check whether there is a command other than the executed command among the received commands.

If another command exists, the storage processor performs an operation corresponding to the command (S306). Such an operation is repeatedly performed until no other command exists in the storage processor.

If no other command exists, the storage processor transmits a completion signal to the host processor (S308). When the storage processor checks the existence of another command after performing an operation according to the command, if no other command exists, the completion signal is completed. Create The storage processor sends the generated completion signal to the host processor. In this case, the completion signal may be transmitted directly from the storage processor to the host processor. In addition, the completion signal may be transmitted from the storage processor to the DP memory and then transmitted from the DP memory to the host processor.

4 is a flowchart illustrating a method of performing an operation by a storage processor in a mobile storage control system according to an exemplary embodiment of the present invention. This is a flow chart further dividing the step (S306 of FIG. 3) performing an operation corresponding to the command received by the storage processor of FIG.

Referring to FIG. 4, during an initial boot-up of a mobile storage control system, a storage processor temporarily stores a firmware program from a flash memory into a first DRAM (S401).

Subsequently, the storage processor receives commands and data from the DP memory (S402).

Subsequently, the storage processor searches for a program corresponding to the received command in the first DRAM (S403). The program search is not limited to a search in the first DRAM, but a search in an external storage connected to a mobile device is also possible.

Subsequently, the storage processor executes the retrieved program from the first DRAM. (S404) The storage processor does not directly execute the program stored in the flash memory in the flash memory but temporarily stores the program in the first DRAM to execute the program. This is because random addressing is impossible. That is, since the flash memory is a nonvolatile memory which cannot be directly executed, the program of the flash memory is temporarily stored in the first DRAM and used.

Subsequently, the program execution result value of the storage processor is transferred to the host processor or stored in the first DRAM or flash memory (S405). After the storage processor performs an operation according to an instruction, the storage processor delivers the result value to the host processor through the DP memory. Store in the first DRAM or flash memory. In this case, the storage of the result value may be stored in the mobile external storage as well as the internal storage.

5 is a flowchart illustrating a method of performing an operation by a host processor in a mobile storage control system according to an exemplary embodiment of the present invention.

Referring to FIG. 5, upon initial booting up of the mobile storage control system, the host processor brings an OS program from the flash memory to the second DRAM (S501).

Subsequently, the host processor receives an instruction and data from the DP memory (S502).

Subsequently, the program corresponding to the command received by the host processor is searched in the second DRAM. (S503) The program search is not limited to the search in the second DRAM, and the search in the external storage connected to the mobile device is also possible.

The host processor then executes the retrieved program from the second DRAM.

Next, the execution result value of the host processor is transferred to the storage processor or stored in the flash memory through the second DRAM or the DP memory (S505).

6 is an exemplary view showing the overall signal flow of the mobile storage system according to an embodiment of the present invention.

Referring to FIG. 6, A2 and A4 are signals directly transmitted and received between the host processor 600 and the storage processor 611. A2 is a wake-up signal from sleep mode. A4 is a power reset release signal. The storage processor 611 in the sleep mode may be switched to the active mode by the wake-up signal of A2. By the power reset release signal A4, the host processor 600 in the active mode can be switched to the sleep mode.

B2, B4, B6, and B8 are signals transmitted and received between the host processor 600, the first DRAM 612, the second DRAM 613, and the DP memory 614. B2 is an operating system (OS) image write signal. B2 may be a signal for storing data transmitted from the host processor 600 to the second DRAM 613. B4 is an OS image data read signal. B4 may be a signal for transmitting a result value performed by the host processor 600 from the second DRAM 613 to the host processor 600. B6 is a signal of message, command, address and data. B6 is a signal for the host processor 600 to transmit instructions and related data to be performed by the storage processor for mobile operation. B8 is an interrupt signal of the DP memory 614.

C2, C4, C6, and C8 are signals transmitted and received between the storage processor 611, the first DRAM 612, and the DP memory 614. C2 is an interrupt signal of the DP memory 614. C4 is a message signal of the storage processor 611. C4 is a signal for requesting an instruction and data stored in the DP memory 614 when the storage processor 611 receives an interrupt signal from the DP memory 614. C6 is a storage processor 611 firmware / FTL read signal. C6 is a signal for transmitting a program and data necessary for performing an operation corresponding to a command received by the storage processor 611 from the first DRAM. C8 is a storage processor 611 firmware / FTL write signal. C8 is a signal for transmitting the result value to the first DRAM 612 after performing the operation corresponding to the command received by the storage processor 611.

E2, E4, E6, E8, E10, and E12 are signals for transmission and reception between the storage processor 611 and storage such as flash memory 615, USB 616, SD / MMC 617, and the like. E2 is a data write signal of the flash memory 615. E2 is a data write signal for storing programs and data necessary for performing operations of the host processor 600 and the storage processor 611. In addition, E2 is a data write signal for storing the result value in the flash memory 615 after the operation of the host processor 600 and the storage processor 611 is performed. E4 is a data read signal of the flash memory 615. The E4 may store a program and data of the flash memory 615 for transferring a program and data necessary for performing an operation of the host processor 600 or the storage processor 611 to the first DRAM 612 or the second DRAM 613. This is a signal to read. E6 is a data write signal for storing data on a storage medium connected by a USB 616 interface. E8 is a data read signal from a storage medium connected by a USB 616 interface. E10 is a data write signal for storing data in a storage medium connected by an SD / MMC 617 interface. E12 is a data read signal from the storage medium connected by the SD / MMC 617 interface.

7 is a flowchart illustrating a data writing operation of a mobile storage system according to an embodiment of the present invention.

In FIG. 7, an embodiment of the present invention, an instruction to be processed by the host processor is to perform a write operation on data to a flash memory.

Referring to FIG. 7, the host processor transmits a write command to the DP memory (S701). The host processor checks whether there is an instruction to be processed. If a command exists to perform a write operation, the host processor sends a write command to the DP memory. The DP memory receiving the write command generates an interrupt signal (S702).

The DP memory transmits the generated interrupt signal to the storage processor (S703). The storage processor recognizes that an instruction has been transmitted from the host processor by an interrupt signal received from the DP memory.

The host processor transmits a data write command to the DP memory (S701) and then transmits data through the DP memory. (S704) The data transfer may be performed after the host processor transmits a write command to the DP memory or writes to the DP memory. When a command is passed, it can be passed with a write command.

The storage processor receiving the interrupt signal requests a command and data from the DP memory (S705).

The DP memory transmits commands and data requested from the storage processor to the storage processor (S706).

The storage processor performs a write operation on the received data to the flash memory (S707). The storage processor transfers the data received from the DP memory to the flash memory.

After the write operation is completed, the storage processor transmits a write operation completion signal indicating that data writing is completed to the DP memory (S708).

When the DP memory receives the write operation completion signal from the storage processor, the DP memory transmits a write operation completion signal to the host processor (S709). When the host processor receives the write operation completion signal from the DP memory, the DP memory recognizes that the data write operation is completed. do.

8 is a flowchart illustrating a data reading operation of a mobile storage system according to an embodiment of the present invention.

In FIG. 8, an embodiment of the present invention, an instruction to be processed by the host processor is to perform a data read operation from a flash memory.

Referring to FIG. 8, the host processor transmits a read command to the DP memory (S801). The host processor checks whether there is an instruction to be processed. If a command exists to perform a read operation, the host processor sends a read command to the DP memory. The DP memory receiving the read command generates an interrupt signal (S802).

The DP memory transmits the generated interrupt signal to the storage processor (S803). The storage processor recognizes that an instruction is transmitted from the host processor by an interrupt signal received from the DP memory.

The storage processor receiving the interrupt signal requests a command from the DP memory (S804).

The DP memory transmits a command requested from the storage processor to the storage processor (S805).

The storage processor requests data from the flash memory according to the received command.

The storage processor retrieves the data to be read from the flash memory and receives the retrieved data (S807).

After the completion of the read operation, the storage processor transmits a read operation completion signal to the DP memory indicating that data reading is completed (S808).

When the DP memory receives the read operation completion signal from the storage processor, the DP memory sends a read operation completion signal to the host processor (S809).

When the host processor receives a read completion signal from the DP memory, the host processor reads data (S810). That is, when the host processor receives a read operation completion signal from the DP memory, the host processor performs a data read operation and recognizes that instruction execution is completed. do.

9 is an exemplary view of a storage system package for a mobile according to an embodiment of the present invention.

Referring to FIG. 9, a mobile storage system package includes a host processor 900, a mobile storage control device 910, and external storages 914 and 915.

The mobile storage control device 910 includes a storage processor 911, a first storage unit 912, and a second storage unit 913.

Here, the storage processor 911, the first storage unit 912, and the second storage unit 913 are configured in the form of a system-in-package (SIP) included in a single package. The DRAM and the DP memory constituting the first storage unit 912 may be configured as separate chips or may be configured as a single chip.

The host processor 900 is configured as a separate package and is connected to the mobile storage control device 910 through a DDR interface.

The external storages 914 and 915 may include the SD / MMC 914 and the USB 124. The SD / MMC 914 is connected to the storage control device 910 for mobile by the SD / MMC standard interface. The USB 915 is connected to the mobile storage control device 910 by a USB interface. The SD / MMC 914 and the USB 915 may be additionally connected as necessary to a storage medium connected from the outside of the mobile.

10 is another exemplary diagram of a storage system package for a mobile according to an embodiment of the present invention.

Referring to FIG. 10, a storage system package for a mobile may largely include a host processor 110, an internal storage 120, a storage processor 130, and external storage 123 and 124. In other words, the internal storage 120 and the storage processor 130 are configured in separate packages.

The internal storage 120 includes the first storage 121 and the second storage 122 in a single package. In the first storage 121, the DRAM and the DP memory may be configured as separate chips or as a single chip.

The host processor 110 and the storage processor 130 are each configured in separate packages.

The host processor 110 is connected to the internal storage 120 through the DDR interface. The storage processor 130 may also be connected to the DRAM of the internal storage 120 system through the DDR interface and may be connected to the flash memory through a flash controller.

In addition, the external storages 123 and 124 may be additionally connected to the storage medium connected from the outside of the mobile as needed.

The mobile storage control device 100 receives a command of the host processor 100 through a DP memory of the storage 200 controlled by the DDR controller 134 of the storage control block 130. The received command is input to the mobile storage processor through the highway bus 112.

According to the mobile storage control apparatus and method according to an embodiment of the present invention, when the mobile function is performed, the host processor can control the low-speed storage medium by the storage processor, thereby improving system performance.

In addition, according to the present invention, since the host processor enters the sleep mode after data transfer, power consumption may be reduced.

In addition, according to the present invention, since the share of the host processor is reduced, there is an effect of improving mobile performance.

Further, according to the present invention, the use of the mobile high speed interface simplifies the configuration of the mobile system, and has the effect of reducing the area and reducing the cost.

In addition, according to the present invention, there is an effect that enhanced security is possible than before.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the invention may be varied and varied without departing from the scope of the invention.

1 is a block diagram of a storage control device for a mobile according to an embodiment of the present invention.

2 is a block diagram illustrating a mobile storage system according to an embodiment of the present invention.

Figure 3 is a flow chart showing a storage control method for a mobile according to an embodiment of the present invention.

4 is a flowchart illustrating a method of performing an operation by a storage processor in a mobile storage control system according to an exemplary embodiment of the present invention.

5 is a flowchart illustrating a method of performing an operation by a host processor in a mobile storage control system according to an exemplary embodiment of the present invention.

Figure 6 is an exemplary view showing the overall signal flow of the mobile storage system according to an embodiment of the present invention.

7 is a flowchart illustrating a data writing operation of a mobile storage system according to an embodiment of the present invention.

8 is a flowchart illustrating a data reading operation of a mobile storage system according to an embodiment of the present invention.

9 is an exemplary view of a storage system package for a mobile according to an embodiment of the present invention.

10 is another exemplary diagram of a storage system package for a mobile according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 210 910: Storage Control Unit for Mobile

101 130 211 911: Storage Processor

110 200 900: Host Processor

102 121 912: First storage

103 122 913: secondary storage

Claims (15)

A storage processor controlling storage and function performance by a request from a host processor; A first storage unit configured to temporarily store communication and programs and data between the host processor and the storage processor; And A second storage unit for storing the program and data used by the host processor or the storage processor, The first storage unit includes a volatile memory unit for temporarily storing a mobile operating system program to be used by the host processor and a DP memory unit for transmitting and receiving commands or data for communication between the host processor and the storage, the second storage unit Is non-volatile memory, The volatile memory unit includes a first DRAM and a second DRAM, wherein the first DRAM temporarily stores programs and data used by the storage processor stored in the second storage unit. And a program and data used by the host processor stored in the second storage unit are temporarily stored. The method of claim 1, The host processor includes a baseband processor for communicating, and an application processor for performing applications and multimedia functions. The method of claim 1, The storage processor is a mobile storage control device comprising a microprocessor of the ARM series. delete The method of claim 1, The second storage unit may further include an external memory supported by USB, Secure Digital (SD), or Multi-Media Card (MMC). delete delete delete The method of claim 1, And the DP memory unit is an SRAM or DRAM memory. The method of claim 1, And the host processor, the storage processor, and the first storage unit are connected by a mobile high speed DDR interface. The method of claim 1, And the storage processor and the second storage unit are connected by a high speed interface for nonvolatile memory. (a) storing, by the DP memory, instructions and data received from the host processor; (b) the DP memory generating an interrupt signal and delivering the interrupt signal to a storage processor; (c) the storage processor receiving the instructions or the data stored in the DP memory; (d) the storage processor performing an operation corresponding to the received instruction; Step (d) (d-1) at the initial boot-up of the mobile storage control system, the storage processor fetching and temporarily storing a firmware program from flash memory into the first DRAM; Wow (d-2) the storage processor searching for the program in the first DRAM corresponding to the command received from the DP memory; Wow (d-3) the storage processor executing the retrieved program from the first DRAM; Wow (d-4) transferring a result value of executing the program of the storage processor to the host processor or storing the result value in the first DRAM; The method of claim 12, After the step (d), and (e) checking, by the storage processor, the DP memory if there are other instructions after completion of the operation. The method of claim 13, In the step (e), If the other command does not exist, (f) the storage processor transmits a completion signal to the host processor through the DP memory. The method of claim 13, If the other command exists, until it is confirmed in step (e) that the other command does not exist, Mobile storage control method, characterized in that for repeating the steps (c) to (e).

Images