KR101137297B1 - Mobile storage control method - Google Patents

Abstract

The present invention relates to a mobile storage control method. A method of controlling storage of a mobile device, the method comprising: (a) receiving a command input from an outside of the mobile by the host processor, (b) storing the command and data in the DP memory by the host processor, and (c) storing the command and data in the DP memory. Generating and sending an interrupt to the storage processor by the stored DP memory; (d) the storage processor receiving the interrupt decrypts the instructions and data stored in the DP memory; (F) transmitting a command response, which is a result of the storage processor performing an operation corresponding to the command, to the DP memory, and (g) the DP memory transmitting an interrupt for the received command response to the host processor. Step and (h) instructions from the DP memory by the host processor receiving the interrupt for the command response. Receiving a response.

Description

How to control your mobile storage {MOBILE STORAGE CONTROL METHOD}

The present invention relates to a mobile storage control method.

Multimedia services such as movies, games, and the Internet using mobile devices are becoming more common and multimedia functions are increasing. Accordingly, a system for managing and operating storage media (storage, storage) at low power and high speed is required.

The prior art can be largely divided into two. First, the first generation technology is a structure in which DRAM (Dynamic-Random-Access-Memory) and NAND (NAND structured nonvolatile memory) are directly attached to a host processor. In this structure, the processor operates NAND-Flash-Controller (NFC) and Flash-Translation-Layer (FTL) for direct NAND memory operation. This is a burden on the host processor has a disadvantage in that performance is reduced. In addition, each time a new process NAND memory is used, the NFC or FTL must be modified, resulting in reduced production efficiency.

Another technology is the second generation, in which the host processor is equipped with a dedicated controller for mobile DRAM and NAND memory. This is unlike the first generation technology, where NAND memory does not attach directly to the host processor. This structure can reduce the burden on the host processor to process the NAND memory compared to the first generation technology. However, there is a disadvantage that performance decreases when transmitting and receiving large data due to the small buffer capacity of the NAND dedicated controller. In addition, hardware connection requires two circuit connections: a double-data-rate (DDR) interface for DRAM connectivity and a secure-digital / multi-media card (SD / MMC) interface for NAND memory connectivity. There is a need for a simple interface and improved methods for processing large amounts of data.

The present invention provides a mobile storage control method that can reduce the share of the host processor to perform the mobile function by the storage processor capable of controlling and managing the mobile storage.

The present invention provides a mobile storage control method capable of controlling a low speed storage at a high speed using a storage processor.

According to an aspect of the present invention, in a storage control method of a mobile, (a) the host processor receives a command input from the outside of the mobile, (b) the host processor storing the command and data in the DP memory (c) the DP memory storing instructions and data generating and transmitting an interrupt to the storage processor, (d) the storage processor receiving the interrupt decrypts the instructions and data stored in the DP memory, (e) the storage processor Performing an operation corresponding to the command decoded by the processor; (f) transmitting a command response, which is a result of the storage processor performing the operation corresponding to the command, to the DP memory; Sending an interrupt to the host processor and (h) receiving the interrupt for the command response. The processor includes the step of receiving a command reply from the DP memory.

After step (a), the method may further include (a-1) checking whether the received command is a general command or an interrupt command.

After the step (a-1), if the command received by the host processor is a general command, the host processor checks the ownership of the DP memory and (a-3) the ownership of the DP memory. If there is no ownership of the DP memory, the method may further include acquiring ownership of the DP memory by sending an interrupt instruction for the ownership request of the DP memory to the storage processor through the DP memory.

After step (a-1), when the command received by the host processor is an interrupt command, the host processor may further include storing the interrupt command and data in an interrupt area of the DP memory.

After step (a), the host processor may further include checking whether the storage processor is activated.

In operation (a-5), when the storage processor is in a deactivated state, the host processor may further include transmitting a command for activating the storage processor to the storage processor through the DP memory.

After step (a), the host processor may further include checking whether there is an empty command queue among the command queues of the DP memory.

In step (a-7), if there is no empty command queue among the command queues of the DP memory, (a-8) the host processor transfers ownership of the DP memory to the storage processor and (a-9) the storage processor DP The method may include executing an instruction stored in the memory, and among the instructions stored in the DP memory, the instruction executed by the storage processor may be deleted.

In step (a-7), if there is no empty command queue in the command queue of the DP memory, the host processor may delete the command stored in the command queue of the DP memory.

In step (d), the storage processor may sequentially decode and execute instructions to be executed based on circular queue header information in the DP memory.

After step (e), the storage processor (e-1) may determine whether to maintain ownership of the DP memory.

In step (e-1), when the storage processor does not maintain ownership of the DP memory, the method may further include transferring ownership of the DP memory to the host processor.

The command response may include a result of performing an operation corresponding to the command, a command code, and a command index.

In step (f), when the storage processor transmits the last command response among the command responses to the DP memory, ownership of the DP memory may be transferred to the host processor.

Prior to step (f), (f-1) may further include determining whether the storage processor transmits a command response to the DP memory.

In step (f-1), if the (f-2) storage processor does not transmit a response to the command, it may return to step (b).

After the step (b), the host processor may further include updating the command list by storing the command stored in the DP memory in a storage space in which the command list to be executed by the storage processor is stored.

After the step (h), (h-1) the host processor may further comprise the step of comparing the received command processing result with the command list to determine whether there are no missing instructions.

After step (h), the host processor may further include checking whether there is another command input from the outside of the mobile while the storage processor performs an operation corresponding to the command.

In step (h-2), if there is another instruction (h-3), the host processor is executed again from step (b) and (h-4) if there is no other instruction, the host processor terminates the instruction processing. It may further comprise the step.

According to another aspect of the invention, in the interrupt instruction processing method of the storage processor for mobile storage control, (a) checking the interrupt flag, (b) when the receipt of the interrupt from the interrupt flag is confirmed, DP memory Decrypting the interrupt instruction received from the processor; (c) executing the interrupt instruction; (d) determining whether to maintain ownership of the DP memory; and (e) determining whether to transmit the interrupt instruction execution result to the host processor. And (f) transmitting the interrupt instruction execution result to the host processor.

According to the present invention, since the storage control and management of the mobile is processed by the storage processor to reduce the share of the host processor has the effect of improving the performance of the mobile.

According to the present invention, when the mobile function is performed, the host processor controls the low speed storage medium at high speed using the storage processor, thereby improving system performance.

In addition, according to the present invention, there is an effect that the host processor and the storage processor can be divided by the mobile function to enhance the security.

According to the present invention, when the host processor and the storage processor do not perform the mobile function, the power consumption may be reduced by entering the low power mode.

1 is a block diagram illustrating an apparatus for controlling a storage processor according to an exemplary embodiment of the present invention.
2 is a diagram illustrating an internal configuration of a DP memory according to an embodiment of the present invention.
3 is a flowchart illustrating a method for controlling storage of a mobile according to an embodiment of the present invention.
4 is a flowchart of instruction processing of a host processor according to an embodiment of the present invention.
5 is a flow chart for instruction processing of a storage processor in accordance with an embodiment of the present invention.
6 is a flowchart illustrating command response processing of a host processor according to an embodiment of the present invention.
7 is a flowchart illustrating a command processing method of a host processor according to a type of a general command according to an embodiment of the present invention.
8 is a flowchart illustrating an interrupt command processing method of a storage processor according to an exemplary embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description.

Hereinafter, embodiments of the mobile storage control method according to the present invention will be described in detail with reference to the accompanying drawings, in the following description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and duplicated thereto The description will be omitted.

1 is a block diagram illustrating an apparatus for controlling a storage processor according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the storage processor control apparatus includes a host processor 110, a storage processor 120, a DP memory 130, an H-port 140, and an M-port 150.

The host processor 110 executes the communication, application, and multimedia functions of the mobile. The host processor 110 includes a baseband processor and an application & multimedia processor (AP / MP). One of the baseband processor and the AP / MP may constitute the host processor 110, or the host processor 110 may be included in a single structure in which two processors are integrated into one.

The baseband processor is a processor that is responsible for the communication function of the mobile. Baseband processor It is responsible for functions such as transmission and reception communication signal processing, signal compression processing, error correction and communication system control. The communication signal is transmitted in compressed / modulated form. When the baseband processor receives a communication signal, the baseband processor performs a demodulation / decoder function to correct errors occurring during transmission and to control a communicator.

AP / MP is a processor that performs mobile application and multimedia functions. AP / MP implements digital music, digital cameras, video, DVD movies, 2D / 3D capabilities, gaming GPS, mobile TV and web browsing.

The storage processor 120 controls function execution and mobile storage by request of the host processor 110. That is, the storage processor 120 reads, writes, or deletes a program or data in the storage according to the received signal.

Mobile storage includes volatile or nonvolatile memory included in mobile. The mobile storage may also include external memory that supports USB or Secure Digital (SD) and Multi-Media Card (MMC) formats. Mobile storage stores the operating system, operating system, and data of the mobile.

The storage processor 120 may be a microprocessor of an ARM series (ARM7, ARM9, ARM10, ARM11, Cotex-A8 / 9, etc.). The instruction processing method of the storage processor 120 may be a reduced instruction set computer (RISC). This is an embedded system processor instruction method suitable for mobile devices with low power consumption and small chip size. However, the command processing method of the storage processor 120 is not limited to RISC. That is, the instruction processing method of the storage processor 120 can be easily changed by those skilled in the art.

The DP memory 130 is responsible for transmitting and receiving instructions or data for communication between the host processor 110 and the storage processor 120. The DP memory 130 is composed of SRAM or DRAM having two inputs and outputs. The DP memory 130 may generate and control an interrupt signal for predetermined protocol communication between processors in addition to the functions of a general dual-port SRAM or DRAM.

The DP memory 130 includes a general command area 131, an interrupt command area 132, and a data area 133. The general command area 131 stores a list of commands received from the host processor 110. The interrupt command area 132 stores an interrupt command that informs the host processor 110 or the storage processor 120 of the ownership change or data transfer of the DP memory 130. The data area 133 is an area where data is stored for data transmission.

The H-port 140 is an input / output port (I / O port) connected for communication and data transmission between the host processor 110 and the DP memory 130. Instructions and data are transmitted from the host processor 120 to the DP memory 130 through the H-port 140, or the processing results from the storage processor 120 are transmitted from the DP memory 130 to the host processor 110. do.

The M-port 150 is an input / output port (I / O port) connected for communication and data transmission between the storage processor 120 and the DP memory 130. Instructions and data from the host processor 120 stored in the DP memory 130 are transmitted to the storage processor 120 through the M-port 150, or the processing result of the storage processor 120 is the DP memory 130. Is sent to.

H-port 140 and M-port 150 may be implemented with a mobile high speed memory interface. For example, the mobile high speed memory interface implementing H-port 140 and M-port 150 may be a Double-Data-Rate DRAM interface bus that meets the JEDEC DDR interface standard. In addition, the H-port 140 and the M-port 150 can be implemented as one of the DDR, DDR2, DDR3 interface according to the performance of the mobile system, it is possible to select from the x16, x32, x64 data bus size Do.

That is, when the host processor 110 receives a command from the mobile operating system, the storage processor control device stores the command and data in the DP memory 130. In this case, ownership of the DP memory 130 is owned by the host processor 110. When the DP memory 130 receives the command and data from the host processor 110, the DP memory 130 transmits an interrupt to the storage processor 120. When the storage processor 120 receives the interrupt, the storage processor 120 receives and executes a command stored in the DP memory 130. At this time, ownership of the DP memory 130 is owned by the storage processor 120. The storage processor 120 transmits the instruction execution result and the ownership of the DP memory 130 to the DP memory 130. The DP memory 130 transmits the received command execution result to the host processor 120.

Data received from the host processor 120 may be transmitted to a storage (not shown) by a write command. The storage (not shown) may be a storage medium embedded in the mobile or an external storage medium connected to the mobile. The storage (not shown) may include any one or more of storage media such as flash memory, USB, and SD / MMC. Data received from the storage processor 120 may be accessed by the host processor 110 by a read command.

By the storage processor control device as described above, the storage processor 120 performs the storage control of the mobile by the command of the host processor 110, thereby reducing the occupancy of the host processor 110.

2 is a diagram illustrating an internal configuration of a DP memory according to an embodiment of the present invention.

Referring to FIG. 2, the DP memory includes an instruction region 210, a data region 220, an instant data region 230, a ownership and an interrupt region 240.

The instruction region 210 is an region in which instructions transmitted from a host processor are stored. The command area 210 includes a queue manager 211, a header 212, a tail 213, and a command queue 214.

Queue manager 211 manages command queue 214. The queue manager 211 classifies an instant command or a general command according to the command type and stores the instant command or the general command in a circular queue. The queue manager 211 uses the index of the header 212 or tail 213 to determine the start and end of an instant instruction or a general instruction. The queue manager 211 stores and manages commands so that there is no empty space between the queues and queues, and processes the commands stored in the queue sequentially from the start queue.

Header 212 and tail 213 store the start index and end index of instruction queue 214.

The instruction queue 214 is an area for storing instructions received from the host processor. Since the number of instructions that can be stored in the command queue 214 affects the performance of the protocol, the performance of the protocol is designed to be optimal. The remainder of the command queue 214 except for the first instant command is an area for general commands. That is, the first command of the command queue 214 is allocated to the instant write / read command area.

DP memory is operated so that there are no empty instructions between the start and end instructions. The DP memory is operated in a round-robin manner after writing from the first area to the last area of the command queue 214, and then returning to the beginning again.

The data area 220 is an area in which data received from the host processor and the storage processor are stored.

The instant data area 230 is an area where data according to an instant command is stored. Instant data is data that will be written to the flash memory area immediately, and will be executed prior to general data write commands.

The ownership and interrupt area 240 is an area where data relating to the interrupt signal and ownership of the DP memory (130 in FIG. 1) are stored. Ownership of the DP memory (130 in FIG. 1) serves to prevent confusion between the host processor (110 in FIG. 1) and the storage processor (130 in FIG. 1) in using the DP memory. Ownership of the DP memory (130 in FIG. 1) allows the host processor (110 in FIG. 1) or the storage processor (120 in FIG. 1) to access the DP memory. Ownership of the DP memory 130 of FIG. 1 may be determined according to instructions of the host processor 110 of FIG. 1. Ownership of the DP memory (130 in FIG. 1) can be used using a flag scheme. Meanwhile, an interrupt area is used for interruption between the host processor 110 (in FIG. 1) and the storage processor (120 in FIG. 1).

When transmitting and receiving commands and data for storage control, high speed storage control may be performed by using a high speed DP memory instead of a conventional low speed nonvolatile memory.

3 is a flowchart illustrating a storage control method of a mobile according to an embodiment of the present invention.

Referring to FIG. 3, first, a host processor receives a command input from the outside of the mobile (S110). For example, the command input from the outside of the mobile may be data writing, reading, and deleting data in the storage. It is apparent that the type of instruction is not limited thereto and may be changed by those skilled in the art. The storage may be an external storage medium included in or connected to the mobile.

Subsequently, the host processor stores the received instruction and data in the DP memory (S120). If the received command is a general command or an instant command, the command is stored in the command queue of the DP memory. In addition, the data for the general command may be stored in the data area of the DP memory, and the command for the instant command may be stored in the instant data area of the DP memory. If the received command is an interrupt command, the interrupt command and data may be stored in an interrupt area of the DP memory.

Subsequently, the DP memory in which the command and the data are stored generates an interrupt to the storage processor and transmits the interrupt to the storage processor (S130).

Subsequently, the storage processor receiving the interrupt decodes the command and data stored in the DP memory (S140).

Subsequently, the storage processor performs an operation corresponding to the decrypted command (S150). For example, when the instruction read by the storage processor is a data write, the storage processor may perform a write operation to the storage using the received data. For example, when the instruction decrypted by the storage processor is data deletion, the storage processor may perform an operation of deleting data stored in the storage.

Subsequently, the storage processor transmits a command response, which is a result of performing an operation corresponding to the command, to the DP memory (S160).

Subsequently, the DP memory transmits an interrupt for the received command response to the host processor (S170).

Subsequently, the host processor receiving the interrupt for the command response receives the command response from the DP memory (S180).

As such, in accordance with an embodiment of the present invention, the host processor does not directly perform storage control of the mobile. The host processor sends instructions to the storage processor to perform storage control. Thus, the storage processor's share of the mobile processor's storage control and management is reduced.

In addition, during storage control and management, command and data transfer between the host processor and the storage processor may be performed through the high speed DP memory, thereby controlling the low speed storage medium at high speed.

4 is a flow chart for instruction processing of a host processor according to an embodiment of the present invention.

Referring to FIG. 4, the host processor receives a command input from the outside of the mobile (S110).

Subsequently, the host processor determines the type of the received instruction (S111). The host processor determines whether the received instruction is a general instruction or an interrupt instruction.

If the input command is an interrupt command, the host processor stores the command and data of the DP memory (S120). At this time, the interrupt instruction and data are stored in the interrupt area of the DP memory. The interrupt instruction may be release ownership, suspend, resume, cancel, read status, or the like. The host processor stores the corresponding instruction in the interrupt register among the interrupt regions of the DP memory and stores data in the interrupt data region.

If the input command is a general command, the host processor verifies ownership of the DP memory (S112).

If the ownership of the DP memory is not the host processor, the host processor may request ownership of the DP memory from the storage processor (S113).

Subsequently, the host processor acquires ownership of the DP memory from the storage processor by requesting ownership of the DP memory (S114).

If the ownership of the DP memory is the host processor, steps S113 and S114 of requesting and acquiring ownership of the DP memory to the storage processor may be omitted.

Subsequently, the host processor checks the state of the storage processor (S115).

If the state of the storage processor is inactive, the host processor transmits an instruction for activating the storage processor (S116) to make the storage processor active. In this case, the deactivation state is a low power state, such as the storage processor is in a sleep state or a deep sleep state.

If the state of the storage processor is activated, the step S116 of transmitting a command for activating the storage processor may be omitted.

Subsequently, the host processor checks whether there is an empty instruction queue in the DP memory (S117).

If there is no empty command queue in the DP memory, according to an embodiment of the present invention, the host processor may request the DP memory to delete an instruction stored in the command queue of the DP memory (S118).

 The method of deleting a command stored in the command queue of the DP memory is not limited thereto. In another embodiment of the present invention for deleting an instruction stored in an instruction queue of a DP memory, the host processor may transfer ownership of the DP memory to the storage processor. The storage processor with ownership of the DP memory can access the DP memory and execute instructions stored in the DP memory. In this case, the command executed by the storage processor may be deleted. Through this process, the command queue of the DP memory may be empty.

Subsequently, the host processor may store instructions and data in the DP memory and transmit ownership of the DP memory to the storage processor (S120). The host processor may copy and store instructions and data in the DP memory, and store information about the queue in a header.

Subsequently, the host processor updates a list of instructions to be executed by the storage processor (S105). The host processor may update the command list by storing the command stored in the DP memory in a storage space in which the command list to be executed by the storage processor is stored.

5 is a flowchart of instruction processing of a storage processor according to an embodiment of the present invention.

Referring to FIG. 5, the storage processor receives an interrupt from a DP memory (S130).

Subsequently, the storage processor verifies ownership of the DP memory (S131). The storage processor may check a register value of the ownership area to verify ownership of the DP memory. The storage processor can identify the processor that has ownership through the value of the ownership register of the identified DP memory. That is, the storage processor may determine whether the host processor or the storage processor owns DP memory that can access the instructions and data stored in the DP memory through the ownership register value.

If the storage processor does not have ownership of the DP memory, the step of verifying ownership of the DP memory may be repeated until the storage processor acquires ownership of the DP memory.

If the storage processor has ownership of the DP memory, the storage processor may receive a command to be executed from the DP memory (S132).

Subsequently, the storage processor decrypts the command received from the DP memory (S140). That is, the storage processor having ownership of the DP memory can access the DP memory to check what operation the stored instruction is to perform. For example, the storage processor may find and decode the queue start command and execute the command based on the circular queue header information of the DP memory.

Subsequently, the storage processor performs an operation corresponding to the command (S150). The storage processor may execute an instruction received from the host processor using data stored in the DP memory according to the decrypted instruction.

Subsequently, when the execution of the command is completed, the storage processor determines whether ownership of the DP memory should be maintained (S151).

If it is necessary to transfer ownership of the DP memory to the host processor, the storage processor transfers ownership of the DP memory to the host processor through the DP memory (S152).

If it is not necessary to transfer ownership of the DP memory to the host processor, the storage processor may omit step S152 of transferring ownership to the host processor.

Subsequently, the storage processor determines whether to send a response to the command to the host processor (S153).

If it is not necessary to transmit the response to the host processor, the storage processor may perform the operation again from the step S131 of verifying ownership of the DP memory.

If it is necessary to transmit the response to the host processor, the storage processor transmits the response to the DP memory (S160). The command response may include a result of performing an operation corresponding to the command, a command code, and a command index.

In the embodiment of the present invention, the order of the instruction processing of the storage processor described above may be changed by those skilled in the art. That is, in the embodiment, the storage processor determines whether to maintain ownership of the DP memory, and then determines whether to transmit a command response. However, the storage processor may determine whether to maintain ownership of the DP memory after determining whether to transmit a command response. In addition, when the storage processor transmits the last command response of the command response to the DP memory, ownership of the DP memory may be transferred to the host processor.

In other words, it is apparent to those skilled in the art that the order of processing instructions of the storage processor is not limited to the order of FIG. 7 and can be easily changed without departing from the technical spirit.

6 is a flowchart illustrating command response processing of a host processor according to an embodiment of the present invention.

Referring to FIG. 6, the host processor receives an interrupt for a command response from the DP memory (S170). When the command response is transmitted from the storage processor for the command to the DP memory, the host processor may receive an interrupt generated from the DP memory. Can be. In this case, the host processor may transfer ownership of the DP memory owned by the storage processor.

Subsequently, the host processor receives a command response from the DP memory (S180). That is, the host processor may receive a processing result of storage control performed by the storage processor by an instruction.

Subsequently, the host processor checks whether there is an unprocessed instruction (S181). The host processor may check whether there is an unprocessed command by using the received command response and the command list.

If there is an unprocessed instruction, the host processor may be executed again from the step of checking whether the instruction queue is empty in the DP memory (S117 of FIG. 6).

If there is no unprocessed instruction, the host processor checks whether there is another instruction input from the outside of the mobile while the storage processor processes the instruction (S182).

If there are other instructions, the host processor may be executed again from the step of checking the type of the received instructions (S111 of FIG. 6).

If there is no other command, the host processor terminates the command processing for controlling the storage (S183).

7 is a flowchart illustrating a command processing method of a host processor according to a type of a general command according to an embodiment of the present invention.

Referring to FIG. 7, the host processor checks the type of the received general command (S910). For example, general commands include write, read, new protection, erase, and flush commands. Before the host processor confirms the type of the general instruction, the step of confirming the type of the instruction received by the host processor (S111 of FIG. 6) may be performed.

If the command received by the host processor is a write command, the host processor writes data to the data area of the DP memory (S920). Here, the data is data to be input from outside the mobile and stored in the storage. At this time, when data writing is completed in the area of the DP memory, the host processor checks whether there is another general command input (S910).

If the command received by the host processor is a read, new protection, delete, or flush command, data corresponding to the command is written in the data area of the DP memory (S930).

If the command received by the host processor is an instant read or instant write command, the host processor writes the instant read or instant write command and data to the instant area of the DP memory (S940).

Subsequently, the host processor transmits ownership of the DP memory to the storage processor (S931).

Here, steps 930 to S931 are steps corresponding to step S120 of FIG. 6.

Subsequently, the host processor receives a response to the command from the storage processor (S932). In this case, step S932 corresponds to step S180 of FIG. 7.

Subsequently, when the host processor receives a response to the command from the storage processor, the host processor checks the information on the order processing order in the queue manager area of the DP memory (S933).

If the received response is delivered after a command such as read, instant read, read info, read protection info, etc. is processed, the host processor may read the read data of the mobile operating system. Transfer to the file system (S934).

If the response received by the host processor is a command such as New Protection, Clear Protection, Change Password, Delete, Flush, or Force Erase, the host processor sends the received response to the mobile. Transfer to the file system of the operating system (S935).

8 is a flowchart illustrating an interrupt command processing method of a storage processor according to an exemplary embodiment of the present invention.

Referring to FIG. 8, first, the storage processor checks an interrupt flag Flag in operation S810. The interrupt flag is a predefined bit used for interrupts. That is, when a command processor and a data are transmitted from the host processor to the DP memory, the DP memory generates an interrupt and transmits the interrupt to the storage processor. At this time, the interrupt flag may be set. The number of bits and the set method of the interrupt flag can be variously changed by those skilled in the art.

If the interrupt flag is not set (Flag == 0) (S820), the storage processor returns to the first step (S810).

If the interrupt flag is set (Flag == 1) (S830), the storage processor decodes an instruction of the DP memory (S840). In other words, if the interrupt flag is set, the host processor stores the instructions to be processed by the storage processor in the DP memory. Thus, if the interrupt flag is set, the storage processor may access the DP memory and decode the stored instruction.

Subsequently, the storage processor executes an operation according to the decrypted interrupt command (S850).

Subsequently, when the interrupt instruction execution (S850) is completed, the storage processor determines whether to maintain ownership of the DP memory or transfer the host processor to the host processor (S860).

If it is necessary to transfer ownership of the DP memory to the host processor, the storage processor transfers ownership of the DP memory to the host processor through the DP memory (S870).

If it is not necessary to transfer ownership of the DP memory to the host processor, step S870 of transferring ownership to the host processor may be omitted.

Subsequently, the storage processor determines whether a response to the execution of the interrupt command should be transmitted to the host processor (S880).

If it is not necessary to send a response to the host processor, the storage processor may return to the first step (S810).

If it is necessary to transmit the response to the host processor, the storage processor transmits the response to the host processor through the DP memory (S890). After the storage processor transmits a response to the command processing to the host processor, the storage processor may return to the first step (S810) and execute again from the beginning.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

110: host processor
120: storage processor
130: DP memory
131: general command area
132: interrupt instruction area
133: data area
140: H-port
150: M-port

Claims (21)

delete delete In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
After step (a),
(a-1) checking, by the host processor, whether the received instruction is a general instruction or an interrupt instruction,
After the step (a-1),
(a-2) if the command received by the host processor is a general command, verifying ownership of the DP memory; And
(a-3) if the host processor does not have ownership of the DP memory as a result of confirming ownership of the DP memory, by sending an interrupt instruction for the ownership request of the DP memory to the storage processor through the DP memory, And obtaining ownership of the DP memory.
In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
After step (a),
(a-1) checking, by the host processor, whether the received instruction is a general instruction or an interrupt instruction,
After the step (a-1),
(a-4) when the command received by the host processor is an interrupt command,
The host processor further comprises the step of storing the interrupt instruction and data in the interrupt area of the DP memory.
In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
After the step (a),
(a-5) The host processor further comprises the step of checking whether the storage processor is active.
The method of claim 5,
In the step (a-5),
(a-6) when the storage processor is inactive,
And transmitting, by the host processor, a command to activate the storage processor to the storage processor through the DP memory.
In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
After the step (a),
(a-7) The host processor further comprises checking whether there is an empty command queue among the command queues of the DP memory.
The method of claim 7, wherein
In the step (a-7),
If there is no empty command queue among the command queues of the DP memory,
(a-8) the host processor transmitting ownership of the DP memory to the storage processor; And
(a-9) the storage processor executing an instruction stored in the DP memory,
And among the instructions stored in the DP memory, instructions executed by the storage processor to delete.
delete In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
In the step (d),
And the storage processor sequentially decrypts and executes a command to be performed based on circular queue header information in the DP memory.
In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
After step (e),
(e-1) the storage processor further comprising determining whether to maintain ownership of the DP memory.
The method of claim 11,
In the step (e-1),
(e-2) if the storage processor does not maintain ownership of the DP memory, transferring ownership of the DP memory to the host processor.
In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
In the step (f),
The command response includes a result of performing an operation corresponding to the command, a command code, a command index.
In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
In the step (f),
And when the storage processor transmits the last command response of the command response to the DP memory, ownership of the DP memory is transferred to the host processor.
In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
Before step (f) above,
and (f-1) determining whether the storage processor transmits the command response to the DP memory.
The method of claim 15, wherein in step (f-1),
(f-2) if the storage processor does not transmit a response to the command, the method returns to step (b).
In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
After step (b),
and (b-1) updating the command list by storing the command stored in the DP memory in a storage space in which the command list to be executed by the storage processor is stored.
The method of claim 17,
After step (h),
(h-1) the host processor further comprising comparing the received command processing result with the command list and checking whether there are no missing commands.
In the storage control method of the mobile,
(a) the host processor receiving an instruction input from an outside of the mobile;
(b) the host processor storing instructions and data in a DP memory;
(c) the DP memory storing the command and data generating and transmitting an interrupt to a storage processor;
(d) decrypting, by the storage processor upon receipt of the interrupt, the instructions and data stored in the DP memory;
(e) performing an operation corresponding to the instruction decrypted by the storage processor;
(f) transmitting a command response to the DP memory as a result of the storage processor performing an operation corresponding to the command;
(g) the DP memory transmitting an interrupt for the received command response to the host processor; And
(h) receiving the command response from the DP memory by the host processor receiving the interrupt for the command response,
After the step (h),
(h-2) the host processor further comprising checking whether there is another command input from the outside of the mobile while the storage processor performs an operation corresponding to the command.
20. The method of claim 19,
In the step (h-2),
(h-3) if there is the other instruction, the host processor is executed again from the step (b); And
(h-4) if there is no other command, the host processor further comprising the step of terminating the command processing.
delete

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