KR102415995B1 - Image processor and display device - Google Patents

Abstract

According to the present invention, the host processing device may manage the arithmetic processing of the image processing unit in units of a plurality of command programs, rather than in units of each command program. That is, according to the present invention, when the host processing device transmits an operation command set including a plurality of command programs to the image processing unit, the image processing unit manages the host processing device until the operation according to all of the plurality of command programs is completed. is not received, the frequency with which the host processing device participates in the arithmetic processing of the image processing unit is reduced, and thus the load on the host processing device is reduced, so that efficient management may be possible.

Description

Image processing device and display device including same {IMAGE PROCESSOR AND DISPLAY DEVICE}

The present invention relates to an image processing apparatus capable of efficient operation management and a display apparatus including the same.

Recently, various flat panel displays (FPDs) capable of reducing weight and volume, which are disadvantages of cathode ray tubes, have been developed. Such flat panel displays include a liquid crystal display (hereinafter referred to as "LCD"), a field emission display (FED), a plasma display panel (hereinafter referred to as "PDP"), and an organic There are an organic light emitting display device and an electroluminescence device.

Among them, in particular, a liquid crystal display device and an organic light emitting display device are in the spotlight.

These display devices are provided with an image processing device for data processing.

The conventional image processing apparatus is managed by the host processing apparatus, and since it must receive a command from the host processing apparatus every time the corresponding image processing apparatus is operated, there is a problem in that the load on the host processing apparatus is increased.

In particular, since the host processing device is also involved in the control and management of processing devices other than the sub processing device, the load on the host processing device is further increased, making it difficult to efficiently manage the image processing device.

SUMMARY OF THE INVENTION The present invention aims to solve the above and other problems.

Another object of the present invention is to provide an image processing apparatus capable of efficient operation management and a display apparatus including the same.

The image processing apparatus includes a control core that receives an operation instruction set including an operation start command and a plurality of instruction programs and is driven by the operation start instruction to fill the operation memory with the plurality of instruction programs included in the operation instruction set; and an operation core that sequentially performs operations according to the plurality of instruction programs stored in an operation memory. Accordingly, according to the present invention, when the host processing device transmits an operation command set including a plurality of command programs to the image processing unit, the image processing unit manages the host processing apparatus until the operation according to all of the plurality of command programs is completed. is not received, the frequency with which the host processing device participates in the arithmetic processing of the image processing unit is reduced, and thus the load on the host processing device is reduced, so that efficient management may be possible.

Since the display device includes the image processing device, the load on the host processing device is reduced, so that overall management of the display device can be optimized through efficient management.

Effects of the image processing apparatus and the display apparatus including the same according to the present invention will be described as follows.

According to at least one of the embodiments of the present invention, since calculations according to a plurality of command programs included in a calculation command set provided from the host processing device may be collectively processed by the image processing unit, the load on the host processing device is reduced for efficient management The advantage is that it is possible to

According to at least one of the embodiments of the present invention, since the bit indicating the end of each instruction group is allocated to the arithmetic core, there is an advantage in that the end of each instruction group can be easily confirmed through these bits.

Further scope of applicability of the present invention will become apparent from the following detailed description. However, it should be understood that the detailed description and specific embodiments such as preferred embodiments of the present invention are given by way of example only, since various changes and modifications within the spirit and scope of the present invention may be clearly understood by those skilled in the art.

1 is a block diagram illustrating a display device according to the present invention.
FIG. 2 is a block diagram illustrating the image processing unit of FIG. 1 in detail.
FIG. 3 is a block diagram illustrating the operation core of FIG. 2 in detail.
4 is a flowchart illustrating an operation process of the image processing unit of FIG. 1 .
5 is a flowchart illustrating an operation process according to a control mode and an operation mode.
6 is a schematic diagram illustrating an operation process according to a control mode and an operation mode.
7 is a schematic diagram showing a state in which a corresponding command is stored in a control memory and an arithmetic memory.
8 shows data having a size of m*n.
9 is a graph showing a comparison of the processing times of the conventional and the present invention.
FIG. 10 is a timing diagram of an arithmetic process of the image processing unit of FIG. 1 .

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numbers regardless of reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "part" for components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have distinct meanings or roles by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in this specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical idea disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

1 is a block diagram illustrating a display device according to the present invention.

Referring to FIG. 1 , a display device according to the present invention includes a host processing device 10 , an image processing unit 30 , a timing controller 40 , a gate driver 50 , a data driver 60 , and a display panel 70 . may include

The host processing device 10 may manage the image processing unit 30 and the timing controller 40 through the bus line 20 .

The display device may further include additional components other than the above-mentioned components.

The host processing device 10 may overall manage the display device. That is, the image processing unit 30 , the timing controller 40 , or other components may be managed by the host processing device 10 .

The timing controller 40 includes gate control signals (GST, On_CLK, and OFF_CLK) and data control signals (SSP, SSC, SOE, POL, etc.) based on the timing control signals (Vsync, Hsync, DE, DCLK, etc.) inputted from the outside. ) can be created.

The image processing unit 30 may process an RGB image signal input from the outside to be suitable for display on the display panel 70 .

The gate driver 50 may generate a gate signal Vg to be sequentially supplied to the display panel 70 in response to the gate control signals GST, On_CLK, and OFF_CLK provided from the timing controller 40 .

The data driver 60 may convert a data voltage corresponding to the image signal provided from the image processing unit 30 according to the data control signal provided from the timing controller 40 .

The display panel 70 may include a lower substrate, an upper substrate, and a liquid crystal layer formed between the substrates.

A plurality of pixels P may be defined by crossing the plurality of gate lines GL and the plurality of data lines DL on the lower substrate. Each pixel P may include a thin film transistor TFT connected to the gate line GL and the data line DL and a pixel electrode connected to the thin film transistor TFT.

A color filter formed to correspond to each pixel P and a black matrix for separating the color filters are formed on the upper substrate. The color filter may be disposed on the lower substrate, but is not limited thereto.

Meanwhile, a common electrode for supplying a common voltage may be formed on any one of the lower substrate and the upper substrate. For example, the common electrode is formed on the upper substrate when the display panel 70 is driven in a vertical electric field method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (In Plane Switching) mode. When driven by a horizontal electric field method such as Fringe Field Switching mode, it may be formed on the lower substrate together with the pixel electrode.

Accordingly, the pixels P connected to the corresponding gate line of the display panel 70 are selected in response to the gate signal provided from the gate driver 50 , and the data voltage provided from the data driver 60 is applied to the corresponding gate line of the display panel 70 . By being applied to the pixels P connected to the gate line, the light transmittance of the liquid crystal layer is adjusted according to the corresponding data voltage, so that an image can be displayed on the display panel 70 .

According to the present invention, the host processing device 10 may manage the arithmetic processing of the image processing unit 30 in units of a plurality of command programs, rather than in units of each command program. That is, according to the present invention, when the host processing device 10 transmits an operation command set including a plurality of command programs to the image processing unit 30 , the image processing unit 30 performs an operation according to all of the plurality of command programs. Since it is not managed by the host processing device 10 until completion, the frequency with which the host processing device 10 participates in the arithmetic processing of the image processing unit 30 is reduced, thereby reducing the load on the host processing device 10 for efficient management may be possible

The image processing unit 30 of the present invention is not run under the management of the host processing device 10 every time, but when it receives an operation command set from the host processing device 10, a plurality of command programs included in the operation command set By sequentially performing the respective operations, the image processing apparatus may perform operations according to each of the plurality of command programs by itself without being managed by the host processing apparatus 10 .

As such, the image processing unit 30 of the present invention that performs calculations by itself may be a self-run operation processor.

The self-driven operation processor may mean to control acquisition of data used for operation and the start and end of a command program within the image processing unit 30 by itself. This self-driving operation may be managed and/or controlled by the control core 110 shown in FIG. 2 .

The instruction program may consist of a plurality of instruction sets, but is not limited thereto.

The operation instruction set may include an operation start instruction, information on the number of repetitions, a plurality of instruction programs, variables, and the like.

The variable may be, for example, a threshold voltage compensation value, a luminance compensation value, etc. in the case of an organic light emitting display device, but is not limited thereto.

The number of repetitions may be the number of instruction programs to be arithmetic and processed in the arithmetic core 130 under the control of the control core 110 in the relationship between the control core 110 and the arithmetic core 130 .

For example, when there are three command programs, the number of repetitions may be three. For example, the three instruction programs are referred to as first to third instruction programs, respectively. In this case, operations according to the first to third instruction programs may be performed until the number of repetitions corresponds to 3 times.

FIG. 2 is a block diagram illustrating the image processing unit of FIG. 1 in detail.

Referring to FIG. 2 , the image processing unit 30 may include a control core 110 , a control memory 120 , an operation core 130 , and an operation memory 140 .

Here, the control memory 120 and the operation memory 140 may be referred to as first and second memories, respectively.

The control core 110 may be designed as an ISA (Instruction Set Architecture) independent of the operation core 130 .

The ISA of the control core 110 may be composed of simple arithmetic and program flow control or an instruction to manage or operate the arithmetic core 130 .

Conventionally, the operation core has been directly managed by the host processing unit, and has been managed by the host processing unit for each operation of the instruction groups included in each instruction program in the operation core. Accordingly, there is a problem in that the host processing device must be involved in the calculation of the computation core every time, and thus the load of the host processing device is increased.

In contrast, in the present invention, the operation core 130 is managed and/or controlled by the control core 110 that has received, for example, an operation start command from the host processing device 10 .

The operation start instruction may be included in the above-described operation instruction set.

The control core 110 may receive the arithmetic instruction set provided from the host processing device 10 , and set the environment to enable the arithmetic operation of the arithmetic core 130 based on the arithmetic instruction set.

In this environment setting, variables included in the operation instruction set and used for operation may be initialized, and variables stored in the control memory 120 and a plurality of instruction programs may be filled or transferred to the operation memory 140 .

The control core 110 may take out variables and a plurality of command programs from the control memory 120 and fill them in the operation memory 140 .

The control memory 120 may be connected to the control core 110 and store a set of operation instructions received from the host processing device 10 under the control of the control core 110 .

In the present invention, the control memory 120 and the operation memory 140 are divided, the control memory 120 stores the operation instruction set under the control of the control core 110 , and the operation memory 140 is the control core 110 . Efficient memory management is possible because the operation instruction set stored in the control memory 120, specifically, variables or a plurality of instruction programs is filled under the control of .

When the operation core 130 receives the number of repetitions of the operation instruction program together with the operation start instruction from the control core 110 , the operation core 130 may perform an operation to which the variable included in the operation instruction set is applied according to the corresponding instruction program. The operation core 130 may perform operations according to a plurality of different programs stored in the operation memory 140 until the number of repetitions is reached.

FIG. 3 is a block diagram illustrating the operation core of FIG. 2 in detail.

Referring to FIG. 3 , the operation core 130 may include a register file 132 and a plurality of functional units 134 , 136 , and 138 .

The register file 132 may receive a corresponding instruction program, decipher what kind of operation the corresponding program is instructed to perform, and transmit the decrypted instruction to the corresponding functional units 134 , 136 , and 138 .

The corresponding functional units 134 , 136 , and 138 may perform an operation according to an instruction transmitted from the register file 132 .

The plurality of functional units 134 , 136 , and 138 may simultaneously perform operations during one clock.

As described above, the computation core 130 capable of simultaneously performing computations by the plurality of functional units 134 , 136 , and 138 may be referred to as a computation core having a very long instruction word (VLIW) structure.

Hereinafter, an operation process of the image processing unit 30 will be described in detail with reference to FIG. 4 .

4 is a flowchart illustrating an operation process of the image processing unit of FIG. 1 .

Referring to FIG. 4 , the control core 110 receives an operation instruction set from the host processing device 10 ( S211 ).

The control core 110 stores the received arithmetic instruction set in the control memory 120 (S213).

The operation instruction set may include an operation start instruction, information on the number of repetitions, a plurality of instruction programs, variables, and the like. Accordingly, an operation start command, repetition number information, a plurality of command programs, variables, and the like may be stored in the control memory 120 .

The control core 110 may store the variables stored in the control memory 120 and a plurality of operation command programs in the operation memory 140 ( S215 ).

When the corresponding variable and the operation command program are stored in the operation memory 140 , the control core 110 may transmit an operation start command to the operation core 130 ( S217 ).

At this time, information on the number of repetitions to be calculated stored in the control memory 120 may also be transmitted to the operation core 130 .

The arithmetic core 130 may be driven by an arithmetic start command. In this case, the control core 110 may be stopped from driving.

When the operation core 130 is driven, the operation core 130 may sequentially perform operations according to a plurality of instruction programs on the image signal based on the variables stored in the operation memory 140 ( S219 ).

For example, when the variable is the threshold voltage compensation value of the organic light emitting diode display, the threshold voltage compensation values for each pixel may be different from each other. In the organic light emitting diode display, the threshold voltages of each pixel may be different from each other due to manufacturing problems. Accordingly, the threshold voltage compensation values of each pixel may be different from each other in order to make the luminance uniform in the display devices having different threshold voltages.

For example, the first to third threshold voltages may be 3.13V, 3.32V, and 3.3V, respectively. In order to match the current flowing through each pixel to the threshold voltage of 3.13V for luminance uniformity, the first to third threshold voltage compensation values may be set to 0V, 0.19V, and 017V, respectively, as variables.

Here, one command program may be a command to process an operation on the compensation data of all pixels of the display device, but is not limited thereto.

When the operation according to the plurality of instruction programs is performed during the corresponding repetition number, the operation core 130 notifies the control core 110 that the operation is finished ( S223 ).

In this way, since the operation core 130 informs the control core 110 that the operation is finished, the control core 110 can take a follow-up action.

The control core 110 may be activated by a notification indicating that the operation is finished. Thereafter, the control core 110 may check whether there is another set of arithmetic commands to be received from the host processing device 10 ( S225 ).

If another arithmetic instruction set is transmitted from the host processing device 10 to the control core 110 , the above-described processes S211 to S223 may be performed.

If another set of arithmetic instructions is not transmitted from the host processing device 10 to the control core 110 , it waits until another set of arithmetic instructions is transmitted from the host processing device 10 or another set of arithmetic commands for a predetermined time. If the set is not transmitted, the operation of the image processing unit 30 may be stopped and the image processing unit 30 may be in an inactive state.

5 is a flowchart illustrating an operation process according to a control mode and an operation mode.

The control mode may be a state in which a control code is driven or activated, and the operation mode may be a state in which the operation core 130 is driven or activated.

In the present invention, the description is limited to the case where the first to third instruction programs are included in the operation instruction set, but the present invention is not limited thereto.

Referring to FIG. 5 , in the control mode, the control core 110 may transmit the execution of the first command program to the operation core 130 ( S311 ).

The operation core 130 may receive an operation start command along with the number of repetitions from the control core 110 .

The operation mode can be switched from the control mode to the operation mode by the operation start command. That is, the operation of the control core 110 may be stopped and the operation of the operation core 130 may be activated.

In the operation mode, the operation core 130 may take out the first instruction program and variables stored in the operation memory 140 and perform an operation according to the first instruction program on the image signal based on the variables (S313).

When the operation according to the first command program is performed, ACK information indicating that the first command program has been executed may be transmitted to the control core 110 ( S315 ).

Accordingly, the operation mode is switched to the control mode, the operation of the operation core 130 may be stopped and the operation of the control core 110 may be activated.

In the control mode, the control code may transmit the execution of the second command program to the operation core 130 (S317).

The operation core 130 may receive an operation start command along with the number of repetitions from the control core 110 .

The operation mode can be switched from the control mode to the operation mode by the operation start command. That is, the operation of the control core 110 may be stopped and the operation of the operation core 130 may be activated.

In the operation mode, the operation core 130 may take out the second instruction program and variables stored in the operation memory 140 and perform an operation according to the second instruction program on the image signal based on the variables ( S319 ).

When the operation according to the second command program is performed, ACK information indicating that the second command program has been executed may be transmitted to the control core 110 (S321).

Accordingly, the operation mode is switched to the control mode, the operation of the operation core 130 may be stopped and the operation of the control core 110 may be activated.

In the control mode, the control code may transmit the execution of the third command program to the operation core 130 (S323).

The operation core 130 may receive an operation start command along with the number of repetitions from the control core 110 .

The operation mode can be switched from the control mode to the operation mode by the operation start command. That is, the operation of the control core 110 may be stopped and the operation of the operation core 130 may be activated.

In the operation mode, the operation core 130 may take out the third instruction program and variables stored in the operation memory 140 and perform an operation according to the third instruction program on the image signal based on the variables ( S325 ).

When the operation according to the third command program is performed, the operation core 130 may check whether the operation is performed as many times as the number of repetitions transmitted from the control core 110 ( S327 ).

If the operation is not performed by the number of iterations, ACK information indicating that the third command program has been executed is transmitted to the control core 110, and then the process of performing the operation according to another command program may be performed (S331).

If the operation is performed by the number of repetitions, it may be notified to the operation core 130 that the operation according to the plurality of instruction programs has been completed for the number of repetitions (S329).

As described above, according to the present invention, since calculations according to a plurality of command programs included in the calculation command set provided from the host processing device 10 can be collectively processed by the image processing unit 30 , the host processing device 10 ), it is possible to efficiently manage it by reducing the load.

6 is a schematic diagram illustrating an operation process according to a control mode and an operation mode.

As shown in FIG. 6 , in the control mode, the control code fills the operation memory 140 with a plurality of instruction programs included in the operation instruction set (Fill VLIW), and executes the first instruction program in the operation core 130 . It can be requested (Scalar Program 1 and Run VLIW).

By such a request, the control mode can be switched to the operation mode. In the operation mode, the operation core 130 may perform operations according to a plurality of instructions (VLIW Routine 1, VLIW Routine 2, ..., VLIW Routine N) included in the first instruction program.

When the operation according to the first instruction program is performed, the operation mode is switched to the control mode, and execution of the second instruction program may be requested from the operation core 130 in the control mode (Scalar Program 2).

Although the subsequent process is not shown, the control mode may be switched to the operation mode by such a request. In the operation mode, the operation core 130 may perform operations according to a plurality of instructions included in the second instruction program.

As described above, the control mode and the operation mode may be alternately and repeatedly switched while the operation is performed by the number of repetitions transferred from the control core 110 to the operation core 130 .

7 is a schematic diagram showing a state in which a corresponding command is stored in the control memory and the operation memory 140 .

For example, as shown in FIG. 7A , a plurality of command programs may be sequentially stored in the control memory 120 in one direction.

For example, each of the plurality of commands Inst 0 to Inst 3M-1 included in the first command program VLIW Program 1 may be sequentially stored in the control memory 120 from an upper direction to a lower direction.

A plurality of commands (Inst 0 to Inst 5M) included in the second command program (VLIW Program 2) from the area where the plurality of commands (Inst 0 to Inst 3M-1) included in the first command program (VLIW Program 1) are stored -1) may be sequentially stored in the control memory 120 from an upper direction to a lower direction.

At this time, the number of the plurality of commands (Inst 0 to Inst 3M-1) included in the first command program (VLIW Program 1) and the plurality of commands (Inst 0 to Inst 3M) included in the second command program (VLIW Program 2) The number of -1) may be different from each other.

As described above, the first and second command programs VLIW Program 1 and VLIW Program 2 stored in the control memory 120 may be filled in the operation memory 140 .

For example, as shown in FIG. 7B , the first and second instruction programs VLIW Program 1 and VLIW Program 2 are stored in a first direction, for example, a vertical direction, of the operation memory 140 , whereas the first and second instruction programs VLIW Program 1 and VLIW Program 2 are stored in the vertical direction. The commands Inst 0 to Inst 3M-1 and Inst 0 to Inst 5M-1 included in each of the two command programs VLIW Program 1 and VLIW Program 2 correspond to the second direction of the operation memory 140 , for example, the horizontal direction. may be stored according to, but is not limited thereto.

For example, the bit width of the control memory 120 and the bit width of the operation memory 140 excluding the End of a VLIW Program (EVP) may have an integer multiple or a real multiple relationship.

Here, the EVP may be a bit for indicating the end of the corresponding command program. EPV may be '0' or '1'. When EVP is '0', it may indicate that the corresponding command program is not the end, and when EVP is '1', it may indicate that the corresponding command program is finished.

For example, three command groups (Inst 0 to Inst M-1, Inst M to Inst 2M-1, Inst 2M to Inst 3M-1) are included in the first command program (VLIW Program 1) stored in the operation memory 140 . can In this case, the EVP of the first command group (Inst 0 to Inst M-1) may be represented by '0', and the EVP of the second command group (Inst M to Inst 2M-1) may be represented by '0'. may be, and the third command group (Inst 2M to Inst 3M-1) may be represented by '1'.

Similarly, in the second command program (VLIW Program 2) stored in the operation memory 140, five command groups (Inst 0 to Inst M-1, Inst M to Inst 2M-1, Inst 2M to Inst 3M-1, Inst 3M) to Inst 4M-1, Inst 4M to Inst 5M-1) are included, only the fifth command group (Inst 4M to Inst 5M-1) has an EVP of '1' and the first to fourth command groups (Inst 0 to Inst M-1, Inst M to Inst 2M-1, Inst 2M to Inst 3M-1, Inst 3M to Inst 4M-1) may have an EVP of '0'.

As described above, since the bit indicating the end of each instruction group is allocated to the operation core 130, it can be easily confirmed that it is the end of each instruction group through these bits.

8 shows data having a size of m*n.

The total calculation time of the prior art and the present invention will be described with reference to FIG. 8 .

As shown in FIG. 8 , it is assumed that compensation data of all pixels of the display device has data of size m*n.

In this case, the total processing time (Ttotal) required to process the compensation data of all pixels of the display device in the prior art and in the present invention is as follows.

Conventional:

[Equation 1]

Ttotal = n×((m×tp)+(m×thi)) --- (Equation 1)

Invention:

[Equation 2]

Ttotal = n×((m×tp)+(m×tsi)+thi)---(Equation 2)

However, tsi < thi

m: number of columns

n: number of rows

tp: processing time of one pixel data

thi: time spent handling interrupt service routines on host processing unit 10 and bus line 20

tsi: time to control the iterative flow in the computation core 130

As shown in FIG. 10 , the host processing device 10 may generate one operation instruction set in response to an interrupt pulse.

The host processing device 10 may transmit an operation command set from the host processing device 10 to the image processing unit 30 via the bus line 20 in response to an interrupt service routine (ISR) pulse.

Accordingly, the time between the interrupt pulse and the ISR pulse, that is, the time taken for handling the interrupt service routine in the host processing unit 10 and the bus line 20 may be thi.

The image processing unit 30 may process all of the operation command sets transmitted from the host processing device 10 before the next interrupt pulse is generated.

As described above, the operation instruction set may include a plurality of instruction programs.

A number of repeating pulses can be generated between the ISR pulse and the next interrupt pulse.

During each repetition pulse, each command program can be processed. Accordingly, it may represent the time tsi for controlling the iterative flow in the computation core 130 during each repetition pulse.

Whereas the time taken to process all of the pixels on one line is the time multiplied by m times the time taken for handling the interrupt service routine in the host processing unit 10 and the bus line 20 (thi) in the prior art , in the present invention, the time (ti) for controlling the iterative flow in the operation core 130, that is, the time multiplied by m times during the repetition pulse in the host processing unit 10 and the bus line 20 It is the time plus the time required for handling the interrupt service routine (thi). Accordingly, the time it takes to process all the pixels on one line is significantly reduced in the present invention compared to the related art.

For convenience of explanation, the total processing time (Ttotal) required to process the compensation data of all pixels of the conventional display device and the present invention by substituting a number is as follows.

For example, let m be 10, n is 10, tp is 1 μs, thi is 20 μs, and tsi is 10 μs.

Then, the total processing time (Ttotal) required to process the compensation data of all pixels of the conventional display device is 10×((10×1)+(10×20))=10×(10+200)=2,100 μs= 2.1 ms.

In contrast, the total processing time Ttotal required to process the compensation data of all pixels of the conventional display device is 10×((10×1)+(10×10)+20)=10×(10+120)= 1,300 μs = 1.3 ms.

Accordingly, the total processing time (Ttotal) required to process the compensation data of all pixels of the display device can be reduced by 61.9% in the present invention compared to the related art, thereby enabling faster operation.

9 is a graph showing a comparison of the processing times of the conventional and the present invention.

As shown in FIG. 9A , as the time thi required for handling the interrupt service routine in the host processing device 10 and the bus line 20 increases, the compensation data of all pixels of the display device is stored. It can be seen that the total processing time (Ttotal) required for processing is conventionally increased, but in the present invention, the almost constant time is maintained and the processing time is significantly reduced compared to the conventional one.

That is, in the prior art, each time each command program is processed, the time required for handling the interrupt service routine in the host processing unit 10 and the bus line 20 (thi) is required, so the clock cycle of thi is increased. Accordingly, the total computation time increases linearly.

In contrast, in the present invention, since one ISR pulse is generated to process a plurality of command programs, the increase in the clock cycle of thi is meaningless and the interrupt service routine in the host processing unit 10 and the bus line 20 is handled. The time taken (thi) to handle is only needed once.

As shown in FIG. 9B , as the time tsi for controlling the iterative flow in the arithmetic core 130 increases, the total processing time Ttotal required to process the compensation data of all pixels of the display device is constant in the prior art. On the other hand, in the present invention, it becomes large. Nevertheless, the total computation time in the present invention is much smaller than the conventional total computation time.

That is, in the related art, since each command program is managed by the host processing device 10, there is no time tsi for controlling the repetition pulse as in the present invention. Accordingly, in the conventional case, the total processing time Ttotal required for the value calculated by Equation 1 to process the compensation data of all pixels of the display device may be constant regardless of the variation of tsi.

On the other hand, since tsi is a repetitive pulse period, if the clock cycle of tsi increases, that is, the number of half-width pulses increases, the total processing time (Ttotal) required to process the compensation data of all pixels of the display device by the number of repetition pulses increases. will increase

In the present invention, although the total processing time (Ttotal) required to process the compensation data of all pixels of the display device increases as tsi increases, the total processing time (Ttotal) is smaller than that of the related art.

The above detailed description should not be construed as restrictive in all respects and should be considered as illustrative. The scope of the present invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the present invention are included in the scope of the present invention.

10: host processing unit
20: bus line
30: image processing unit
40: timing controller
50: gate driver
60: data driver
70: display panel
110: control core
120: control memory
130: compute core
140: operation memory

Claims (9)

a control core that receives an operation instruction set including an operation start instruction and a plurality of instruction programs, and is driven by the operation start instruction to fill the operation memory with the plurality of instruction programs included in the operation instruction set; and
Comprising a arithmetic core that sequentially performs operations according to the plurality of instruction programs stored in the arithmetic memory,
The image processing apparatus is switched to a arithmetic mode in which the arithmetic core is activated while the operation according to each command program is performed, and is switched to a control mode in which the control core is activated during other sections. According to claim 1,
The operation instruction set further includes iteration number information and variables,
The control core is
The image processing apparatus stores the iteration count information and variables together with the plurality of command programs in a control memory, and stores the variables together with the plurality of command programs in an arithmetic memory. 3. The method of claim 2,
The control core is
sending the operation start command to the operation core;
The operation core is driven by the operation start instruction,
The computational core is
An image processing apparatus for sequentially performing operations according to the plurality of command programs based on the variables stored in the operation memory. 4. The method of claim 3,
The computational core is
When the operation according to the plurality of command programs is finished, the image processing apparatus notifies the control core that the operation is finished. 5. The method of claim 4,
The computational core is
An image processing apparatus for determining whether an operation according to the plurality of command programs has been completed based on the number of repetitions information. According to claim 1,
Each command program includes a plurality of command groups,
An image processing apparatus to which a bit indicating that a last command group among a plurality of command groups stored in the operation memory is an end of a corresponding command program is allocated. delete According to claim 1,
An image processing apparatus in which the control mode and the operation mode are alternately switched while the operation according to the plurality of command programs is being performed. a host processing unit for generating an operation instruction set including an operation start instruction and a plurality of instruction programs;
A control core that receives the operation instruction set from the host processing unit, is driven by the operation start instruction, and fills the operation memory with the plurality of instruction programs included in the operation instruction set, and the plurality of instruction programs stored in the operation memory an image processing unit including an arithmetic core that sequentially performs an operation according to ; and
and a display panel for displaying the calculated image signal;
The image processing unit is switched to a arithmetic mode in which the arithmetic core is activated while the operation according to each command program is performed, and is switched to a control mode in which the control core is activated during other sections.

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