KR101747728B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of reducing a kickback voltage to improve image quality, and more particularly, to a liquid crystal display device including a plurality of gate lines sequentially driven; A plurality of pixels connected in common to the data lines and sequentially supplied with gate signals from the two gate lines; The nth (n is a natural number) pixel includes: a first switching device for switching an (n-m) -th data signal from the data line in response to an (n-m) th gate signal from an n-mth gate line (m is a natural number smaller than n); a second switching device for switching an n-th data signal from the data line in response to an n-th gate signal from an n-th gate line; And a liquid crystal cell receiving the n-mth data signal from the first switching device and the n-th data signal from the second switching device in order and displaying an image.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of reducing the variation of a pixel voltage according to a kickback voltage to improve image quality.

The pixel voltage charged in the pixel of the liquid crystal display device fluctuates in accordance with the change of the gate signal. That is, the pixel voltage fluctuates in synchronization with the moment when the gate signal falls from the high voltage to the low voltage. The variation of the pixel voltage is referred to as a kickback voltage. When the pixel voltage is a positive polarity voltage by the positive polarity data signal, the pixel voltage is reduced by the kickback voltage. When the pixel voltage is a negative polarity voltage by the negative polarity data signal, . As a result, there is a problem that image quality variation between pixels increases according to the polarity of a data signal, thereby lowering the image quality.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a liquid crystal display device capable of reducing a variation of a pixel voltage by minimizing a size of a kickback voltage, .

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a plurality of gate lines sequentially driven; A plurality of pixels connected in common to the data lines and sequentially supplied with gate signals from the two gate lines; The nth (n is a natural number) pixel includes: a first switching device for switching an (n-m) -th data signal from the data line in response to an (n-m) th gate signal from an n-mth gate line (m is a natural number smaller than n); a second switching device for switching an n-th data signal from the data line in response to an n-th gate signal from an n-th gate line; And a liquid crystal cell receiving the n-mth data signal from the first switching device and the n-th data signal from the second switching device in order and displaying an image.

The n-mth gate signal is output before the nth gate signal; And the pulse width of the n-mth gate signal and the pulse width of the nth gate signal are overlapped.

And the size of the second switching element is smaller than the size of the first switching element.

And the channel width of the second switching element is smaller than the channel width of the first switching element.

And m is one of 1 and 2.

And a connection line connecting the gate electrode of the first switching element and the n-mth gate line; And the connection line is located outside the pixel.

And a connection line connecting the gate electrode of the first switching device and the n-mth gate line;

And the connection line is located inside the pixel.

According to another aspect of the present invention, there is provided a liquid crystal display device including: a plurality of pixels commonly connected to a data line and individually connected to each of a plurality of gate lines; And a gate driver sequentially supplying the pre-charge gate signal and the present charge gate signal to each gate line; The preliminary charging gate signal and the present charging gate signal are sequentially supplied to one gate line within one frame period; the main charging gate signal supplied to the n-th (n is a natural number) gate line and the main charging gate signal supplied to the n-mth (m is a natural number smaller than n) gate line are outputted in the same period; the main charging gate signal supplied to the nth gate line and the precharging gate signal supplied to the (n + m) th gate line are outputted in the same period; And the amplitude of the present charging gate signal is smaller than the amplitude of the precharging gate signal.

the polarity of the data signal supplied by the n-th pixel connected to the n-th gate line by the pre-charge gate signal is the same as the polarity of the data signal supplied by the present charging gate signal.

And m is 2.

The liquid crystal display device according to the present invention has the following effects.

First, the size of the kickback voltage can be reduced by sequentially supplying gate signals to the pixels through the first and second switching elements having different sizes.

Second, the size of the kickback voltage can be reduced by driving the pixels using the pre-charge gate signal and the present charge gate signal having different amplitudes and sequentially output.

1 is a view illustrating a liquid crystal display device according to a first embodiment of the present invention;
2 is a diagram showing gate signals supplied to three gate lines shown in FIG. 1 and data signals supplied to any one of the data lines
3 is a view showing a configuration of several pixels shown in Fig. 1
4 is a detailed configuration diagram of a liquid crystal cell included in the n-th pixel of Fig. 3
FIG. 5 is a graph showing a change in the magnitude of a pixel voltage according to the (n-1) -th gate signal and the (n-1) -th gate signal supplied to the n-
6 is a graph showing a change in the magnitude of a pixel voltage according to the (n-1) -th data signal and the (n-1) -th data signal supplied to the n-th pixel,
7 is a view showing still another configuration of several pixels shown in Fig. 1
8 is a view illustrating a liquid crystal display device according to a second embodiment of the present invention
9 is a diagram showing gate signals supplied to any three gate lines of FIG. 8 and data signals supplied to any one of the data lines
10 is a view showing a configuration of several pixels shown in Fig. 8
11 is a detailed configuration diagram of the liquid crystal cell provided in the n-th pixel in Fig. 10
12 is a diagram showing a magnitude variation of the pixel voltage according to the precharge gate signal and the main charging gate signal of the n-th gate signal supplied to the n-th pixel

FIG. 1 is a view illustrating a liquid crystal display according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating gate signals supplied to three gate lines shown in FIG. 1 and a data signal supplied to one of the data lines Fig.

The display device according to the first embodiment of the present invention includes a display panel (DSP), a data driver (DD), a gate driver (GD), and a timing controller, as shown in Fig.

The display panel DSP includes i * j pixels (PXLs) for displaying an image and i (i is a natural number) gate lines GL1 to GLi connected to these pixels and j (j is a natural number) And data lines DL1 to DLn. The j pixels arranged in the horizontal direction are commonly connected to two gate lines, and the i pixels arranged in the vertical direction are connected in common to one data line. The i * j pixels PXL are divided into a plurality of red pixels for displaying a red image, a plurality of green pixels for displaying a green image, and a plurality of blue pixels for displaying a blue image . The red pixels, the green pixels, and the blue pixels are arranged in a matrix form on the display unit.

On the other hand, the j pixels arranged in the first horizontal lines are connected to the first gate line and the dummy gate line.

The data driver (DD) supplies image data for displaying an image to j data lines. The data driver DD converts the red, green, and blue image data supplied from the timing controller TC into an analog signal and outputs it to j data lines. That is, the data driver DD converts the red, green, and blue image data corresponding to the pixels (j pixels) of one horizontal line driven by the gate driver GD into an analog signal, And simultaneously supplies image data of one horizontal line to j data lines DL1 to DLj during one horizontal period 1H. Each pixel displays an image by image data from the data line to which it is connected.

The polarity of the data signal Vd (m) supplied to one data line is inverted every horizontal period as shown in Fig.

The gate driver GD sequentially drives i gate lines GL1 through GLi in one frame period to sequentially transfer j pixels to j data lines DL1 through DLj every horizontal period in which each gate line is driven Respectively. To this end, the gate driver sequentially supplies gate signals to each gate line. 2 shows the gate signals Vg (n-1), Vg (n), and Vg (n + 1) supplied to three gate lines, . For example, as shown in FIG. 2, the pulse width of the (n-1) th gate signal Vg (n-1) supplied to the (n-1) (Vg (n)) is superposed for a predetermined period. As another embodiment, these gate signals may be output without being overlapped.

The timing controller TC rearranges the red, green, and blue image data supplied from the system and supplies them to the data driver in timing. The timing controller TC generates a gate control signal, a data control signal, and an operation control signal using a dot clock, a horizontal synchronization signal, and a vertical synchronization signal supplied from the system. The timing controller TC controls the operation of the gate driver GD using the gate control signal and the operation of the data driver DD using the data control signal.

Here, the configuration of the pixel PXL will be described in more detail as follows.

FIG. 3 is a diagram illustrating a configuration of several pixels shown in FIG. 1. Referring to FIG.

In FIG. 3, four pixels are shown, and since all pixels have the same structure, any one pixel will be exemplarily described.

Any one n-th pixel PXL (n) includes a first switching device TFT1, a second switching device TFT2 and a liquid crystal cell LC, as shown in Fig.

the first switching element TFT1 provided in the nth pixel PXL (n) is connected to the (n-1) th gate signal Vg (n-1) from the (n-1) 1) -th data signal from the m-th data line DL (m) in response to the n-th data line DL (m). The gate electrode of the first switching element TFT1 is connected to the (n-1) -th gate line GL (n-1) through a connection line, which is located inside the pixel.

the second switching element TFT2 provided in the n-th pixel PXL (n) is turned on in response to the n-th gate signal Vg (n) from the n-th gate line GL (n) DL (m)).

Here, the size of the second switching device TFT2 is smaller than that of the first switching device TFT1. That is, the channel width of the second switching element TFT2 is smaller than the channel width of the first switching element TFT1.

the liquid crystal cell LC provided in the n-th pixel PXL (n) sequentially outputs the (n-1) th data signal from the first switching device TFT1 and the n-th data signal from the second switching device TFT2 And displays an image.

4 is a detailed configuration diagram of a liquid crystal cell LC provided in the n-th pixel in FIG. As shown in Fig. 4, the liquid crystal cell LC includes a liquid crystal capacitance capacitor and a storage capacitance capacitor. A common voltage is supplied to one terminal of each of the liquid crystal capacitance capacitor and the auxiliary capacitance capacitor, and a data signal is supplied to the other terminal.

The operation of the n-th pixel will be described with reference to FIGS. 2 and 4. FIG.

When the (n-1) th gate signal Vg (n-1) is supplied to the (n-1) th gate line GL (n-1), the first switching element TFT1 is turned on. Then, the (n-1) th data signal is supplied to the liquid crystal cell LC through the turn-on first switching element TFT1. The (n-1) -th data signal is a data signal to be supplied to the (n-1) -th pixel, and the liquid crystal cell LC of the n-th pixel PXL (n) starts to be charged by the (n-1)

Thereafter, when the n-th gate signal Vg (n) is supplied to the n-th gate line GL (n), the second switching element TFT2 is turned on. Then, the n-th data signal is supplied to the liquid crystal cell LC through the turn-on second switching element TFT2. The n-th data signal is an actual data signal required for the n-th pixel. Accordingly, the n-th pixel displays its own image by the n-th data signal.

FIG. 5 is a diagram illustrating a magnitude variation of a pixel voltage according to an (n-1) -th gate signal and an (n-1) -th gate signal supplied to an n-th pixel.

As shown in FIG. 5, when the (n-1) th gate signal Vg (n-1) falls to the low voltage, the pixel voltage Vpx decreases due to the kickback phenomenon. n) is maintained at the high voltage (Vgh), the pixel voltage Vpx is increased again. Thereafter, when the n-th gate signal Vg (n) falls to the low voltage Vgl, the pixel voltage Vpx again decreases due to the kickback phenomenon. However, since the size of the second switching element TFT2 for supplying the n-th gate signal is smaller than that of the first switching element TFT1, the reduction amount of the pixel voltage Vpx due to the kickback phenomenon caused by the n- small. That is, the kickback voltage Vg (n) generated by the n-th gate signal Vg (n) is greater than the kickback voltage dVp1 (hereinafter referred to as the first kickback voltage) generated by the n- dVp2 (hereinafter referred to as the second kickback voltage) is smaller, the variation amount of the final pixel voltage Vpx charged in the liquid crystal cell LC is smaller than in the conventional case.

Equation (1) represents a formula for calculating the magnitude of the first kickback voltage (dVp1), and Equation (2) represents a formula for calculating the magnitude of the second kickback voltage (dVp2).

Cgs, A denotes the capacitance of the parasitic capacitor between the gate and source electrodes of the first switching element TFT1, VGH denotes the high voltage of the gate signal, VGL denotes the low voltage of the gate signal, Means the capacitance of the capacitive capacitor, and CST means the capacitance of the auxiliary capacitance capacitor. Here, Ggs and B mean the capacitance of the parasitic capacitor between the gate and the source electrode of the second switching element TFT2.

Assuming that the values of all the variables in Equations 1 and 2 are the same, the VGH-VGL value in Equation 2 becomes smaller than the VGH-VGL value in Equation 1 because the size of the second switching device TFT2 is small . Therefore, the first kickback voltage dVp1 becomes smaller than the second kickback voltage dVp2.

(N-1) -th gate signal Vg (n-1) and the (n-1) -th data signal supplied to the n- ) Is smaller than the kickback voltage generated by the n-th gate signal Vg (n).

Here, the pixel voltage Vpx means a data signal supplied to the pixel, that is, as the data signal is supplied to the pixel, the pixel voltage Vpx corresponding to the data signal is charged into the pixel.

Fig. 7 is a diagram showing another configuration of several pixels shown in Fig. 1. As shown in Fig. 7, the connection line is located outside the pixel. The remaining components are the same as those shown in Fig.

On the other hand, the gate electrode of the first switching element TFT1 provided in the nth pixel in the first embodiment may be connected to the (n-2) th gate line instead of the (n-1) th gate line. Particularly, in the liquid crystal display device of the Z-inversion drive type in which two adjacent pixels arranged in the horizontal direction are connected in common to one data line and these two pixels are connected to different gate lines, The gate electrode of the first switching element TFT1 provided in the nth pixel may be connected to the (n-2) th gate line. That is, in this Z-inversion driving method, the nth pixel can be connected to the nth gate line and the (n-2) th gate line. At this time, it is more preferable that the n-th gate line and the (n-2) th gate line are connected to pixels displaying the same color. In other words, in the Z-inversion driving method, the pixels connected to the n-th gate line and the pixels connected to the (n-2) -th gate line may all be red pixels indicating the same color, for example, red.

FIG. 8 is a diagram illustrating a liquid crystal display according to a second embodiment of the present invention. FIG. 9 shows gate signals supplied to the three gate lines shown in FIG. 8 and data signals supplied to any one of the data lines Fig.

The display device according to the second embodiment of the present invention includes a display panel (DSP), a data driver (DD), a gate driver (GD), and a timing controller, as shown in Fig.

The display panel DSP includes i * j pixels (PXLs) for displaying an image and i (i is a natural number) gate lines GL1 to GLi connected to these pixels and j (j is a natural number) And data lines DL1 to DLj. The j pixels PXL arranged in the horizontal direction are commonly connected to one gate line, and the i pixels PXL arranged in the vertical direction are connected in common to one data line. The i * j pixels PXL are divided into a plurality of red pixels for displaying a red image, a plurality of green pixels for displaying a green image, and a plurality of blue pixels for displaying a blue image . The red pixels, the green pixels, and the blue pixels are arranged in a matrix form on the display unit.

The remaining gate driver GD, data driver DD and timing controller TC are the same as those in the first embodiment described above.

However, as shown in FIG. 9, the gate driver GD according to the second embodiment of the present invention sequentially supplies the gate signals composed of the pre-charging gate signal Vg_P and the charging gate signal Vg_O sequentially Output. That is, the gate signal supplied to one gate line is composed of the pre-charging gate signal Vg_P and the main charging gate signal Vg_O sequentially outputted.

The preliminary charging gate signal Vg_P and the main charging gate signal Vg_O are sequentially supplied to one gate line within one frame period.

9 shows three gate signals Vg (n-1), Vg (n), and Vg (n + 1) Vg (n) is a gate signal supplied to the nth gate line, and Vg (n + 1) is a gate signal supplied to the (n + 1) th gate line.

the precharge gate signal Vg_P supplied to the nth gate line and the main charging gate signal Vg_O supplied to the (n-1) th gate line are outputted in the same period, and the main charging gate signal The gate signal Vg_O and the precharge gate signal Vg_P supplied to the (n + 1) th gate line are outputted in the same period.

At this time, the amplitude of the present charging gate signal (Vg_O) is smaller than the amplitude of the precharging gate signal (Vg_P).

In addition, the polarity of the data signal supplied to the n-th pixel connected to the n-th gate line by the pre-charge gate signal Vg_P is the same as the polarity of the data signal supplied by the present charging gate signal Vg_O. The remaining pixels are supplied with data signals of the same polarity when the precharge gate signal Vg_P is supplied in the same manner and when the present charge gate signal Vg_O is supplied. Thus, the charging speed of the pixel is improved.

At this time, since the amplitude of the present charging gate signal Vg_O supplied to each pixel is smaller than the amplitude of the preliminary charging gate signal Vg_P, the above-described kickback voltage can be reduced.

FIG. 10 is a diagram showing a configuration of several pixels shown in FIG. 8. FIG.

In FIG. 10, four pixels are shown, and since all pixels have the same structure, any one pixel will be exemplarily described.

One of the n-th pixel PXL (n) includes a switching element (TFT) and a liquid crystal cell LC, as shown in Fig.

the switching element TFT provided in the n-th pixel PXL (n) is connected to the precharge gate signal Vg_P of the n-th gate signal Vg (n) from the n-th gate line GL (n) Th data line DL (m) in response to the main charging gate signal Vg_O of the n-th gate signal Vg (n) Th data signal from the data line DL (m). The n-th data signal is an actual data signal required for the n-th pixel.

11 is a detailed configuration diagram of the liquid crystal cell LC provided in the n-th pixel in FIG. As shown in Fig. 11, the liquid crystal cell LC includes a liquid crystal capacitance capacitor and a storage capacitance capacitor. A common voltage is supplied to one terminal of each of the liquid crystal capacitance capacitor and the auxiliary capacitance capacitor, and a data signal is supplied to the other terminal.

12 is a diagram showing a change in the magnitude of the pixel voltage Vpx according to the precharge gate signal Vg_P and the present charge gate signal Vg_O of the n-th gate signal supplied to the n-th pixel.

As shown in FIG. 12, when the precharge gate signal Vg_P of the n-th gate signal drops to a low voltage, the pixel voltage Vpx decreases due to a kickback phenomenon, And the pixel voltage Vpx again increases as the gate signal Vg_O for the pixel increases. Thereafter, when the present charging gate signal Vg_O falls to a low voltage, the pixel voltage Vpx again decreases due to the kickback phenomenon. However, since the amplitude of the present charging gate signal Vg_O is smaller than the amplitude of the preliminary charging gate signal Vg_P, the amount of decrease in the pixel voltage Vpx due to the kickback phenomenon caused by the main charging gate signal Vg_O is small. That is, the kickback voltage generated by the charging gate signal Vg_O (hereinafter, referred to as the second kickback voltage (dVp1)) is smaller than the kickback voltage (hereinafter referred to as the first kickback voltage dVp1) generated by the precharging gate signal Vg_P dVp2) is smaller, the amount of variation of the final pixel voltage Vpx charged in the liquid crystal cell LC is smaller than in the prior art.

Here, the pixel voltage Vpx means a data signal supplied to the pixel, that is, as the data signal is supplied to the pixel, the pixel voltage Vpx corresponding to the data signal is charged into the pixel.

Equation (3) is a formula for calculating the magnitude of the first kickback voltage (dVp1), and Equation (4) is a formula for calculating the magnitude of the second kickback voltage (dVp2).

Cgs denotes the capacitance of the parasitic capacitor between the gate and source electrodes of the switching element (TFT), VGH denotes the high voltage of the gate signal, VGL denotes the low voltage of the gate signal, CLC denotes the capacitance of the liquid crystal capacitance capacitor , And CST means the capacitance of the storage capacitor. VGH1 denotes a high voltage of the precharge gate signal Vg_P, and VGH2 denotes a high voltage of the present charging gate signal Vg_O.

Assuming that the values of all the variables in Equations 3 and 4 are the same, since the amplitude of the present charging gate signal Vg_O is smaller, the value of VGH-VGL in Equation 4 is smaller than the value of VGH-VGL in Equation 3 . Therefore, the first kickback voltage dVp1 becomes smaller than the second kickback voltage dVp2.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

TFT1: first switching element TFT2: second switching element
DL (m): m-th data line DL (m + 1): m +
GL (n-1): n-1 th gate line GL (n): nth gate line GL
GL (n + 1): n + 1th gate line PXL (n): nth pixel
PXL (n + 1): n + 1 th pixel LC: liquid crystal cell
CL: connection line

Claims (10)

A plurality of gate lines sequentially driven;
A plurality of pixels connected in common to the data lines and sequentially supplied with gate signals from the two gate lines;
The n-th (n is a natural number)
th data signal from the data line in response to an n-th gate signal from the n-th gate line (m is a natural number smaller than n);
a second switching device for switching an n-th data signal from the data line in response to an n-th gate signal from an n-th gate line; And
And a liquid crystal cell for receiving an n-th data signal from the first switching device and an n-th data signal from the second switching device in order to display an image. The method according to claim 1,
The nm-th gate signal is output before the n-th gate signal;
And the pulse width of the nm-th gate signal and the pulse width of the n-th gate signal are superimposed. The method according to claim 1,
Wherein a size of the second switching element is smaller than a size of the first switching element. The method of claim 3,
And the channel width of the second switching element is smaller than the channel width of the first switching element. The method according to claim 1,
Wherein m is any one of 1 and 2. The method according to claim 1,
And a connection line connecting the gate electrode of the first switching device and the nm-th gate line;
And the connection line is located outside the pixel. The method according to claim 1,
And a connection line connecting the gate electrode of the first switching device and the nm-th gate line;
And the connection line is located inside the pixel. A plurality of pixels connected in common to the data lines and individually connected to each of the plurality of gate lines;
And a gate driver sequentially supplying the pre-charge gate signal and the present charge gate signal to each gate line;
The preliminary charging gate signal and the present charging gate signal are sequentially supplied to one gate line within one frame period;
the main charging gate signal supplied to the nth (n is a natural number) gate line and the main charging gate signal supplied to the nmth (m is a natural number smaller than n) gate line are outputted in the same period;
the main charging gate signal supplied to the nth gate line and the precharging gate signal supplied to the (n + m) th gate line are outputted in the same period;
And the amplitude of the present charging gate signal is smaller than the amplitude of the precharging gate signal. 9. The method of claim 8,
the polarity of the data signal supplied to the nth pixel connected to the nth gate line by the precharge gate signal is the same as the polarity of the data signal supplied by the present charging gate signal. 10. The method of claim 9,
And m is 2.

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