KR102391616B1 - Gate driver and touch screen integrated display device including the same - Google Patents

Abstract

The touch screen integrated display device of the present invention includes an R node charging/discharging unit, and a stage that outputs the last scan pulse in the display driving period before touch driving generates a normal output based on an auxiliary reset signal applied through the R node charging/discharging unit. can do. In addition, according to the present invention, a stage or a standby stage of a general display driving period may perform a normal output based on an output signal of the next stage and the next stage after being applied through the R node charging/discharging unit. Accordingly, according to the present invention, all stages can make a normal output during the display driving period.

Description

GATE DRIVER AND TOUCH SCREEN INTEGRATED DISPLAY DEVICE INCLUDING THE SAME

The present invention relates to a gate driving circuit and a touch screen integrated display device including the same.

Touch screen is a liquid crystal display (Liquid Crystal Display), field emission display (FED), plasma display panel (PDP), electroluminescence display (Electroluminescence Device, EL), electrophoretic display device It is a type of input device installed in an image display device, such as, etc., in which a user presses (presses or touches) a touch sensor in a touch screen while viewing the image display device to input predetermined information.

The touch screen used in the above-described display device may be divided into an add-on type, an on-cell type, and an in-cell type according to the structure thereof. The attachment type is a method of attaching the touch screen to the upper plate of the display device after manufacturing the display device and the touch screen separately. The top plate type is a method of directly forming elements constituting the touch screen on the surface of the upper glass substrate of the display device. The built-in type is a method in which a touch screen is embedded inside the display device to achieve thinness of the display device and to increase durability. However, the attachable touch screen has a problem in that the finished touch screen is mounted on the display device, and the thickness is thick, and the brightness of the display device is darkened, thereby reducing visibility. In addition, the top-panel touch screen has a structure in which a separate touch screen is formed on the upper surface of the display device, and although the thickness can be reduced compared to that of the attached type, it is still the entirety because of the driving and sensing electrodes constituting the touch screen and an insulating layer for insulating them. As the thickness increases and the number of processes increases, there is a problem in that the manufacturing price increases.

On the other hand, the integrated touch screen has the advantage of solving the problems caused by the attachable type and the top plate type touch screen in that durability and thinness can be improved. Such an integrated touch screen may be divided into an optical type and a capacitive type touch screen.

The optical touch screen is a method of forming a light sensing layer on a thin film transistor substrate array of a display device and recognizing light reflected through an object existing in a touched portion using light or infrared light from a backlight unit. However, the optical touch screen shows relatively stable driving performance when the surroundings are dark, but when the surroundings are bright, lights stronger than the reflected light act as noise. This is because the intensity of the light reflected by the actual touch is very weak, and an error may occur in touch recognition even if the outside is slightly bright. In particular, the optical touch screen has a problem in that, when the surrounding environment is exposed to sunlight, the intensity of light is so strong that the touch may not be recognized in some cases.

The capacitive touch screen may be divided into a self-capacitance type and a mutual capacitance type. The mutual capacitance type touch screen divides the common electrode and divides it into a driving electrode and a sensing electrode to form a mutual capacitance between the driving electrode and the sensing electrode, thereby reducing the amount of change in mutual capacitance that occurs during touch. A method of recognizing a touch by measuring it. However, in the mutual capacitance type touch screen, the size of the mutual capacitance generated during touch recognition is very small, whereas the parasitic capacitance between the gate line and the data line constituting the display device is very large. There is a problem that is difficult to recognize. In addition, the mutual capacitive touch sensor has a problem in that it requires a very complicated wiring structure because a plurality of touch driving lines for driving a touch and a plurality of touch sensing lines for sensing a touch must be formed on a common electrode. In order to solve this problem, recently, when a plurality of electrodes are formed in the display area of a panel, they are formed to overlap a plurality of pixel electrodes, and these electrodes are used to drive liquid crystals together with the pixel electrodes formed in each pixel during the display driving period. A split method between a display and a touch driving has been proposed, which operates as a common electrode and operates as a touch electrode that detects a touch position by a touch scan signal applied from a touch driver during a touch driving period.

In general, when the display is driven, each stage receives the signal of the next stage to reset the output of each stage. In addition, each stage receives the signal of the previous stage to start driving each stage.

However, in the case of the display and touch division driving method, there is a stage in which the Q node is held in a stand-by state among the stages constituting the shift register of the gate driving circuit during the touch driving time. Accordingly, the standby stage has no output until the display driving period. The stage that output the last scan pulse before touch driving does not reset because there is no output from the standby stage during the touch driving period, so it produces abnormal output. Furthermore, there is a problem in that the touch electrode cannot perform touch sensing because the stage outputs abnormally during the touch driving period.

In addition, when the display driving period starts after the touch driving period ends, there is a problem in that the standby stage cannot be driven because there is no output of the previous stage.

An object of the present invention is to provide a gate driving circuit in which a stage driven last before a touch driving period can output a normal output, and a touch screen integrated display device including the same.

Another object of the present invention is to provide a gate driving circuit capable of performing touch sensing by a touch electrode during a touch driving period and a touch screen-integrated display device including the same.

Another object of the present invention is to provide a gate driving circuit capable of normal driving even when there is no output from a previous stage when a display driving period starts after the touch driving period ends, and a touch screen integrated display device including the same.

Another object of the present invention is to provide a gate driving circuit capable of outputting normally in all stages during a display driving period and a touch screen integrated display device including the same.

As a means for solving the above problems, as a gate driving circuit that time-divisions one frame into a display driving section and a touch driving section, it is controlled by the output signal of the N-1 (N is a natural number) stage to supply high potential power to the Q node and the Q node charging/discharging unit for supplying low potential power to the Q node controlled by the voltage on the R node of the R node charging/discharging unit, the R node charging/discharging unit for supplying high potential power or low potential power to the R node, and the Q node and a pull-up transistor that is controlled by a voltage and outputs an applied clock signal to an N-th output stage; and an N-th stage including an R node charging/discharging unit, controlled by the output signal of the N+1-th stage to generate a high-potential power supply It is possible to provide a gate driving circuit including a first transistor for supplying to the R node, and a third transistor controlled by the output signal of the N+2th stage to supply a low potential power to the R node. Accordingly, according to the present invention, when the display driving period starts after the touch driving period ends, it is possible to drive normally even if there is no output from the previous stage. In addition, according to the present invention, all stages can make a normal output during the display driving period.

As another solution to the above problem, as a gate driving circuit for time-dividing one frame into a display driving section and a touch driving section, it is controlled by the output signal of the N-1 (N is a natural number) stage to supply high potential power to the Q node Q node charging/discharging unit supplying low potential power to Q node controlled by the voltage on R node of R node charging/discharging unit, R node charging/discharging unit supplying high potential power or low potential power to R node, and Q an N-th stage including a pull-up transistor that is controlled by a voltage on a node and outputs an applied clock signal to an N-th output terminal, wherein the N-th stage outputs a last scan pulse in a display driving period before touch driving, and an R node The charging/discharging unit may provide a gate driving circuit including a second transistor controlled by the auxiliary reset signal to supply high potential power to the R node. Accordingly, according to the present invention, the stage driven last before the touch driving period may produce a normal output due to the auxiliary reset signal. In addition, in the present invention, since there is no abnormal output of the stage during the touch driving period, the touch electrode can perform touch sensing. In addition, according to the present invention, all stages can make a normal output during the display driving period.

According to the present invention, the stage driven last before the touch driving period may produce a normal output due to the auxiliary reset signal.

In addition, in the present invention, since there is no abnormal output of the stage during the touch driving period, the touch electrode can perform touch sensing.

In addition, according to the present invention, when the display driving period starts after the touch driving period ends, the display can be driven normally even if there is no output from the previous stage.

In addition, according to the present invention, all stages can make a normal output during the display driving period.

1A is a diagram illustrating a touch panel integrated display device and a driver thereof according to an embodiment including one gate driving circuit.
1B is a diagram illustrating a plurality of pixels of a display panel and pattern electrodes corresponding thereto.
1C is a diagram illustrating a connection relationship between a pattern electrode and a sensing line.
FIG. 2 is a diagram illustrating a touch panel integrated display device and a driver thereof according to an embodiment having two gate driving circuits.
3 is a diagram illustrating a connection relationship between a plurality of stages constituting a shift register according to the first embodiment.
4 is a diagram illustrating a connection relationship between a plurality of stages constituting a shift register according to the second embodiment.
5 is a diagram illustrating a gate scan of a shift register according to the first and second embodiments.
6 is a time flow diagram illustrating display and touch time division driving.
7 is a circuit diagram of an Nth stage constituting a shift register according to an embodiment of the present invention.
8 is a diagram illustrating Q node charging and scan pulse output operations of the N-th stage in the display driving period before the start of touch driving.
9 is a diagram illustrating Q node discharging and QB node charging of the Nth stage in the display driving period before touch driving starts.
10 is a waveform diagram of an N-th stage in a display driving period before touch driving starts.
11 is a diagram illustrating the Q node charging and scan pulse output operations of the N+1th stage in the display driving period after the touch driving is finished.
12 is a diagram illustrating discharging of a Q node and charging of a QB node of an N+1th stage in the display driving period after the touch driving is terminated.
13 is a diagram illustrating R-node discharge of the N+1th stage in the display driving period after the touch driving is finished;
14 is a waveform diagram of the N+1th stage in the display driving period after the touch driving is finished.
15 is a diagram illustrating Q node charging and scan pulse output operations of the Nth stage in a general display driving period.
16 is a diagram illustrating Q node discharging and QB node charging of the Nth stage in a general display driving period.
17 is a diagram illustrating R node discharge of the Nth stage in a general display driving period.
18 is a waveform diagram of the N-th stage in a general display driving period.

Hereinafter, a gate driving circuit according to an embodiment of the present invention and a touch screen integrated display device including the same will be described in detail with reference to the drawings. The embodiments introduced below are provided as examples so that the spirit of the present invention can be sufficiently conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. Like reference numbers refer to like elements throughout.

Advantages and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout. The sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of description.

Reference to an element or layer to another element or “on” or “on” includes not only directly on the other element or layer, but also with other layers or other elements interposed therebetween. do. On the other hand, reference to an element "directly on" or "directly on" indicates that there are no intervening elements or layers.

Spatially relative terms "below, beneath", "lower", "above", "upper", etc. are one element or component as shown in the drawings. and can be used to easily describe the correlation with other devices or components. The spatially relative term should be understood as a term including different directions of the device during use or operation in addition to the directions shown in the drawings. For example, when an element shown in the figures is turned over, an element described as "beneath" or "beneath" another element may be placed "above" the other element. Accordingly, the exemplary term “below” may include both directions below and above.

The terminology used herein is for the purpose of describing the embodiments, and thus is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprise” and/or “comprising” refers to the presence of one or more other components, steps, operations, and/or elements mentioned. or addition is not excluded.

1A is a view showing a touch panel integrated display device and a driver thereof according to an embodiment having one gate driving circuit, and FIG. 1B is a view showing a plurality of pixels and corresponding pattern electrodes of the display panel. , FIG. 1C is a diagram illustrating a connection relationship between a pattern electrode and a sensing line. And FIG. 2 is a view showing a touch panel integrated display device and a driver thereof according to an embodiment having two gate driving circuits.

As shown, the display device of the present invention includes a liquid crystal panel 100 for displaying an image, a timing controller 400 for generating various control signals by receiving a timing signal from an external system, and a liquid crystal panel ( It includes gate and data driving circuits 200 and 300 for controlling 100 , and a touch driving circuit 500 for driving a touch.

In the liquid crystal panel 100, K (K is a natural number) gate wiring GL and a plurality of data wiring DL cross each other in a matrix form on a substrate using glass, and a plurality of pixels 110 are formed at the intersection points. define. Each pixel 110 is provided with a thin film transistor TFT, a liquid crystal capacitor Clc, and a storage capacitor Cst, and all pixels 110 form one display area A/A. An area in which the pixel 110 is not defined is divided into a non-display area N.

In addition, the liquid crystal panel 100 has a built-in touch screen, and the touch screen performs a function of detecting the user's touch position. In particular, the liquid crystal panel according to the present invention has a built-in in-cell type touch screen to which a self-capacitance method is applied. can do. Also, as shown in FIG. 1B , the liquid crystal panel 100 groups all the pixels 110 into a plurality of pixel groups, and may further include a plurality of pattern electrodes 120 corresponding to each group 1:1. Also, as shown in FIG. 1C , the plurality of pattern electrodes 120 may be connected to the touch driving circuit 500 through the sensing line SL.

A common voltage may be applied to the pattern electrode 120 to drive the display of the liquid crystal panel 100 , and accordingly, it may operate as a common electrode for driving the liquid crystal together with the pixel electrode. In addition, a touch scan signal may be applied to the pattern electrode 120 for touch sensing, and accordingly, the pattern electrode 120 may operate as a touch electrode sensing a touch position. For example, since it is a touch screen-integrated display device according to an embodiment of the present invention, display driving and touch driving are temporally divided and driven within one frame, and if the driving mode of the liquid crystal panel 100 is the display driving mode The plurality of pattern electrodes 120 receive a common voltage and operate as a common electrode for driving the display together with the pixel electrode. It operates as a touch electrode for sensing a touch position by receiving a signal. Here, the common voltage may be applied from the touch driving circuit 500 or may be provided with a separate common voltage generator to be directly applied to the liquid crystal panel 100 without going through the touch driving circuit 500 .

In addition, the touch driving circuit 500 includes a touch scan signal generating unit that generates a touch scan signal, a touch sensing unit that detects whether there is a touch using a difference between the received touch sensing signals, and a common voltage or a touch scan signal to the plurality of electrodes. It may be configured to include a switching unit that applies , receives a touch sensing signal generated by the touch scan signal from the plurality of pattern electrodes 120 , and detects whether or not there is a touch by using a difference between the received touch sensing signals.

Meanwhile, the pattern electrodes 120 may be grouped and sequentially operated for each group during one frame, and the number of pattern electrodes 120 constituting the group may be varied in consideration of the touch driving time and the display driving time.

The timing controller 400 receives timing signals such as an image signal (RGB) transmitted from an external system, a clock signal (DCLK), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a data enable signal (DE). A control signal and an auxiliary reset control signal ARSTC of the gate driving circuit 200 and the data driving circuit 300 are generated in response to the application.

Here, the horizontal sync signal Hsync is a signal representing the time taken to display one horizontal line of the screen, and the vertical sync signal Vsync is a signal representing the time taken to display the screen of one frame. Also, the data enable signal DE is a signal indicating a period in which the data voltage is supplied to the pixels defined in the liquid crystal panel 100 .

Also, the timing controller 400 generates a control signal GCS of the gate driving circuit 200 and a control signal DCS of the data driving circuit 300 in synchronization with an input timing signal.

In addition, the timing controller 400 generates a plurality of clock signals CLK for determining driving timing of each stage of the gate driving circuit 200 and provides them to the gate driving circuit 200 . In addition, the timing controller 400 aligns and modulates the received image data RGB DATA in a form that the data driving circuit 300 can process, and outputs it. Here, the aligned image data may be in a form to which a color coordinate correction algorithm for image quality improvement is applied.

In addition, the timing controller 400 may provide a touch enable signal TouchEN for driving a touch to the touch driving circuit 500 , and the touch driving circuit 500 provides a high level touch enable signal Touch While EN) is supplied, it becomes a touch driving section, and a touch can be sensed at this time.

Also, the timing controller 400 may generate an auxiliary reset control signal ARSTC for discharging the Q node during a set period. The set period may be a display driving period before touch driving starts. The set period may be stored in the memory unit of the timing controller 400 .

Next, the data driving circuit 300 shifts a source start pulse (SSP) from the timing controller 400 according to a source shift clock (SSC) to generate a sampling signal. In addition, the data driving circuit 300 latches image data input according to the source shift clock SSC according to the sampling signal, converts it into a data signal, and responds to a Source Output Enable (SOE) signal. Thus, the data signal is supplied to the data lines DL in units of horizontal lines. To this end, the data driving circuit 300 may include a data sampling unit, a latch unit, a digital-to-analog converter, an output buffer, and the like.

Also, the data driving circuit 300 may include a level shifter. The level shifter may generate an auxiliary reset signal ARST having the same level and duration as that of the clock signal CLK in response to the auxiliary reset control signal ARSTC from the timing controller 400 .

Next, the gate driving circuit 200 shifts the gate start pulse (GSP) transmitted from the timing controller 400 according to the gate shift clock (GSC), and sequentially the gate line ( A scan pulse having a gate high voltage VGH is supplied to GL 1 to GL n), and a gate low voltage is applied to the gate lines GL 1 to GL n during the remaining period when the scan pulse of the gate high voltage VGH is not supplied. (VGL) will be supplied.

On the other hand, the gate driving circuit 200 applied to the present invention is formed independently of the panel and can be electrically connected to the panel in various ways, but the gate driving circuit 200 is the liquid crystal panel ( 100), it may be embedded in the non-display area N in the form of a thin film pattern in a gate-in-panel (GIP) method. In this case, the gate control signal for controlling the gate driving circuit 200 may be a clock signal CLK and a start signal VST for driving the first stage of the shift register.

Also, the gate driving circuit 200 applied to the present invention may discharge the Q node of the last driven stage before the touch driving period according to the auxiliary reset signal ARST transmitted from the level shifter. For this reason, according to the present invention, the stage driven last before the touch driving period may produce a normal output.

Also, referring to FIG. 2 , two gate driving circuits 200 may be provided at both ends of the liquid crystal panel 100 and in the non-display area N. As shown in FIG. The first and second gate driving circuits 200a and 200b include a plurality of stages including shift registers. The first and second gate driving circuits 200a and 200b respond to the gate control signal GCS input from the timing controller 400 through a plurality of gate lines GL1 to GLn formed in the liquid crystal panel 100 . The scan pulse, the gate high voltage VGH, may be alternately output. Here, the output gate high voltage VGH may overlap for a predetermined horizontal period. This is for precharging the gate lines GL 1 to GL n, and more stable pixel charging may be performed when a data voltage is applied.

3 and 4 are diagrams illustrating a connection relationship between a plurality of stages constituting a shift register according to different embodiments of the present invention. And FIG. 5 is a diagram illustrating a gate scan of a plurality of stages constituting the shift register according to FIGS. 3 and 4 . 6 is a time flow diagram illustrating display and touch time division driving.

As shown in FIG. 5 , the stages are driven in the order of A and B when the gate scan is driven. And during gate scan driving, A is a stage that outputs the last scan pulse before touch driving, B is a holding stage in which the Q node maintains a charged state during touch driving, and is a stage that outputs the first scan pulse after touch driving is finished . B is also called a standby stage.

For convenience of explanation, the connection relationship of the N-th stage (N is a natural number and the N-th stage means the N-th stage) among the plurality of stages and the gate high voltage VGH are output from the N-th stage to the corresponding gate line Describe what you do.

<First and Second Shift Registers>

Referring to FIG. 3 , a shift register 210 according to an exemplary embodiment is a shift register included in the gate driving circuit 200 according to the exemplary embodiment shown in FIG. 1 , and referring to FIG. 4 , a shift register 210 according to another exemplary embodiment The register 210 is a shift register included in the gate driving circuits 200a and 200b according to the embodiment shown in FIG. 2 .

3 is a first shift register according to an embodiment, and FIG. 4 is a second shift register according to another embodiment. N-1, N, N+1, and N+2 are illustrated as a plurality of stages constituting the shift register 210 according to the embodiments of FIGS. 3 and 4 .

Each of the stages N-1, N, N+1, and N+2 includes a clock signal CLK line (first and second gate driving circuits 200a and 200b). In another embodiment, the first clock signal CLK 1) The clock signal may be applied from the wiring and the second clock signal (CLK 2 ). In addition, one of the output signals of the adjacent stages of the plurality of stages may be applied as a start signal VST and the other may be applied as a first reset signal RST1. In addition, the plurality of stages may receive the output signal of the next next stage as the second reset signal RST2.

Also, some stages among the plurality of stages may be a stage A that outputs the last scan pulse before touch driving. In this case, the stage A outputting the last scan pulse before the touch driving may receive the clock signal CLK from the clock signal CLK line, and the auxiliary reset signal ARST line (first and second gates). In another embodiment including the driving circuits 200a and 200b, the auxiliary reset signal ARST may be applied from the first auxiliary reset signal ARST 1 line and the second auxiliary reset signal ARST 2 line).

In addition, some stages among the plurality of stages may be a stage functioning as the standby stage (B). The standby stage B is a stage for outputting a first scan pulse after touch driving is terminated. That is, the standby stage B is a stage that needs to maintain the Q node voltage during the touch driving period.

The standby stage B may receive the clock signal CLK from the clock signal CLK line, one of the output signals of the adjacent stage is applied as the start signal VST, and the other is the first reset signal RST1 . ) can be approved. Also, the standby stage B may receive an output signal of the next next stage as the second reset signal RST2.

The stages may perform an operation for supplying a scan pulse when the start signal VST is input. Also, the stages may perform an operation of discharging the gate line GL when receiving the auxiliary reset signal ARST, the first reset signal RST1 and the second reset signal RST2.

Specifically, when driving a general display, the N-th stage Normal may include a start signal VST input terminal, a first reset signal RST1 input terminal, and a second reset signal RST2 input terminal. In addition, the N-th stage (Normal) receives the scan pulse output from the output terminal (G(n-1)) of the N-1 th stage, which is the previous stage, to the start signal (VST) input terminal, and the next stage The scan signal output from the output terminal G(n+1) of the N+1th stage is input to the first reset signal RST1 input terminal, and the output terminal G of the N+2th stage which is the next stage A scan signal output from (n+2)) may be input to the second reset signal RST2 input terminal.

The N+1th stage Normal may include a start signal VST input terminal, an auxiliary reset signal ARST input terminal, a first reset signal RST1 input terminal, and a second reset signal RST2 input terminal. there is. The N+1th stage receives the scan signal output from the output terminal G(n) of the Nth stage, which is the previous stage, as the start signal VST input terminal, and outputs the next stage, the N+2th stage. The scan signal output from the terminal G(n+2) is inputted to the first reset signal RST1 input terminal, and the scan signal is received from the output terminal G(n+3) of the N+3th stage, which is the next stage. The output scan signal may be received through the second reset signal RST2 input terminal.

The N+2th stage Normal may include a start signal VST input terminal, an auxiliary reset signal ARST input terminal, a first reset signal RST1 input terminal, and a second reset signal RST2 input terminal. there is. The N+2th stage (Normal) receives a scan pulse output from the output terminal (G(n+1)) of the N+1th stage, which is the previous stage, as the input terminal of the start signal (VST), and is the next stage A scan signal output from the output terminal G(n+3) of the N+3th stage is input to the first reset signal RST1 input terminal, and the output terminal G of the N+4th stage which is the next stage A scan signal output from (n+4)) may be input to the second reset signal RST2 input terminal.

Also, the stage A that outputs the last scan pulse before touch driving may be the N-th stage. In this case, the N-th stage A may further include an auxiliary reset signal ARST input terminal. Also, the Nth stage A may receive an auxiliary reset signal ARST from an auxiliary reset signal ARST line to the auxiliary reset signal ARST input terminal. In addition, the N-th stage A receives the scan signal output from the output terminal G(n+1) of the N+1-th stage B, which is the next stage, as the first reset signal until the touch driving is finished. (RST1) cannot receive an input through the input terminal, and when the display driving is started after the touch driving is finished, the scan signal output from the output terminal G(n+1) of the N+1th stage B, which is the next stage, is applied to the first The reset signal RST1 may be input through the input terminal.

Also, the standby stage B that outputs the first scan pulse after the touch driving is terminated may be the N+1th stage. In this case, the N+1th stage B receives the scan signal output from the output terminal G(n) of the Nth stage, which is the previous stage, as the start signal VST input terminal, and receives a Q node during touch driving. can remain charged. In addition, the N+1th stage B receives the scan signal output from the output terminal G(n+2) of the N+2th stage, which is the next stage, as the input terminal of the first reset signal RST1. The Q node can be discharged and the R node can be charged. In addition, the N+1th stage B receives the scan signal output from the output terminal G(n+3) of the N+3th stage, which is the next next stage, as the second reset signal RST2 input terminal. R node can be discharged.

As described above, the shift register 210 according to the embodiment of the present invention may include a plurality of standby stages B. As shown in FIG. For example, as shown in FIG. 5 , scan pulses are applied to the first to 64th stages for sequentially supplying scan pulses to the first to 64th gate lines GL1 to GL64 and the 65th to 128th gate lines GL65 to GL128 . In the 65th to 128th stages for sequentially supplying , the 65th stage may be a standby stage (B). However, although the gate lines GL are grouped by 64, the present invention is not limited thereto and may be set differently in consideration of the touch driving time and the driving time period.

Meanwhile, the plurality of stages may output the gate high voltage VGH as a scan pulse to any one of the plurality of gate lines GL 1 to GL n in synchronization with any one of the clock signals CLK.

In addition, the plurality of stages may receive the high potential power VDD from the high potential power supply terminal and the low potential power VSS from the low potential power supply terminal.

Referring to FIG. 6 , one frame (1Frame) may be time-divided into a plurality of display driving periods DT1, DT2, etc. and a plurality of touch driving periods TT1, TT2, and the like. Also, the plurality of display driving periods DT1, DT2, etc. and the plurality of touch driving periods TT1, TT2, etc. may alternately occur. Specifically, in the display device of the present invention, after driving the display during the display driving period (eg DT1) within one frame (1Frame), the touch sensing driving is performed during the touch driving period (eg TT1) and then again During the display driving period (eg, DT2), the display driving method may be repeated to alternately display driving and touch sensing driving.

<Circuit diagram of the Nth stage>

7 is a circuit diagram of an Nth stage constituting a shift register according to an embodiment of the present invention.

Referring to FIG. 7 , the N-th stage includes a pull-up transistor Tup, a pull-down transistor Tdown, a Q node charging/discharging unit 211, an R node charging/discharging unit 212, a QB node stabilizing unit 213, and a QB node charging unit. It may include a 214 and a Q-node stabilizing unit 215 .

When explaining the connection relationship between the above-described components of the N-th stage, the gate terminal of the pull-up transistor Tup is connected to the Q node, the drain terminal is connected to the clock signal CLK supply terminal, and the source terminal of the pull-up transistor Tup is the N-th stage. may be connected to the output terminal G(n) of In addition, the pull-down transistor Tdown may stably discharge the output terminal during the discharge period. A gate terminal of the pull-down transistor Tdown may be connected to a QB node, a drain terminal may be connected to an output terminal G(n) of the Nth stage, and a source terminal may be connected to an input terminal of the low potential power supply VSS.

In addition, the Q node charging/discharging unit 211 may function to charge or discharge the Q node. In addition, the Q-node charging/discharging unit 211 may include fourth and fifth transistors T4 and T5 . The gate terminal of the fourth transistor T4 is connected to the output terminal G(n-1) of the N-1 th stage, the drain terminal is connected to the input terminal of the high potential power supply VDD, and the source terminal is Q It can be connected to a node. A gate terminal of the fifth transistor T5 may be connected to an R node, a drain terminal may be connected to a Q node, and a source terminal may be connected to an input terminal of the low potential power supply VSS.

In addition, the R-node charging/discharging unit 212 may function to charge or discharge the R-node. In addition, the R-node charging/discharging unit 212 may include first to third transistors T1 , T2 , and T3 . The gate terminal of the first transistor T1 is connected to the output terminal G(n+1) of the N+1th stage, the drain terminal is connected to the input terminal of the high potential power supply VDD, and the source terminal is R It can be connected to a node. The gate terminal of the second transistor T2 may be connected to the input terminal of the auxiliary reset signal ARST, the drain terminal may be connected to the output terminal G(n) of the Nth stage, and the source terminal may be connected to the R node. there is. The gate terminal of the third transistor T3 is connected to the output terminal G(n+2) of the N+2th stage, the drain terminal is connected to the R node, and the source terminal of the low potential power VSS It can be connected to the input terminal.

In addition, the QB node stabilizing unit 213 may function to discharge the QB node. In addition, the stabilization unit 213 may include eighth and tenth transistors T8 and T10 . A gate terminal of the eighth transistor T8 may be connected to a Q node, a drain terminal may be connected to a QB node, and a source terminal may be connected to an input terminal of the low potential power supply VSS. The gate terminal of the tenth transistor T10 is connected to the output terminal G(n-1) of the N-1 th stage, the drain terminal is connected to the QB node, and the source terminal is connected to the low potential power supply VSS. It can be connected to the input terminal.

The QB node charging unit 214 may function to charge the QB node. In addition, the QB node charging unit 214 may include seventh and ninth transistors T7 and T9 . A gate terminal of the seventh transistor T7 may be connected to the R node, a drain terminal may be connected to an input terminal of the high potential power source VDD, and a source terminal may be connected to the QB node. The ninth transistor T9 is a diode connection transistor, and the diode connection transistor electrically connects a gate terminal and a drain terminal to drive an operation similar to that of a diode device. An operation similar to that of a diode device is driven by electrically connecting a gate terminal and a drain terminal of the ninth transistor T9. A drain terminal of the ninth transistor T9 may be connected to an input terminal of the high potential power source VDD, and a source terminal may be connected to a QB node. Meanwhile, since the ninth transistor T9 is a diode-connected transistor, the QB node can be charged without a separate control signal to be controlled.

The Q node stabilizing unit 215 may function to discharge the Q node and may include a sixth transistor T6 . A gate terminal of the sixth transistor T6 may be connected to a QB node, a drain terminal may be connected to a Q node, and a source terminal may be connected to an input terminal of the low potential power supply VSS.

<The driving method of the Nth stage (A) for outputting the last scan pulse in the display driving period before the start of the touch driving>

8 is a view showing the Q node charging and scan pulse output operation of the Nth stage in the display driving period before the touch driving starts, and FIG. 9 is the Q node discharging and QB of the Nth stage in the display driving period before the touch driving starts. It is a diagram showing node charging, and FIG. 10 is a waveform diagram of the Nth stage in the display driving period before the start of touch driving.

For a description of the driving method of the stage A that outputs the last scan pulse before touch driving, it is assumed that the stage A that outputs the last scan pulse before touch driving is an N-th stage.

8 and 10 , during the first time period (①) of the display driving period DT1 , the ninth transistor T9 is turned on by the output signal of the high potential power supply VDD to generate the high potential power supply VDD. can be supplied to the QB node. The QB node is in a charged state. The sixth transistor T6 is turned on by the charged QB node to supply the low potential power VSS to the Q node. The Q node is in a discharged state.

During the second time period (②), the fourth transistor T4 is turned on by the output signal of the N-1 th stage to supply the high potential power VDD to the Q node. The Q node is in a charged state. The eighth transistor T8 is turned on by the charged Q node to supply the low potential power VSS to the QB node. Also, the tenth transistor T10 may be turned on by the output signal of the N-1 th stage to supply the low potential power VSS to the QB node. The QB node is in a discharged state.

During the third time period ③, the pull-up transistor Tup may be bootstrapped by the high logic level of the clock signal CLK and turned on. Accordingly, a scan pulse of a high logic level may be output to the output terminal G(n) of the N-th stage A. As shown in FIG.

9 and 10 , during the fourth time period ④, the second transistor T2 is turned on by the high logic level of the auxiliary reset signal ARST to transmit the output signal of the N-th stage A to the R node can be supplied to The fifth transistor T5 may be turned on by the R node to supply the low potential power VSS to the Q node. The seventh transistor T7 may be turned on by the R node to supply the high potential power VDD to the QB node. The ninth transistor T9 is turned on by the output signal of the high potential power VDD to supply the high potential power VDD to the QB node. The QB node is in a charged state. The sixth transistor T6 may be turned on by the QB node to supply the low potential power VSS to the Q node. The Q node is in a discharged state. The pull-down transistor Tdown may be turned on by the QB node to provide the low potential power VSS to the output terminal G(n) of the Nth stage A. That is, the output terminal G(n) of the N-th stage A may output a low logic level. In particular, since the signal of the R node momentarily changes from a high logic level to a low logic level by the output signal of the Nth stage A, it may be a pulse wave waveform. For this reason, unlike the prior art, in the present invention, the stage driven last before the touch driving period may produce a normal output due to the auxiliary reset signal. In addition, in the present invention, since there is no abnormal output of the stage during the touch driving period, the touch electrode can perform touch sensing.

<Drive method of standby stage (B)>

11 is a view showing the Q node charging and scan pulse output operation of the N+1th stage in the display driving period after the touch driving is finished, and FIG. 12 is the Q of the N+1th stage in the display driving period after the touch driving is finished. It is a diagram showing node discharging and QB node charging, FIG. 13 is a diagram showing R node discharging of the N+1th stage in the display driving period after the touch driving is finished, and FIG. 14 is the first in the display driving period after the touch driving is finished. It is a waveform diagram of the N+1 stage.

The standby stage B is a holding stage in which the Q node maintains a charged state during touch driving, and a stage for outputting a first scan pulse after the touch driving is terminated. For explanation, it is assumed that the N+1th stage is the standby stage (B). In this case, the (N+1)th stage (B) may be a stage following the Nth stage (A) for outputting the last scan pulse before touch driving.

11 and 14 , during the first time period (①, hereinafter, first to fourth time periods are different from the first to fourth time periods of FIG. 10 ) of the display driving period DT1, the fourth transistor ( T4) may be turned on by the output signal of the N-th stage to supply the high potential power VDD to the Q node. The Q node is in a charged state. The eighth transistor T8 is turned on by the charged Q node to supply the low potential power VSS to the QB node. Also, the tenth transistor T10 may be turned on by the output signal of the Nth stage to supply the low potential power VSS to the QB node. The QB node is in a discharged state.

11 and 14 , the touch driving period TT1 starts, and the charged voltage on the Q node is maintained during the second time period ② of the touch driving period TT1. That is, the second time period (②) is a Q node voltage holding period.

11 and 14 , the display driving period DT2 starts, and during the third time period ③, the pull-up transistor Tup may be bootstrapped by the high logic level of the clock signal CLK and turned on. there is. Accordingly, a scan pulse of a high logic level may be output to the output terminal G(n+1) of the N+1th stage B. FIG.

12 and 14 , during the fourth time period ④, the first transistor T1 is turned on by the output signal of the N+2th stage to supply the high potential power VDD to the R node. The fifth transistor T5 may be turned on by the R node to supply the low potential power VSS to the Q node. The R node is in a charged state. The seventh transistor T7 may be turned on by the R node to supply the high potential power VDD to the QB node. The ninth transistor T9 is turned on by the output signal of the high potential power VDD to supply the high potential power VDD to the QB node. The QB node is in a charged state. The sixth transistor T6 may be turned on by the QB node to supply the low potential power VSS to the Q node. The Q node is in a discharged state. The pull-down transistor Tdown is turned on by the QB node to provide the low potential power VSS to the output terminal G(n+1) of the N+1th stage B. That is, the output terminal G(n+1) of the N+1th stage B may output a low logic level. For this reason, unlike the prior art, in the present invention, when the display driving period starts after the touch driving period ends, the Q node of the driving stage can be sufficiently charged even if there is no output from the previous stage. Accordingly, the present invention can drive a normal display.

13 and 14 , during the fifth time period ⑤, the third transistor T3 is turned on by the N+3th output signal to supply the low potential power VSS to the R node. The R node is in a discharged state. Due to this, the N+1th stage B is in a ready state for the next driving.

<General stage (Normal) driving method>

15 is a view showing the Q node charging and scan pulse output operation of the Nth stage in a general display driving period, and FIG. 16 is a diagram showing the Q node discharging and QB node charging of the Nth stage in a general display driving period. , FIG. 17 is a diagram illustrating R node discharge of the N-th stage in a general display driving period, and FIG. 18 is a waveform diagram of the N-th stage in a general display driving period.

A general stage (Normal) is a display driving stage except for the stage (A) outputting the last scan pulse and the standby stage (B). It is assumed that the Nth stage (Normal) is a general stage.

15 and 18 , during the first time period (①, hereinafter, first to fifth time periods are different from the first to fifth time periods of FIGS. 10 and 14 ) of the display driving period DT1 ) The 9 transistor T9 is turned on by the output signal of the high potential power VDD to supply the high potential power VDD to the QB node. The QB node is in a charged state. The sixth transistor T6 is turned on by the charged QB node to supply the low potential power VSS to the Q node. The Q node is in a discharged state.

During the second time period (②), the fourth transistor T4 is turned on by the output signal of the N-1 th stage to supply the high potential power VDD to the Q node. The Q node is in a charged state. The eighth transistor T8 is turned on by the charged Q node to supply the low potential power VSS to the QB node. Also, the tenth transistor T10 may be turned on by the output signal of the N-1 th stage to supply the low potential power VSS to the QB node. The QB node is in a discharged state.

During the third time period ③, the pull-up transistor Tup may be bootstrapped by the high logic level of the clock signal CLK and turned on. Accordingly, a scan pulse of a high logic level may be output to the output terminal G(n) of the N-th stage A. As shown in FIG.

16 and 18 , during the fourth time period ④, the first transistor T1 is turned on by the output signal of the N+1th stage to supply the high potential power VDD to the R node. The fifth transistor T5 may be turned on by the R node to supply the low potential power VSS to the Q node. The R node is in a charged state. The seventh transistor T7 may be turned on by the R node to supply the high potential power VDD to the QB node. The ninth transistor T9 is turned on by the output signal of the high potential power VDD to supply the high potential power VDD to the QB node. The QB node is in a charged state. The sixth transistor T6 may be turned on by the QB node to supply the low potential power VSS to the Q node. The Q node is in a discharged state. The pull-down transistor Tdown may be turned on by the QB node to provide the low potential power VSS to the output terminal G(n) of the N-th stage Normal. That is, the output terminal G(n) of the N-th stage Normal may output a low logic level.

17 and 18 , during the fifth time period ⑤, the third transistor T3 is turned on by the N+2th output signal to supply the low potential power VSS to the R node. The R node is in a discharged state. Accordingly, the N-th stage (Normal) is in a ready state for the next driving.

Accordingly, according to the present invention, the stage driven last before the touch driving period may produce a normal output due to the auxiliary reset signal.

In addition, in the present invention, since there is no abnormal output of the stage during the touch driving period, the touch electrode can perform touch sensing.

In addition, according to the present invention, when the display driving period starts after the touch driving period ends, the display can be driven normally even if there is no output from the previous stage.

In addition, according to the present invention, all stages can make a normal output during the display driving period.

In the detailed description of the present invention described above, although it has been described with reference to preferred embodiments of the present invention, those skilled in the art or those having ordinary knowledge in the technical field of the present invention described in the claims to be described later It will be understood that various modifications and variations of the present invention can be made without departing from the spirit and scope of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10 display
100 liquid crystal panel
110 pixels
120 pattern electrode
200 gate driving circuit
200a first gate driving circuit
200b second gate driving circuit
210 shift register
211 Q-node charging/discharging unit
212 R node charge/discharge unit
213 QB node stabilization part
214 QB node charging part
215 Q node stabilization part
300 data drive circuit
400 timing controller
500 touch drive circuit

Claims (12)

It is controlled by the output signal of the N-1th stage (N is a natural number greater than 1) to supply the high potential power to the Q node, and controlled by the voltage on the R node of the R node charging/discharging unit to supply the low potential power to the Q node. Q node charging/discharging unit to supply;
A first transistor controlled by the output signal of the N+1th stage to supply a high potential power to the R node, and a second transistor controlled by an auxiliary reset signal to supply an output signal of the Nth stage to the R node and an R node charging/discharging unit including a third transistor controlled by the output signal of the N+2th stage to supply a low potential power to the R node;
a pull-up transistor controlled by the voltage on the Q node and outputting an applied clock signal to an N-th output terminal; and
An N-th stage including a pull-down transistor controlled by the voltage on the QB node to supply a low potential power to the N-th output terminal,
Time division of one frame into a display driving section and a touch driving section,
When the Nth stage is a stage for outputting the last scan pulse before the start of the touch driving period, the R node charging/discharging unit supplies the output signal of the Nth stage to the R node in response to the auxiliary reset signal to provide the Q A gate driving circuit for discharging a node with a low potential power supply, charging the QB node with a high potential power supply, and resetting the N-th output terminal. It is controlled by the output signal of the N-1th stage (N is a natural number greater than 1) to supply the high potential power to the Q node, and controlled by the voltage on the R node of the R node charging/discharging unit to supply the low potential power to the Q node. Q node charging/discharging unit to supply;
an R node charging/discharging unit including a second transistor controlled by an auxiliary reset signal to supply an output signal of an Nth stage to the R node;
a pull-up transistor controlled by the voltage on the Q node and outputting an applied clock signal to an N-th output terminal; and
An N-th stage including a pull-down transistor controlled by the voltage on the QB node to supply a low potential power to the N-th output terminal,
The N-th stage outputs the last scan pulse in the display driving section before touch driving,
Time division of one frame into a display driving section and a touch driving section,
When the Nth stage is a stage for outputting the last scan pulse before the start of the touch driving period, the R node charging/discharging unit supplies the output signal of the Nth stage to the R node in response to the auxiliary reset signal to provide the Q A gate driving circuit for discharging a node with a low potential power supply, charging the QB node with a high potential power supply, and resetting the N-th output terminal. According to claim 1,
The display driving section includes a first display driving section before the touch driving section and a second display driving section following the touch driving section,
In the first display driving period, the Q node is charged,
A gate driving circuit for outputting a scan pulse to the N-th output terminal during the second display driving period. delete 3. The method according to claim 1 or 2,
The N-th stage further includes a QB node stabilizing unit for supplying low-potential power to the QB node,
and the QB node stabilizing unit includes a tenth transistor controlled by an output signal of an N-1 th stage to supply low potential power to the QB node. 6. The method of claim 5,
The QB node stabilizing unit further includes an eighth transistor controlled by the voltage on the Q node to supply a low potential power to the QB node. 3. The method according to claim 1 or 2,
The Nth stage further includes a QB node charging unit for supplying high potential power to the QB node,
The QB node charging unit includes a seventh transistor controlled by the voltage on the R node to supply a high potential power to the QB node. 8. The method of claim 7,
The QB node charging unit further includes a ninth transistor having a gate terminal and a drain terminal electrically connected and a high potential power source being provided to the drain terminal to supply the high potential power to the QB node. 3. The method according to claim 1 or 2,
The Nth stage further includes a Q node stabilizing unit for supplying low potential power to the Q node,
The Q node stabilizing unit includes a sixth transistor controlled by the voltage on the QB node to supply a low potential power to the Q node. The gate driving circuit according to claim 1;
a panel for displaying images; and
Including; a touch driving circuit for sensing the touch of the panel;
the gate driving circuit provides a scan signal to the panel;
The panel includes a plurality of pixels, a plurality of pattern electrodes grouping the plurality of pixels into a plurality of pixel groups, one-to-one corresponding to each group, and a sensing line connecting each of the pattern electrodes to the touch driving circuit A touch screen integrated display comprising a. The gate driving circuit according to claim 2;
a panel for displaying images; and
Including; a touch driving circuit for sensing the touch of the panel;
the gate driving circuit provides a scan signal to the panel;
The panel includes a plurality of pixels, a plurality of pattern electrodes grouping the plurality of pixels into a plurality of pixel groups, one-to-one corresponding to each group, and a sensing line connecting each of the pattern electrodes to the touch driving circuit A touch screen integrated display comprising a. 12. The method of claim 11,
a timing controller outputting an auxiliary reset control signal; and
The touch screen integrated display device further comprising a; data driving circuit for outputting an auxiliary reset signal based on the auxiliary reset control signal.

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