KR102390982B1 - Display device, and driving device and method thereof - Google Patents

Abstract

The present invention relates to a display device, a driving device and a method thereof, and the display device can maintain a voltage of a Q node by minimizing a leakage current of a stage in a standby state during touch driving.

Description

DISPLAY DEVICE, AND DRIVING DEVICE AND METHOD THEREOF

The present invention relates to a display device and a driving device and method therefor.

Touch screen is a liquid crystal display (Liquid Crystal Display), field emission display (FED), plasma display panel (PDP), electroluminescence display (Electroluminescence Device, EL), electrophoretic display device It is a type of input device installed in an image display device, such as, etc., in which a user presses (presses or touches) a touch sensor in a touch screen while viewing the image display device to input predetermined information.

The driving circuit of the display device includes a pixel array on which an image is displayed, a data driving circuit that supplies a data signal to data lines of the pixel array, and a gate pulse (or scan pulse) synchronized with the data signal to the gate lines (or scan pulses) of the pixel array. and a gate driving circuit (or scan driving circuit) sequentially supplied to the scan lines), a timing controller controlling the data driving circuit and the gate driving circuit, and the like.

Each of the pixels may include a thin film transistor (TFT) that supplies a voltage of a data line to the pixel electrode in response to a gate pulse. The gate pulse swings between a gate high voltage (VGH) and a gate low voltage (VGL). The gate high voltage VGH is a turn-on voltage of the transistor and is set to a voltage higher than a threshold voltage in the case of an n-type MOSFET. The gate low voltage VGH is a turn-off voltage of the transistor and is set to a voltage lower than a threshold voltage in the case of an n-type MOSFET.

Recently, a technique for embedding a gate driving circuit together with a pixel array in a display panel has been applied. Hereinafter, a gate in panel (GIP) refers to a gate driving circuit embedded in a display panel. A gate driving circuit includes a shift register. A shift register includes a number of cascadingly connected stages. The stages generate an output in response to a start pulse and shift the output according to a shift clock.

The stages of the shift register include a Q node for charging the gate wiring, a QB node for discharging the gate wiring, and a switch circuit connected to the Q node and the QB node. The switch circuit raises the voltage of the gate wiring by supplying the Q node in response to the start pulse or the output of the previous stage, and discharges the QB node in response to the output of the next stage or the reset pulse. The switch circuit may be implemented with TFTs having a metal oxide semiconductor field effect transistor (MOSFET) structure.

The touch screen can be divided into an add-on type, an on-cell type, and an in-cell type according to its structure. The attachment type is a method of attaching the touch screen to the upper plate of the display device after manufacturing the display device and the touch screen separately. The top plate type is a method of directly forming elements constituting the touch screen on the surface of the upper glass substrate of the display device. The built-in type is a method in which a touch screen is embedded inside the display device to achieve thinness of the display device and to increase durability. However, the attachable touch screen has a problem in that the finished touch screen is mounted on the display device, and the thickness is thick, and the brightness of the display device is darkened, thereby reducing visibility. In addition, the top-panel touch screen has a structure in which a separate touch screen is formed on the upper surface of the display device, and although the thickness can be reduced compared to that of the attached type, it is still the entirety because of the driving and sensing electrodes constituting the touch screen and an insulating layer for insulating them. As the thickness increases and the number of processes increases, there is a problem in that the manufacturing price increases.

On the other hand, the integrated touch screen has the advantage of solving the problems caused by the attachable type and the top plate type touch screen in that durability and thinness can be improved. Such an integrated touch screen may be divided into an optical type and a capacitive type touch screen.

The optical touch screen is a method of forming a light sensing layer on a thin film transistor substrate array of a display device and recognizing light reflected through an object existing in a touched portion using light or infrared light from a backlight unit. However, the optical touch screen shows relatively stable driving performance when the surroundings are dark, but when the surroundings are bright, lights stronger than the reflected light act as noise. This is because the intensity of the light reflected by the actual touch is very weak, and an error may occur in touch recognition even if the outside is slightly bright. In particular, the optical touch screen has a problem in that, when the surrounding environment is exposed to sunlight, the intensity of light is so strong that the touch may not be recognized in some cases.

The capacitive touch screen may be divided into a self-capacitance type and a mutual capacitance type. The mutual capacitance type touch screen divides the common electrode and divides it into a driving electrode and a sensing electrode to form a mutual capacitance between the driving electrode and the sensing electrode, thereby reducing the amount of change in mutual capacitance that occurs during touch. A method of recognizing a touch by measuring it. However, in the mutual capacitance type touch screen, the size of the mutual capacitance generated during touch recognition is very small, whereas the parasitic capacitance between the gate wiring and the data wiring constituting the display device is very large. There is a problem that is difficult to recognize. In addition, the mutual capacitive touch sensor has a problem in that it requires a very complicated wiring structure because a plurality of touch driving lines for driving a touch and a plurality of touch sensing lines for sensing a touch must be formed on a common electrode. In order to solve this problem, recently, when a plurality of electrodes are formed in the display area of a panel, they are formed to overlap a plurality of pixel electrodes, and these electrodes are used to drive liquid crystals together with the pixel electrodes formed in each pixel during the display driving period. A split method between a display and a touch driving has been proposed, which operates as a common electrode and operates as a touch electrode that detects a touch position by a touch scan signal applied from a touch driver during a touch driving period.

In the case of the display and touch division driving method, there is a stage in which the Q node is held in a stand-by state among the stages constituting the shift register of the gate driving circuit during the touch driving time. Since the Q node of the corresponding stage is in a floating state without power supply during the touch driving time, there is a problem in that a voltage drop due to leakage current occurs. This problem leads to a problem in that an abnormal signal is output on the gate wiring, and there is a problem in image quality such as a dim phenomenon in which a horizontal line is recognized on a display panel corresponding to the corresponding gate wiring. Furthermore, there is a limitation in increasing the touch driving time due to a problem in which the Q node voltage of the stage in the standby state drops.

The present invention can provide a display device and a driving device and method for maintaining the voltage of the Q node by minimizing the leakage current of the stage in the standby state when the driving circuit is touch driven.

The present invention may also provide a driving circuit for a display device capable of securing a clock time (CLK time) at high resolution by reducing a margin time between a driving circuit display driving time and a touch driving time, and a driving device and method therefor .

The present invention may also provide a display device capable of increasing a touch driving time according to holding the Q node voltage of a standby stage with a stable driving circuit, and a driving device and method driving circuit therefor.

A display device of the present invention includes: a display panel in which data lines and gate lines are crossed, pixels are arranged in a matrix form, and touch sensors; a touch driving circuit for driving the touch sensors; a data driving circuit for supplying a data signal to the data lines; a gate driving circuit for supplying a gate pulse to the gate wirings using a shift register; and a timing controller that supplies input image data to the data driving circuit and controls operation timings of the data driving circuit and the gate driving circuit.

The timing controller generates a touch enable signal defining a display section and a touch section. The shift register includes a stage to which the touch enable signal is input.

The stage includes a Q node for controlling a pull-up transistor; and a transistor connected to a discharge path of the Q node, including a drain connected to the Q node and a source to which a high level voltage of the touch enable signal is applied, and maintaining an off state during the touch period.

The method of driving the display device may include generating a touch enable signal defining the display section and the touch section; and a high level voltage of the touch enable signal during the touch period to a gate driving circuit that supplies a gate pulse to the gate wiring of the display device according to the voltage of the Q node, so that the drain of the transistor connected to the discharge path of the Q node - reducing the voltage between the sources.

In the gate driving circuit of the present invention and a touch screen integrated display including the same, one frame is time-divided into a display driving section and a touch driving section, and the touch enable signal is high or low in the touch driving section. ) level, a first transistor that is controlled by the output signal of the previous stage to supply a first level touch enable signal to the Q node, and a second level of touch that is controlled by the output signal of the next stage a second transistor for supplying an enable signal to the Q node, and a pull-up transistor for outputting a first clock signal applied by being controlled by a voltage on the Q node to an N-th output terminal; When the transistor is an N-type transistor, the first level becomes a high level and the second level becomes a low level, and when the transistor is a P-type, the second level becomes a high level and the first level becomes a low level. In the path between the source-drain terminal where the charged charge on the Q node can easily escape by including the stage, a high logic level touch enable signal (Touch EN) that is a high potential power to the source or drain terminal that is the terminal opposite to the Q node By supplying , it is possible to keep the Q node voltage from falling and to rise to a higher voltage even during bootstrap.

The gate driving circuit and the touch screen integrated display including the same according to an embodiment of the present invention maintain the voltage of the Q node by minimizing the leakage current of the standby stage when the touch is driven, and between the display driving time and the touch driving time. A gate driving circuit that can secure the clock time (CLK time) at high resolution by reducing the margin time and increase the touch driving time according to the holding of the Q node voltage of the stable standby stage It is possible to provide a touch screen integrated display device.

1 is a diagram showing Id according to Vgs of an n-type MOSFET.
2 is a diagram showing Id according to Vds in a region below a threshold voltage of an n-type MOSFET.
3 and 4 are diagrams illustrating examples in which the Q node may be discharged in the gate driving circuit.
5 to 8 are views showing embodiments of preventing discharge of the Q node in the present invention.
9 to 11 are views showing a driving device according to an embodiment of the present invention.
12 is a view illustrating a touch panel integrated display device and a driver thereof according to an embodiment having one gate driving circuit;
13 is a view illustrating a plurality of pixels of a display panel and pattern electrodes corresponding thereto;
14 is a diagram illustrating a connection relationship between a pattern electrode and a sensing line;
15 is a view showing a touch panel integrated display device and a driver thereof according to an embodiment having two gate driving circuits;
Fig. 16A is a diagram showing a connection relationship between a plurality of stages constituting the shift register according to the first embodiment;
Fig. 16B is a diagram showing a connection relationship between a plurality of stages constituting a shift register according to the second embodiment;
Fig. 17A is a diagram showing a connection relationship between a plurality of stages constituting a shift register according to the third embodiment;
Fig. 17B is a diagram showing a connection relationship between a plurality of stages constituting a shift register according to the fourth embodiment;
Fig. 18A shows forward and reverse gate scans of the shift register according to the first and third embodiments;
Fig. 18B is a diagram showing forward and reverse gate scans of the shift register according to the second and fourth embodiments;
18C is a diagram without a dummy stage when the gate scan direction is unidirectional (forward) scan.
18D is a view in which a dummy stage is added when the gate can be driven in both directions.
19 is a time flow chart showing display and touch time division driving.
20 is a circuit diagram of an Nth stage constituting a shift register according to an embodiment of the present invention;
Fig. 21 is a circuit diagram of a standby stage;
22 is a circuit diagram of a dummy stage;
Fig. 23 is a diagram showing Q node charging and gate pulse output operations of the Nth stage in forward driving;
24 is a diagram illustrating discharging of a Q node and charging of a QB node of an N-th stage in forward driving.
Fig. 25 is a view showing the operation of charging the Q node and outputting the gate pulse of the Nth stage in the reverse driving.
26 is a diagram illustrating discharging of a Q node and charging of a QB node of an N-th stage in reverse driving.
Fig. 27 is a diagram showing Q node charging of the Nth stage as a standby stage in forward driving;
28 is a diagram illustrating a holding period for maintaining the Q node voltage;
Fig. 29 is a diagram showing a gate pulse output operation;
30 is a diagram illustrating discharging operations of a Q node and an output terminal;
Fig. 31 is a waveform diagram when a standby stage is driven;
Fig. 32 is a diagram showing Q-node charging of a dummy stage in forward driving;
33 is a diagram illustrating a holding period for maintaining the Q node voltage;
Fig. 34 is a diagram showing a gate pulse output operation;
35 is a diagram illustrating discharging operations of a Q node and an output terminal;
36 is a waveform diagram when a dummy stage is driven;
37 is a waveform diagram illustrating a Q node voltage when a standby stage or a dummy stage is operated;

Hereinafter, a gate driving circuit according to an embodiment of the present invention and a touch screen integrated display device including the same will be described in detail with reference to the drawings. The embodiments introduced below are provided as examples so that the spirit of the present invention can be sufficiently conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numbers refer to like elements throughout.

Advantages and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout. The sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of description.

Reference to an element or layer to another element or “on” or “on” includes not only directly on the other element or layer, but also with other layers or other elements interposed therebetween. do. On the other hand, reference to an element "directly on" or "directly on" indicates that there are no intervening elements or layers.

Spatially relative terms "below, beneath", "lower", "above", "upper", etc. are one element or component as shown in the drawings. and can be used to easily describe the correlation with other devices or components. The spatially relative term should be understood as a term including different directions of the device during use or operation in addition to the directions shown in the drawings. For example, when an element shown in the figures is turned over, an element described as "beneath" or "beneath" another element may be placed "above" the other element. Accordingly, the exemplary term “below” may include both directions below and above.

The terminology used herein is for the purpose of describing the embodiments, and thus is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprise” and/or “comprising” refers to the presence of one or more other components, steps, operations, and/or elements mentioned. or addition is not excluded.

In the gate driving circuit of the present invention, the switch elements may be implemented as transistors having an n-type or p-type MOSFET structure. It should be noted that although the n-type transistor is exemplified in the following embodiments, the present invention is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, since electrons flow from source to drain, the direction of current flows from drain to source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed according to the applied voltage. The invention should not be limited by the source and drain of the transistor in the following embodiments.

According to the present invention, pixels and touch sensors are driven by time-divisioning one frame period into one or more touch times and one or more display times. The display section is separated with a touch driving section interposed therebetween. The shift register of the gate driving circuit does not generate an output during the touch driving period and must generate the next output when the next display period is resumed. However, when the Q node voltage of the shift register is discharged during the touch driving period and the next display period is resumed, the voltage of the gate pulse is lowered, and as a result, the charging field of the pixels connected to the same gate wiring is lowered, thereby generating line-type noise. .

When the gate-source voltage (Vgs) of the transistor is lower than the threshold voltage (Vth), the transistor is turned off so that the drain current (Id) does not flow, but the transistor is in the off state or the threshold A leakage current may be generated in a sub-threshold region. In fact, when Vgs is lower than Vth (Vgs < Vth), a sub-threshold current is generated in an off state of the transistor or in a sub-threshold region as shown in FIG. 1 . The leakage current or the sub-threshold current in the region below the threshold voltage increases as the drain-source voltage Vds and the gate-source voltage Vgs of the transistor increase as shown in FIGS. 1 and 2 . . Although the leakage current is not large, the amount of leakage current increases as the leakage current flows longer, adversely affecting circuit operation and generating power consumption. In addition, the leakage current of the transistor increases as the operating temperature increases, and increases in proportion to the intensity of the light when the semiconductor channel of the transistor is exposed.

In the present invention, the discharge of the Q node is prevented by reducing Vds in the off state (Vgs < Vth) of the transistor in order to minimize the leakage current of the transistors connected on the discharge path of the Q node during the touch driving period.

3 and 4 are diagrams illustrating examples in which the Q node may be discharged in the gate driving circuit. 3 and 4 illustrate an n-th stage that generates an n-th output Vout by operating in a forward mode in a bi-directional shift register. It should be noted that the gate driving circuit shown in FIGS. 3 and 4 exemplifies a situation in which discharging of the Q node may occur, and is not a prior art widely known prior to the filing of the present application. The transistors shown in FIGS. 3 and 4 exemplify an n-type MOSFET, but the present invention is not limited thereto.

3 and 4, the shift register of the gate driving circuit includes cascadingly connected stages. Each of the stages includes a Q node controlling the pull-up transistor Tup, a charging/discharging unit 21 connected to the Q node, a Q node stabilizing unit 22, and a QB node controlling the pull-down transistor Tdown.

The charging/discharging unit 21 includes first and second transistors T1 and T2 . The first and second transistors T1 and T2 charge and discharge the Q node. When the bidirectional shift register operates in the forward mode, the first transistor T1 charges the Q node in response to the output Gn-1 of the n-1 th stage, and the second transistor T2 has the n+1 th stage. The Q node is discharged in response to the output (Gn+1) of the stage. The drain of the first transistor T1 is connected to the forward power terminal, and the source is connected to the Q node. The gate of the first transistor T1 is connected to the first gate terminal. In forward mode, VGH is supplied to the forward power terminal. In the reverse mode, the gate low voltage VGL is supplied to the forward power terminal. The output (G(n-1)) of the previous clock or n-1 th stage is input to the first gate terminal. The previous clock is a clock having a higher phase than the n-th clock CLK applied to the pull-up transistor Tup. VGH is set to a voltage higher than the threshold voltage Vth of the transistors T1 , T2 , and T3 . VGL is set to a voltage lower than the threshold voltage Vth of the transistors T1 , T2 , and T3 .

The drain of the second transistor T2 is connected to the Q node, and the source is connected to the reverse power terminal. The gate of the second transistor T2 is connected to the second gate terminal. In forward mode, the reverse power supply terminal is supplied with VGL. In reverse mode, VGH is supplied to the reverse power terminal. To the second gate terminal, the next clock or the output (G(n+1)) of the n+1th stage is input. The next clock is a clock having a phase later than the n-th clock CLK.

The Q node is pre-charged with VGH from the charging/discharging unit 21, and when the n-th clock CLK is supplied to the pull-up transistor Tup, its potential rises to 2VGH due to bootstrapping. to turn on the pull-up transistor Tup. The pull-up transistor Tup is turned on according to the Q node voltage to increase the output voltage Vout to the VGH potential with the nth clock CLK of VGH. The gate of the pull-up transistor Tup is connected to the Q node. A drain of the pull-up transistor Tup is connected to a clock terminal. A source of the pull-up transistor Tup is connected to an output terminal. An n-th clock CLK is input to the clock terminal.

The Q node stabilizing unit 22 includes a third transistor T3 . The third transistor T3 discharges the Q node in response to the QB node. A QB control signal generated based on an n-th clock CLK and a clock applied to the first gate terminal or a clock that does not overlap with the previous output Gn-1 is input to the QB node. The QB control signal simultaneously turns on the third transistor T3 and the pull-down transistor Tdown to discharge the Q node and poll the output voltage Vout. The gate of the third transistor T3 is connected to the QB node. A drain of the third transistor T3 is connected to the Q node. The source of the third transistor T3 is connected to the low potential power terminal. VGL is supplied to the low potential power terminal.

The pull-down transistor Tdown lowers the output voltage Vout to VGL by discharging the output terminal in response to the QB control signal. The gate of the pull-down transistor Tdown is connected to the QB node. A drain of the pull-down transistor Tdown is connected to an output terminal. A source of the pull-down transistor Tdown is connected to a low potential power terminal.

The touch period is longer than one horizontal time of the display period. During this touch period, VGL is applied to the gates of the second and third transistors T2 and T3. Therefore, since Vgs = 0 of the second and third transistors T2 and T3 during the touch period, ideally there should be no drain-source current Ids, but Ids occurs due to the leakage current I Thus, the voltage at the Q node is discharged. During the touch period, since the drain-source voltage Vds of the transistors T2 and T3 is as high as the difference voltage between VGH and VGL (Vds = Vq - VGL ≒ VGH - VGL), the leakage current (I) in the OFF state of the transistor is generated When the discharging time of the Q node is prolonged, the Q node voltage Vq is lowered, so that the gate driving circuit does not generate a normal output.

In FIG. 4 , CLKB is a clock out of phase with the nth clock CLK. Vqb is the voltage at the QB node.

In the present invention, in order to prevent such leakage current, Vds is minimized (Vds) in the off state (Vgs < Vth) of the transistors T2 and T3 present on the discharge path of the Q node during the touch period as shown in FIGS. 5 to 8 . = 0) to control.

5 to 8 are views showing embodiments of preventing discharge of the Q node in the present invention.

5 and 6 , the present invention prevents discharging of the Q node during a touch period using an alternating current signal, that is, a touch enable signal (VTEN). The touch enable signal VTEN is an AC signal that maintains a low level voltage (=VGL) during a display period and a high level voltage (=VGH) during a touch period.

VGL is applied to the gates of the transistors T1 , T2 , and T3 during the touch period to maintain an off state. Sources of the transistors T1 , T2 , and T3 are supplied with VGH of the touch enable signal VTEN during the touch period. The first transistor T1 charges the Q node to VGH during the touch period. On the other hand, the second and third transistors T2 and T3 are connected to the discharge path of the Q node to suppress discharge of the Q node during the touch period. In this case, the sources of the second and third transistors T2 may be viewed as drains. Accordingly, since the Vds of each of the transistors T1, T2, and T3 is at a minimum (Vds = 0), there is no leakage current through the transistors and the Q node is not discharged.

Meanwhile, when the clock CLK is input, the voltage of the Q node rises to 2VGH. At this time, in order to minimize Vds of the transistor, the voltage of the touch enable signal may also be increased to 2VGH in synchronization with the clock CLK.

During the touch period, since Vds = Vq - VGH ≒ VGH - VGH = 0 in each of the transistors T1, T2, and T3, there is no leakage current. As a result, in the present invention, the voltage Vq of the Q node can be maintained almost as it is during the touch period.

The reason for applying the touch enable signal VTEN to the first transistor T1 is to change the scan direction by changing the clock signal. Among all stages of the shift register, the dummy stage circuit shown in FIGS. 5 and 7 may be applied only to stages where the touch period starts and ends. For the other stages, an existing stage circuit must be used.

The touch enable signal VTEN may have a wider high-level section than the touch section as shown in FIG. 6 in response to a change in the scanning direction of the shift register. When the touch enable signal VTEN and the voltage of the QB node simultaneously rise to a high level (=VGH), the Q node is charged through the third transistor T3 even if the first transistor T1 is not turned on. At an undesired timing, the output Vout may rise to a high level (=VGH). In consideration of this, when the touch enable signal VTEN is extended to be wider than the touch period, it is limited as follows. When the touch enable signal VTEN rises to a high level (=VGH) before one clock pulse width before the start of the touch period or falls to a low level (=VGL) later than one clock pulse width immediately after the touch period ends, Can not be done. One clock pulse width is one pulse width of the gate shift clock CLK applied to the shift register. In other words, when the touch enable signal VTEN extends beyond the touch period, the touch enable signal VTEN rises to the VGH level within one clock pulse width of the start of the touch period, and the touch period ends. Immediately after, it should be polled to the VGL level in a time within one clock pulse width.

7 to 8B , VGH may be applied to the drain of the first transistor T1 . This embodiment may apply the circuit of all stages of the shift register to the circuit shown in FIG. 7 or may be applied only to a specific stage.

The high level section of the touch enable signal VTEN may be set to be the same as the touch section. The touch enable signal VTEN rises to the VGH level at the same time as the start of the touch period and is polled to the VGH level at the same time as the touch period ends.

The example of FIG. 8A is an example of enabling the CLK to a high level first after one touch period ends and before the next display period starts.

The example of FIG. 8B is an example of enabling the CLKB to a high level first after one touch period ends and before the next display period starts. The number of stages of the gate driving circuit to which the touch enable signal VTEN is applied is as much as the number of touch sections set within one frame period. Among these stages, when viewed in one treatment period, there is only one stage that needs to hold the voltage of the Q node, and in the other stages to which the touch enable signal VTEN is applied, the Q node and the QB node are floating. ) can be In this case, if CLK is enabled immediately while the charge of the Q node is introduced due to an external influence, an unwanted output may be generated. Therefore, if CLKB is enabled before CLK is enabled, the Q node will reduce the gate low voltage ( VGL), the QB node is initialized to the gate high voltage (VGH) and then the display period operation is started, thereby increasing the stability of the circuit circuit operation.

The driving device of the present invention may be implemented as an IC (Integrate Circuit) package in the form shown in FIGS. 9 to 11 .

Referring to FIG. 9 , the driving device includes a drive IC (DIC) and a touch IC (TIC).

The drive IC (DIC) includes a touch sensor channel unit 10, a Vcom buffer 11, a switch array 12, a timing control signal generator 13, a multiplexer (MUX) 14, and a DTX compensator ( 15).

The touch sensor channel unit 10 is connected to the pattern electrodes 120 of the touch sensors through the sensing line SL, and is connected to the Vcom buffer 11 and the multiplexer 14 through the switch array 12 . The multiplexer 14 connects the sensing line SL to the touch IC TIC. In the case of the 1:3 multiplexer, the multiplexer 14 reduces the number of channels of the touch IC TIC by time-divisionally connecting one channel of the touch IC TIC to three sensing lines SL. The multiplexer 14 selects sensing lines to be connected to a channel of the touch IC TIC in response to the MUX control signals MUX C1 to C3. The multiplexer 14 is connected to channels of the touch IC (TIC) through touch lines.

The Vcom buffer 11 outputs the common voltage Vcom of the pixel. The switch array 12 supplies the common voltage Vcom from the Vcom buffer 11 to the touch sensor channel unit 10 during the display period under the control of the timing control signal generating unit 13 . The switch array 12 connects the sensing lines SL to the touch IC TIC during the touch period under the control of the timing control signal generator 13 .

The timing control signal generator 13 generates timing control signals for controlling operation timings of the display driving circuit and the touch IC (TIC). The display driving circuit includes a data driving circuit and a gate driving circuit for writing input image data to a pixel. The data driving circuit generates a data voltage and supplies it to data lines of the display panel. The data driving circuit may be integrated in the drive IC (DIC). The gate driving circuit sequentially supplies a gate pulse (or scan pulse) synchronized with the data voltage to the gate lines of the display panel. The gate driving circuit may be disposed together with the pixels on the substrate of the display panel as shown in FIGS. 12 and 15 .

The timing control signal generator 13 is substantially the same as the timing control signal generator in the timing controller 400 shown in FIG. 12 . The timing control signal generator 13 drives the display driving circuit during the display period and drives the touch IC (TIC) during the touch period.

The timing control signal generator 13 synchronizes the display driving circuit and the touch IC (TIC) by generating a touch enable signal (Touch EN) defining a display section and a touch section. The display driving circuit writes data to the pixels during the first level period of the touch enable signal Touch EN. The touch IC senses a touch input by driving touch sensors in response to the second level of the touch enable signal Touch EN. The first level of the touch enable signal Touch EN may be a low level, and the second level may be a high level, but vice versa.

The touch enable signal VTEN suppressing discharge of the Q node of the gate driving circuit is generated based on the digital logic level touch enable signal Touch EN generated from the timing control signal generator 13 . The timing control signal generator 13 modulates the touch enable signal Touch EN by further extending the second level section of the touch enable signal Touch EN forward and backward by a width within one clock pulse width, as shown in FIG. The timing of the touch enable signal VTEN may be defined or the timing of the touch enable signal VTEN as shown in FIG. 8 may be defined by using the touch enable signal Touch EN as it is. A level shifter (not shown) cannot control the MOSFET of the gate driving circuit with the digital logic level touch enable signal (Touch EN) output from the timing control signal generator 13, so the touch enable signal ( Touch EN) level is shifted to generate a touch enable signal VTEN that swings between VGH and VGL. The level shifter shifts the levels of the gate start pulse VST and the gate shift clock CLK of the digital logic level output from the timing control signal generator 13 to VGH and VGL. The touch enable signal VTEN, the gate start pulse VST, and the gate shift clock CLK are supplied from the level shifter to the shift register of the gate driving circuit.

Noise may increase in the touch sensor signal according to a change in input image data. The DTX compensator 15 analyzes the input image data, removes the noise component from the touch raw data (TDATA) according to the gradation change of the input image, and transmits it to the touch IC (TIC). DTX means Display and Touch crosstalk. Since the DTX compensator 15 is not required in the case of a system in which the noise of the touch sensor does not change sensitively according to the data change of the input image, it can be omitted. In FIG. 9 , DTX DATA is output data of the DTX compensator 15 .

The touch IC TIC drives the multiplexer 14 during the touch period in response to the touch enable signal Touch EN from the timing control signal generator 13 through the multiplexer 14 and the sensing lines SL. Receive the charge of the touch sensor. In FIG. 9, MUXs C1 to C3 are signals for selecting channels of the multiplexer.

The touch IC (TIC) detects the amount of change in charge before and after the touch input from the received signal of the touch sensor, compares the amount of change in the phone with a predetermined threshold, and determines the positions of the touch sensors having the amount of change in charge greater than or equal to the threshold as the touch input area. . The touch IC (TIC) transmits touch data including touch input coordinate information to an external host system by calculating coordinates for each touch input. A touch IC (TIC) includes an amplifier that amplifies the charge of the touch sensor, an integrator that accumulates the charge received from the touch sensor, an analog to digital converter (ADC) that converts the voltage of the integrator into digital data, and an arithmetic logic unit. The operation logic unit compares the touch raw data output from the ADC with a threshold value, determines a touch input according to the comparison result, and executes a touch recognition algorithm that calculates coordinates.

The drive IC (DIC) and the touch IC (TIC) may transmit and receive signals through a Serial Peripheral Interface (SPI) interface.

The host system refers to a system body of an electronic device to which the display device of the present invention is applicable. The host system may be any one of a phone system, a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), and a home theater system. The host system transmits input image data to the drive IC (DIC), receives the touch input data from the touch IC (TIC), and executes an application related to the touch input.

Referring to FIG. 10 , the driving device includes a drive IC (DIC) and a micro controller unit (MCU).

The drive IC (DIC) includes a touch sensor channel unit 10 , a Vcom buffer 11 , a switch array 12 , a first timing control signal generator 13 , a multiplexer 14 , a DTX compensator 15 , and sensing a unit 16 , a second timing control signal generating unit 17 , and a memory 18 . This embodiment is different from the above-described embodiment of FIG. 9 in that the sensing unit 16 and the second timing control generating unit 17 are integrated in the drive IC (DIC). The first timing control generating unit 13 is substantially the same as that of FIG. 9 . Accordingly, the first timing control generator 13 generates timing control signals for controlling operation timings of the display driving circuit and the touch IC (TIC).

The sensing unit 16 includes an amplifier for amplifying the charge of the touch sensor, an integrator for accumulating the charge received from the touch sensor, and an ADC for converting the voltage of the integrator into digital data. Touch raw data (TDATA) output from ADC is transmitted to MCU. The second timing control generating unit 17 generates a timing control signal, a clock, and the like for controlling the operation timing of the multiplexer 14 and the sensing unit 16 . In the drive IC (DIC), the DTX compensator 15 may be omitted. The memory 18 temporarily stores the touch raw data TDATA under the control of the second timing control generator 17 .

The drive IC (DIC) and the MCU may transmit and receive signals through an SPI (Serial Peripheral Interface) interface. The MCU executes a touch recognition algorithm that compares the raw touch data (TDATA) with a threshold value, determines a touch input according to the comparison result, and calculates coordinates.

Referring to FIG. 11 , the driving device includes a drive IC (DIC) and a memory (Memory, MEM).

The drive IC (DIC) includes a touch sensor channel unit 10 , a Vcom buffer 11 , a switch array 12 , a first timing control signal generator 13 , a multiplexer 14 , a DTX compensator 15 , and sensing It includes a unit 16 , a second timing control signal generating unit 17 , a memory 18 , and an MCU 19 . This embodiment is different from the embodiment of Fig. 10 described above in that the MCU 19 is integrated in the drive IC (DIC). The MCU 19 compares the touch raw data TDATA with a threshold value, determines a touch input according to the comparison result, and executes a touch recognition algorithm for calculating coordinates.

The memory MEM stores a register setting value related to timing information required for the operation of the display driving circuit and the sensing unit 16 . When the power of the register setting value display device is turned on from the memory MEM, the first timing control signal generator 16 and the second timing control signal generator 17 are loaded. The first timing control signal generating unit 16 and the second timing control signal generating unit 17 generate timing control signals for controlling the display driving circuit and the sensing unit 16 based on the register setting value read from the memory. do. It is possible to respond to the model change by changing the register setting value of the memory (MEM) without structural change of the driving device.

12 is a view showing a touch panel integrated display device and a driver thereof according to an embodiment having one gate driving circuit, and FIG. 13 is a view showing a plurality of pixels and corresponding pattern electrodes of the display panel. , FIG. 14 is a diagram illustrating a connection relationship between a pattern electrode and a sensing line. And FIG. 15 is a view showing a touch panel integrated display device including two gate driving circuits and a driving unit thereof according to an embodiment.

As shown, the display device of the present invention includes a display panel 100 that displays an image, a timing controller 400 that receives a timing signal from a host system to generate various control signals, and a display panel ( The gate driving circuit 200 and the data driving circuit 300 for controlling the 100 , and a touch driving circuit 500 for driving a touch are included.

In the display panel 100 , K gate lines GL and a plurality of data lines DL cross each other in a matrix form on a substrate using glass (where K is a natural number), and a plurality of pixels 110 are formed at the intersection points. define. Each pixel 110 is provided with a thin film transistor TFT, a liquid crystal capacitor Clc, and a storage capacitor Cst, and all pixels 110 form one display area A/A. An area in which the pixel 110 is not defined is divided into a non-display area N.

In addition, the display panel 100 has a built-in touch screen, and the touch screen performs a function of detecting the user's touch position. can do. And, as shown in FIG. 13 , the display panel 100 groups all the pixels 110 into a plurality of pixel groups, and may further include a plurality of pattern electrodes 120 corresponding to each group in a 1:1 ratio. Also, as shown in FIG. 14 , the plurality of pattern electrodes 120 may be connected to the touch driving circuit 500 through the sensing line SL.

A common voltage may be applied to the pattern electrode 120 to drive the display of the display panel 100 , and accordingly, it may operate as a common electrode for driving liquid crystal together with the pixel electrode. In addition, a touch scan signal may be applied to the pattern electrode 120 for touch sensing, and accordingly, the pattern electrode 120 may operate as a touch electrode sensing a touch position. For example, since it is a touch screen-integrated display device according to an embodiment of the present invention, the display driving and the touch driving are temporally divided within one frame to be driven, and if the driving mode of the display panel 100 is the display driving mode, The plurality of pattern electrodes 120 receive a common voltage and operate as a common electrode for driving the display together with the pixel electrode. It operates as a touch electrode for sensing a touch position by receiving a signal. Here, the common voltage may be applied from the touch driving circuit 500 or may be provided with a separate common voltage generator and directly applied to the display panel 100 without going through the touch driving circuit 500 .

In addition, the touch driving circuit 500 includes a touch scan signal generating unit that generates a touch scan signal, a touch sensing unit that detects whether a touch is made by using a difference between the received touch sensing signals, and a common voltage or a touch scan signal to the plurality of electrodes. It may be configured to include a switching unit that applies , receives a touch sensing signal generated by the touch scan signal from the plurality of pattern electrodes 120 , and detects whether or not there is a touch by using a difference between the received touch sensing signals.

Meanwhile, the pattern electrodes 120 may be grouped and sequentially operated for each group during one frame, and the number of pattern electrodes 120 constituting the group may be varied in consideration of the touch driving time and the display driving time.

The timing controller 400 transmits the input image signal RGB received from the host system to the data driving circuit 200 . The timing controller 400 uses timing signals such as a clock signal DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE received together with the input image signal RGB. A timing control signal for controlling operation timings of the gate driving circuit 200 and the data driving circuit 300 is generated.

Here, the horizontal sync signal Hsync is a signal representing the time taken to display one horizontal line of the screen, and the vertical sync signal Vsync is a signal representing the time taken to display the screen of one frame. Also, the data enable signal DE is a signal indicating a period in which the data voltage is supplied to the pixels defined in the display panel 100 .

Also, the timing controller 400 generates a control signal GCS of the gate driving circuit 200 and a control signal DCS of the data driving circuit 300 in synchronization with an input timing signal.

In addition, the timing controller 400 generates a plurality of clock signals for determining driving timing of each stage of the gate driving circuit 200 and provides them to the gate driving circuit 200 . In addition, the timing controller 400 aligns and modulates the input image data RGB DATA in a form that the data driving circuit 300 can process, and outputs it. Here, the aligned image data may be in a form to which a color coordinate correction algorithm for image quality improvement is applied.

Also, the timing controller 400 generates a touch enable signal Touch EN for driving a touch. The touch enable signal Touch EN is provided to the touch driving circuit 500 . The touch enable signal Toch EN is supplied to the gate driving circuit 200 through the level shifter 402 . Driving Circuit The touch driving circuit 500 is driven while a high level touch enable signal Touch EN is supplied to sense a touch input.

Next, the data driving circuit 300 shifts a source start pulse (SSP) from the timing controller 400 according to a source shift clock (SSC) to generate a sampling signal. In addition, the data driving circuit 300 latches image data input according to the source shift clock SSC according to the sampling signal, converts it into a data signal, and responds to a Source Output Enable (SOE) signal. Thus, the data signal is supplied to the data lines DL in units of horizontal lines. To this end, the data driving circuit 300 may include a data sampling unit, a latch unit, a digital-to-analog converter, and an output buffer.

Next, the gate driving circuit 200 shifts the gate start pulse (GSP) transmitted from the timing controller 400 according to the gate shift clock (GSC), and sequentially the gate wiring ( A gate pulse of VGH level is supplied to GL 1 to GL n), and a gate low voltage VGL is supplied to the gate lines GL 1 to GL n during the remaining period when the gate pulse is not supplied.

On the other hand, the gate driving circuit 200 applied to the present invention may be formed independently of the panel and may be configured to be electrically connected to the panel in various ways, but the gate driving circuit 200 is the display panel ( 100), it may be embedded in the non-display area N in the form of a thin film pattern in a gate-in-panel (GIP) method. In this case, the gate control signal for controlling the gate driving circuit 200 may be a clock signal CLK and a start signal VST for driving the first stage of the shift register.

Referring to FIG. 15 , two gate driving circuits 200 may be provided at both ends of the display panel 100 and in the non-display area N. As shown in FIG. The first and second gate driving circuits 200a and 200b include a plurality of stages including shift registers. The first and second gate driving circuits 200a and 200b are formed in the display panel 100 in response to a gate control signal GCS input from the timing controller 400 through a plurality of gate lines GL1 to GLn. It is possible to output the gate pulses alternately. Here, the output gate pulses may overlap for a predetermined horizontal period. This is for precharging the gate lines GL 1 to GL n, and more stable pixel charging may be performed when a data voltage is applied.

16A, 16B, 17A, and 17B are diagrams illustrating a connection relationship between a plurality of stages constituting a shift register according to different embodiments of the present invention. 18A is a diagram illustrating forward and reverse gate scans of a plurality of stages constituting the shift register according to FIGS. 16A and 17A . 18B is a diagram illustrating forward and reverse gate scans of a plurality of stages constituting the shift register according to FIGS. 16B and 17B. 19 is a time flow diagram illustrating display and touch time division driving.

As illustrated in FIG. 18A , the stages are driven in the order of B, C (dummy stage), and A when driving in the forward direction, and the stages are driven in the order of A, C (dummy stage) and B when driving in the reverse direction. And during forward driving, B is a stage outputting the last gate pulse before touch driving, C is a dummy stage and holding stage in which the Q node maintains a charged state during the touch driving period, and A is a stage that outputs the first gate pulse after touch driving is completed It is a stage to And, during forward driving, A is a stage that outputs the last gate pulse before touch driving, C is a dummy stage, and is a holding stage in which the Q node maintains a charged state during touch driving, and B is a stage that outputs the first gate pulse after touch driving is completed It is a stage to

As shown in FIG. 18B , the stages are driven in the order of B and A when driving in the forward direction, and the stages are driven in the order of A and B when driving in the reverse direction. And, during forward driving, B is a stage outputting the last gate pulse before touch driving, A is a holding stage in which the Q node maintains a charged state during touch driving, and is a stage outputting the first gate pulse after touch driving is terminated. And, during forward driving, A is a stage outputting the last gate pulse before touch driving, B is a holding stage in which the Q node maintains a charged state during touch driving, and outputting the first gate pulse after touch driving is terminated.

18C is an example in which there is no dummy stage when the gate scan direction is scanned unidirectionally (forward). A is a holding stage in which the Q node maintains a charged state during touch driving, and a stage for outputting the first gate pulse after touch driving is terminated.

18D is an example in which the dummy stage C is added when the gate can be driven in both directions (forward and forward).

For convenience of explanation, the connection relationship of the N-th stage among the plurality of stages ((N is a natural number, the N-th stage means the N-th stage) and the VGH level gate pulse output from the N-th stage to the corresponding gate wiring will be explained based on

<first and third shift Register>

16A and 16B , the shift register 210 according to the first and second embodiments is a shift register included in the gate driving circuit 200 according to the first embodiment as shown in FIG. 1 , and FIGS. 17A and 17A and FIG. Referring to 17b , the shift registers 210 according to the third and fourth embodiments are shift registers included in the gate driving circuits 200a and 200b according to the second embodiment as shown in FIG. 15 .

As a plurality of stages constituting the shift register 210 according to the first and third embodiments shown in FIGS. 16A and 17A , N, N+1, N+2, and a dummy stage are shown.

Each of the N, N+1, and N+2 stages includes a clock signal line CLK, a first clock signal line CLK1 and a shift register included in the gate driving circuits 200a and 200b according to the second embodiment. At least two clock signals may be applied from the second clock signal line CLK 2 . In addition, one of the output signals of the adjacent stage may be applied as a start signal and the other may be applied as a reset signal.

In addition, the dummy stage may receive at least two clock signals from the clock signal line CLK and may receive touch enable signals VTEN, VTEN1, and VTEN2 driving circuits from the touch enable signal line. In addition, one of the output signals of the adjacent stage may be applied as a start signal VST and the other may be applied as a reset signal RST.

The stages may perform an operation for supplying a gate pulse when receiving the start signal VST, and perform an operation for discharging the gate line GL when receiving the reset signal RST.

Specifically, the N-th stage includes a start signal (VST) input terminal and a reset signal (RST) input terminal, and receives the gate pulse output from the output terminal (G(n-1)) of the N-1th stage, which is the previous stage. Receive the start signal VST input terminal, and receive the carry signal Vc output from the output terminal G(n+1/2) of the dummy stage, which is the next stage, to the reset signal RST input terminal can

The dummy stage includes a start signal VST input terminal and a reset signal RST input terminal, and receives a gate pulse output from an output terminal G(n) of an N-th stage that is a previous stage as the start signal VST input terminal. The input terminal may receive a scan signal output from the output terminal G(n+1) of the N+1th stage, which is the next stage, and may receive the scan signal outputted from the reset signal RST input terminal.

In particular, the dummy stage can maintain the voltage charged in the Q node while preventing leakage current by using the touch enable signal TEN of VGH level during the touch driving period, and applied to the dummy stage at the end of the touch driving period. The carry signal Vc may be output to the output terminal G(n+1/2) in response to the clock signal of the VGH level, and may be provided to the next stage, the N+1 stage.

The N+1th stage includes a start signal (VST) input terminal and a reset signal (RST) input terminal, and a carry signal Vc output from an output terminal (G(n+1/2)) of a dummy stage that is a previous stage ) is input to the start signal VST input terminal, and a scan signal output from the output terminal G(n+2) of the N+2th stage, which is the next stage, is input to the reset signal RST input terminal. can

The N+2th stage includes a start signal (VST) input terminal and a reset signal (RST) input terminal, and receives a gate pulse output from an output terminal (G(n+1)) of an N+1th stage, which is a previous stage. A scan signal output from an output terminal G(n+3) of an N+3 th stage that is a next stage may be input through the start signal VST input terminal and may be inputted through the reset signal RST input terminal. .

As described above, the shift register 210 according to an embodiment of the present invention may include a plurality of dummy stages. For example, as shown in FIG. 18A , the first to 64th stages for sequentially supplying gate pulses to the first to 64th gate lines GL1 to GL64 and gate pulses to the 65th to 128th gate lines GL65 to GL128 may include one dummy stage disposed between the 65th to 128th stages for sequentially supplying the . However, although the gate wirings GLs are grouped by 64, the present invention is not limited thereto. Stages corresponding to the gate wirings to be activated during one display period among a plurality of display periods within one frame are grouped as shown in FIG. Each of the dummy stages may be included in the .

Meanwhile, the above description has been described with reference to the forward operation in the order of the first stage to the last stage, but the present invention is not limited thereto. After the pulse output, the dummy stage may operate, and then the Nth stage may operate.

Meanwhile, the plurality of stages may output a gate pulse to any one of the plurality of gate lines GL 1 to GL n in synchronization with any one of the clock signals CLK.

In addition, each of all stages may receive a high potential power supply (VDD) from a high potential power supply terminal and VGL, a forward power supply (FWD) and a reverse power supply (REV) from a low potential power supply terminal, and all dummy stages each A touch enable signal may be supplied. The forward power supply FWD is generated at the VGH level in the forward scan mode and is generated at the VGL level in the reverse scan mode. Conversely, the reverse power supply REV is generated at the VGH level in the reverse scan mode and is generated at the VGL level in the forward scan mode.

<Second and Fourth shift Register>

N, N+1, N+2 and N+3 are shown as a plurality of stages constituting the shift register 210 according to the second and fourth embodiments according to FIGS. 16B and 17B.

Each of the N, N+1, and N+2 stages includes a first clock signal line CLK 1 and At least two clock signals may be applied from the second clock signal line CLK 2 . The first and second clock signals may have opposite logic levels. In addition, one of the output signals of the adjacent stage may be applied as a start signal VST and the other may be applied as a reset signal RST.

Also, some stages among the plurality of stages function as standby stages, and are stages that need to maintain the Q node voltage during the touch driving period. The standby stage may receive at least two clock signals from the clock signal line CLK and may receive touch enable signals VTEN, VTEN1, and VTEN2 from the touch enable signal line. In addition, one of the output signals of the adjacent stage may be applied as a start signal VST and the other may be applied as a reset signal RST.

The stages may perform an operation for supplying a gate pulse when receiving the start signal VST, and perform an operation for discharging the gate line GL when receiving the reset signal RST.

Specifically, the N-th stage includes a start signal (VST) input terminal and a reset signal (RST) input terminal, and receives the gate pulse output from the output terminal (G(n-1)) of the N-1th stage, which is the previous stage. A scan signal output from an output terminal G(n+1) of an N+1-th stage that is a next stage may be input to the reset signal RST input terminal and may be input to the start signal VST input terminal. .

The N+1th stage includes a start signal (VST) input terminal and a reset signal (RST) input terminal, and receives a scan signal output from an output terminal (G(n)) of the previous stage, the Nth stage, as the start signal ( VST) input terminal, and a scan signal output from an output terminal G(n+2) of an N+2th stage that is a next stage may be input through the reset signal RST input terminal.

The N+2th stage includes a start signal (VST) input terminal and a reset signal (RST) input terminal, and receives a gate pulse output from an output terminal (G(n+1)) of an N+1th stage, which is a previous stage. A scan signal output from an output terminal G(n+3) of an N+3 th stage that is a next stage may be input through the start signal VST input terminal and may be inputted through the reset signal RST input terminal. .

In particular, the N+1th stage set as the standby stage among the plurality of stages can maintain the voltage charged in the Q node while preventing leakage current by using the touch enable signal VTEN of VGH level during the touch driving period, and touch driving. At the end of the period, a gate pulse may be output to the output terminal G(n+1) in response to the clock signal of the VGH level applied to the N+1th stage, and provided to the N+2 stage, which is the next stage.

As described above, the shift register 210 according to the embodiment of the present invention may include a plurality of standby stages. For example, as shown in FIG. 18B , the first to 64th stages for sequentially supplying gate pulses to the first to 64th gate lines GL1 to GL64 and gate pulses to the 65th to 128th gate lines GL65 to GL128 In the 65th to 128th stages for sequentially supplying , the 65th stage may be a standby stage. However, although the gate lines GL are grouped by 64, the present invention is not limited thereto and may be set differently in consideration of the touch driving time and the driving time period.

Meanwhile, the plurality of stages may output a gate pulse to any one of the plurality of gate lines GL 1 to GL n in synchronization with any one of the clock signals CLK.

In addition, each of the plurality of stages may receive a high potential power supply (VDD) from a high potential power supply terminal and VGL, a forward power supply (FWD) and a reverse power supply (REV) from a low potential power supply terminal, and each of the standby stages may receive a touch enable signal.

< Nth on stage Schematic>

20 is a circuit diagram of an Nth stage constituting a shift register according to an embodiment of the present invention.

Referring to FIG. 20 , the N-th stage is one of stages for charging a Q node during a display period other than a standby stage or a dummy stage and sequentially outputting scan pulses in synchronization with an input clock signal. The N-th stage may include a pull-up transistor Tup, a pull-down transistor Tdown, and a first capacitor CQ and a second capacitor CQB, and additionally a charging/discharging unit 211 and a Q-node stabilizing unit 212 . may include.

When explaining the connection relationship of the above-described components constituting the N-th stage, the gate terminal of the pull-up transistor Tup is connected to the Q node, the drain terminal is connected to the supply terminal of the first clock signal CLK 1 , and the source The terminal may be connected to the output terminal G(n) of the Nth stage. And the gate terminal of the pull-down transistor Tdown for stably discharging the output terminal during the discharge period is connected to the QB node, the drain terminal is connected to the output terminal G(n) of the Nth stage, and the source terminal is VGL can be connected to the input terminal of In addition, the first capacitor CQ may be connected to the QB node and the input terminal of the VGL. In addition, the second capacitor CQB may be connected to the Q node and the input terminal of the VGL.

Also, the charging/discharging unit 211 may function to charge or discharge the Q node. and first and second transistors T1 and T2, a gate terminal of the first transistor T1 is connected to an output terminal G(n-1) of an N-1 th stage, and a drain The terminal may be connected to the input terminal of the forward power source (FWD), and the source terminal may be connected to the Q node. And the gate terminal of the second transistor T2 is connected to the output terminal G(n+1) of the N+1th stage, the drain terminal is connected to the input terminal of the reverse power supply REV, and the source terminal is Q It can be connected to a node.

In addition, the Q node stabilizing unit 212 functions to discharge the Q node and may include a third transistor T3, a gate terminal of the third transistor T3 is connected on the QB node, and the QB The node may be connected to a terminal supplying a voltage for turning on the third transistor T3 in synchronization with the timing of discharging the Q node or the output signal of the next stage or the second clock signal CLK2 is supplied to the node as shown in the figure. . And the drain terminal may be connected to the Q node, and the source terminal may be connected to the input terminal of VGL. In the second clock signal, when the first transistor T1 is turned on and the Q node is charged, the third transistor T3 is turned off, and a gate pulse is output to the corresponding output terminal according to the bootstrap of the Q node, When discharging the Q node immediately after birth, the third transistor T3 may be a clock signal having a level and timing to be controlled so that it can be turned on.

21 is a circuit diagram of a standby stage.

<Standby stage >

Referring to FIG. 21 , the standby stage is a standby stage applied to the shift register of FIG. 16B or 17B , and maintains the Q node voltage charged in the touch driving period and synchronizes with a clock signal inputted when the touch driving is terminated. It is a stage that outputs a gate pulse to the output stage. The standby stage may include a pull-up transistor Tup, a pull-down transistor Tdown, and a first capacitor CQ and a second capacitor CQB, and additionally a charging/discharging unit 211 and a Q-node stabilizing unit 212 . may include

When explaining the connection relationship of the above-described components constituting the N-th stage as the standby stage, the gate terminal of the pull-up transistor Tup is connected to the Q node, and the drain terminal of the pull-up transistor Tup is the supply terminal of the first clock signal CLK 1 . connected to and a source terminal may be connected to the output terminal G(n) of the Nth stage, a gate terminal of the pull-down transistor Tdown may be connected to a QB node, and a drain terminal may be connected to an output terminal G(n) of the Nth stage. n)), and the source terminal may be connected to the input terminal of VGL. In addition, the first capacitor CQ may be connected to the QB node and the input terminal of VGL. In addition, the second capacitor CQB may be connected to the Q node and the input terminal of VGL.

Also, the charging/discharging unit 211 may function to charge or discharge the Q node. and first and second transistors T1 and T2, a gate terminal of the first transistor T1 is connected to an output terminal G(n-1) of an N-1 th stage, and a drain The terminal may be connected to the input terminal of the touch enable signal VTEN or the forward power supply FWD, and the source terminal may be connected to the Q node. And the gate terminal of the second transistor T2 is connected to the output terminal G(n+1) of the N+1th stage, the drain terminal is connected to the input terminal of the touch enable signal VTEN, and the source terminal may be connected to the Q node.

In addition, the Q node stabilizing unit 212 functions to discharge the Q node and may include a third transistor T3 , and a gate terminal of the third transistor T3 has a second clock signal CLK2 supply terminal. , the drain terminal may be connected to the Q node, and the source terminal may be connected to the input terminal of the touch enable signal VTEN.

22 is a circuit diagram of a dummy stage.

<dummy stage >

Referring to FIG. 22 , the dummy stage is a stage applied to the shift register of FIG. 16A or 17A , and is a dummy stage disposed between an Nth stage and an N+1th stage. The dummy stage may include a pull-up transistor Tup, a pull-down transistor Tdown, and a first capacitor CQ and a second capacitor CQB, and additionally includes a charging/discharging unit 211 and a Q-node stabilizing unit 212 . may include

When describing the connection relationship of the above-described components constituting the dummy stage, a gate terminal of the pull-up transistor Tup is connected to a Q node, a drain terminal is connected to a supply terminal of the first clock signal CLK 1 , and a source terminal may be connected to the output terminal G(n+1/2) of the dummy stage, the gate terminal of the pull-down transistor Tdown is connected to the QB node, and the drain terminal of the pull-down transistor Tdown is the output terminal G(n+1) of the dummy stage /2)), and the source terminal may be connected to the input terminal of VGL. In addition, the first capacitor CQ may be connected to the QB node and the input terminal of VGL. In addition, the second capacitor CQB may be connected to the Q node and the input terminal of VGL.

Also, the charging/discharging unit 211 may function to charge or discharge the Q node. and first and second transistors T1 and T2, wherein a gate terminal of the first transistor T1 is connected to an output terminal G(n) of an N-th stage, and a drain terminal of the first transistor T1 is touch-in. It may be connected to the input terminal of the enable signal VTEN, and the source terminal may be connected to the Q node. And the gate terminal of the second transistor T2 is connected to the output terminal G(n+1) of the N+1th stage, the drain terminal is connected to the input terminal of the touch enable signal VTEN, and the source terminal may be connected to the Q node.

In addition, the Q node stabilizing unit 212 functions to discharge the Q node and may include a third transistor T3 , and a gate terminal of the third transistor T3 has a second clock signal CLK2 supply terminal. , the drain terminal may be connected to the Q node, and the source terminal may be connected to the input terminal of the touch enable signal VTEN.

< on stage Forward and reverse driving method>

23 is a diagram illustrating the Q node charging and gate pulse output operation of the Nth stage in the forward driving, and FIG. 24 is a diagram showing the Q node discharging and the QB node charging of the Nth stage in the forward driving.

<Display driving section: forward driving>

During the first time period of the display driving period T1, the first transistor T1 is turned on by the output signal of the N-1 th stage, the forward power FWD is supplied to the Q node, and the first clock signal CLK 1 ) as the pull-up transistor Tup is turned on according to the bootstrap by the VGH level of the VGH level, a gate pulse of the VGH level may be output to the output terminal G(n) of the N-th stage.

During a second time period following the first time period of the display driving period T1, the second transistor T2 is turned on by the output signal of the N+1th stage, and the reverse power REV is supplied to the Q node. As the Q node is discharged and the second clock signal CLK 2 of the VTH level charges the QB node, the third transistor T3 and the pull-down transistor Tdown are turned on, and the Q node and the output terminal G( n)) can each be discharged by VGL.

25 is a diagram illustrating the Q node charging and gate pulse output operation of the Nth stage in the reverse driving, and FIG. 26 is a diagram showing the Q node discharging and the QB node charging of the Nth stage in the reverse driving.

<Display driving section: reverse driving>

During the first time period of the display driving period T1, the second transistor T2 is turned on by the output signal of the N+1th stage, the reverse power REV is supplied to the Q node, and the first clock signal CLK 1 ) as the pull-up transistor Tup is turned on according to the bootstrap by the VGH level of the VGH level, a gate pulse of the VGH level may be output to the output terminal G(n) of the N-th stage.

During the second time period following the first time period during the display driving period T1, the first transistor T1 is turned on by the output signal of the N-1 th stage and the forward power FWD is supplied to the Q node. As the Q node is discharged, the third transistor T3 and the pull-down transistor Tdown are turned on while the second clock signal CLK 2 of the VGH level charges the QB node, the Q node and the output terminal G( n)) can each be discharged by VGL.

On the other hand, each of the first and second transistors T1 and T2 operates only one of them according to the forward or reverse operation of the gate driving circuit 200 to provide the forward power FWD or the reverse power REV to the Q node. In addition, when driving in the forward direction, the forward power supply FWD may have a higher voltage than the reverse power supply REV, and when driving in the reverse direction, the forward power supply FWD may have a higher voltage than the reverse power supply REV.

<Standby on stage Forward drive method>

FIG. 27 is a diagram illustrating charging of the Q node of the Nth stage as a standby stage in forward driving, FIG. 28 is a diagram illustrating a holding period for maintaining the Q node voltage, and FIG. 29 is a diagram illustrating a gate pulse output operation. 30 is a diagram illustrating discharging operations of the Q node and the output terminal. And FIG. 31 is a waveform diagram when the standby stage is driven.

-Q node charge period (Charge)

27 and 31 , during the display driving period T1 just before the touch driving period T2 starts, a gate pulse is output from the N-1 th stage, and the touch enable signal VTEN reaches the VGH level. can be transferred At this time, the first transistor T1 is turned on by the output signal from the N-1 th stage and the touch enable signal VTEN transitioned to the VGH level is supplied to the Q node to charge the Q node.

-Q node voltage holding period (Holding Time=Touch Time)

28 and 31 , the touch driving period T2 starts, and the charged voltage on the Q node is maintained during the touch driving period. At this time, since the touch enable signal VTEN maintains the VGH level, a voltage of VGH level is supplied to the source terminal of the first transistor T1, and a voltage of VGH level is also supplied to the drain terminal of the second transistor T2. and a voltage of the VGH level is also supplied to the source terminal of the third transistor T3. As such, the path between the source-drain terminals of the first to third transistors T1, T2, and T3 through which the leakage current may flow may be removed by supplying high potential power to their source or drain terminals. .

-Output period

29 and 31 , in the display driving period T3 immediately following the type of the touch driving period T2, the pull-up transistor Tup according to the bootstrap by the VGH level of the first clock signal CLK 1 . As is turned on, the gate pulse of the VGH level may be stably output to the output terminal G(n) of the N-th stage.

-discharge period ( Dis -Charge)

30 and 31 , during the discharge period following the output period, the second transistor T2 is turned on by the output signal of the N+1-th stage, and the touch enable signal VTEN, which is at the VGL level, becomes the Q node. is supplied to the Q node, the Q node is discharged, and the third transistor T3 and the pull-down transistor Tdown are turned on while the second clock signal CLK 2 of the VGH level charges the QB node, and the Q node and the output terminal of the N-th stage (G(n)) can each be discharged by VGL.

<dummy on stage Forward drive method>

FIG. 32 is a diagram illustrating charging of a Q node of a dummy stage in forward driving, FIG. 33 is a diagram illustrating a holding period for maintaining a Q node voltage, and FIG. 34 is a diagram illustrating a gate pulse output operation. Also, FIG. 35 is a diagram illustrating discharging operations of the Q node and the output terminal. And FIG. 36 is a waveform diagram when the dummy stage is driven.

-Q node charge period (Charge)

32 and 36 , a gate pulse is output from the N-th stage during the first time period of the display driving period T1 immediately before the touch driving period T3 starts, and the touch enable signal VTEN is Transition to VGH level is possible. At this time, the first transistor T1 is turned on by the output signal from the N-th stage and the touch enable signal VTEN transitioned to the VGH level is supplied to the Q node to charge the Q node.

-Q node voltage holding time

Referring to FIGS. 33 and 36 , the touch driving period T2 starts, and the charged voltage on the Q node is maintained during the touch driving period. At this time, since the touch enable signal VTEN maintains the VGH level, a voltage of VGH level is supplied to the source terminal of the first transistor T1, and a voltage of VGH level is also supplied to the drain terminal of the second transistor T2. and a voltage of the VGH level is also supplied to the source terminal of the third transistor T3. As such, the path between the source-drain terminals of the first to third transistors T1, T2, and T3 through which the leakage current may flow may be removed by supplying high potential power to their source or drain terminals. .

-Output period

34 and 36 , at the end of the touch driving period T3, the pull-up transistor Tup is turned on according to the bootstrap by the VGH level of the first clock signal CLK 1 and the output terminal of the dummy stage ( The carry signal Vc of the VGH level may be stably output to G(n+1/2)).

-discharge period ( Dis -Charge)

35 and 36 , in the display driving period T3 following the output period, the second transistor T2 is turned on by the output signal of the (N+1)th stage during the discharge period and the touch-in is at the VGL level. As the enable signal VTEN is supplied to the Q node, the Q node is discharged, and as the second clock signal CLK 2 of the VGH level charges the QB node, the third transistor T3 and the pull-down transistor Tdown are turned on. The output terminals G(n+1/2) of the node and the dummy stage may be respectively discharged by VGL.

On the other hand, in the case of the shift registers according to the second and fourth embodiments, when a standby stage having a holding state during the touch driving period is used without including a separate dummy stage, the Q node voltage holding period (Holding Time) is the touch driving period. However, in the case of the shift registers according to the first and third embodiments, since a dummy stage having a holding state is used during the touch driving period, the entire Q node voltage holding period (Holding Time) and the output period (Output) are the touch driving period. do.

37 is a waveform diagram illustrating a Q node voltage when a standby stage or a dummy stage is operated.

Referring to FIG. 37 , the standby or dummy stage is a high-potential power source VGH level touch-in to the source or drain terminal opposite to the Q node in the path between the source-drain terminal through which the charged charge on the Q node can easily escape. By supplying the enable signal VTEN, the Q node voltage can be maintained so that it does not drop, and it can be made to rise to a higher voltage even during bootstrap. Therefore, since the gate pulse of the VGH level is output, it is possible to remove the dim phenomenon, which is a horizontal line visibility phenomenon.

As described above, since the voltage of the Q node of the standby stage or the dummy stage can be maintained in the touch driving period, the number of touch driving periods can be reduced during one frame and the time length of one touch driving period can be increased. In addition, it is possible to secure a clock time (CLK time) at high resolution by adding a margin time between the display driving section and the touch driving section.

Meanwhile, although the transistor of the stage and the thin film transistor (TFT) of the display panel 100 have been described based on the N type, the present invention is not limited thereto, and the first to third transistors T1, T2, and T3 of the stage and the pull-up and pull-down The transistors Tup and Tdown and the thin film transistor TFT of the display panel 100 may all be P-type. In this case, the high or low logic level of all the above-described signals becomes a low or high logic level on the contrary, and accordingly, a leakage current is generated between the source and drain terminals of the first to third transistors T1, T2, and T3. By maintaining the potential difference so as not to prevent leakage of current, it is possible to stably maintain the voltage of the Q node during the touch driving period.

In the detailed description of the present invention described above, although it has been described with reference to preferred embodiments of the present invention, those skilled in the art or those having ordinary knowledge in the art will It will be understood that various modifications and variations of the present invention can be made without departing from the spirit and scope of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be defined by the claims.

10: display device
100: display panel
110: pixel
120: pattern electrode
200: gate driving circuit
200a: first gate driving circuit
200b: second gate driving circuit
210: shift register
211: charge/discharge unit
212: stabilization part
300: data driving circuit
400: timing controller
500: touch driving circuit

Claims (20)

a display panel in which data lines and gate lines cross, pixels are arranged in a matrix, and touch sensors;
a touch driving circuit for driving the touch sensors;
a data driving circuit for supplying a data signal to the data lines;
a gate driving circuit for supplying a gate pulse to the gate wirings using a shift register; and
a timing controller for supplying input image data to the data driving circuit and controlling operation timings of the data driving circuit and the gate driving circuit,
The timing controller generates a touch enable signal defining a display section and a touch section,
the shift register includes a stage to which the touch enable signal is input;
the stage is
a Q node that controls the pull-up transistor; and
a transistor connected to the discharge path of the Q node, including a drain connected to the Q node and a source to which a high level voltage of the touch enable signal is applied, and maintaining an off state during the touch period;
The touch enable signal rises to a high level from a time within one clock pulse width prior to the start of the touch period, and is polled to a low level within a time within one clock pulse width immediately after the touch period ends to extend beyond the touch period A display device including a high-level section. The method of claim 1,
During the touch period, the gate-source voltage of the transistor is lower than the threshold voltage of the transistor,
A display device in which the drain-source voltage of the transistor is minimum. 3. The method of claim 2,
A low-level section of the touch enable signal is the display section excluding the high-level section. delete A driving device for a display device including a gate driving circuit that is divided into a display section and a touch section and is time-division driven, and supplies a gate pulse to a gate wiring of the display device according to a voltage of a Q node,
a timing control circuit for generating a touch enable signal defining the display section and the touch section;
a high level voltage of the touch enable signal is supplied to the gate driving circuit during the touch period;
The gate driving circuit is
a transistor connected to the discharge path of the Q node, including a drain connected to the Q node and a source to which a high level voltage of the touch enable signal is applied, and maintaining an off state during the touch period;
The touch enable signal rises to a high level from a time within one clock pulse width prior to the start of the touch period, and is polled to a low level within a time within one clock pulse width immediately after the touch period ends to extend beyond the touch period A driving device of a display device including a high-level section. 6. The method of claim 5,
During the touch period, the gate-source voltage of the transistor is lower than the threshold voltage of the transistor,
A driving device for a display device in which the drain-source voltage of the transistor is minimum. delete delete In the method of driving a display device divided into a display section and a touch section and time-division driven,
generating a touch enable signal defining the display section and the touch section; and
The drain of the transistor connected to the discharge path of the Q node by supplying the high level voltage of the touch enable signal during the touch period to a gate driving circuit that supplies a gate pulse to the gate wiring of the display device according to the voltage of the Q node; reducing the inter-source voltage;
The touch enable signal rises to a high level from a time within one clock pulse width prior to the start of the touch period, and is polled to a low level within a time within one clock pulse width immediately after the touch period ends to extend beyond the touch period A method of driving a display device including a high-level section. 10. The method of claim 9,
During the touch period, the gate-source voltage of the transistor is lower than the threshold voltage of the transistor,
A method of driving a display device in which the drain-source voltage of the transistor is minimum. A gate driving circuit in which one frame is time-divided into a display driving section and a touch driving section, and a touch enable signal is input at a first level or a second level in the touch driving section,
the gate driving circuit includes a shift register;
The Nth (N is a positive integer) stage of the shift register is
a first transistor controlled by an output signal of a previous stage to supply the touch enable signal of the first level to the Q node;
a second transistor controlled by an output signal of a next stage to supply the touch enable signal of the second level to the Q node; and
a pull-up transistor for outputting the applied first clock signal to an N-th output terminal controlled by the voltage on the Q node;
the first transistor, the second transistor, and the pull-up transistor;
When the N type, the first level is a high level, the second level is a low level, when the P type is the second level is a high level, the first level is a low level,
The touch enable signal rises to a high level from a time within one clock pulse width prior to the start of the touch driving period, and then falls to a low level within a time within one clock pulse width immediately after the touch driving period ends to drive the touch A gate driving circuit including a high-level section that is longer than the section. 12. The method of claim 11,
The Nth stage is a dummy stage,
The display driving section includes a first display driving section before the touch driving section and a second display driving section following the touch driving section,
In the first display driving period, the Q node is charged,
outputting a carry signal to the N-th output terminal in the touch driving period;
a gate driving circuit in which the Q node is discharged during the second display driving period. 12. The method of claim 11,
The display driving section includes a first display driving section before the touch driving section and a second display driving section following the touch driving section,
In the first display driving period, the Q node is charged,
A gate driving circuit for outputting a gate pulse to the N-th output terminal during the second display driving period. 14. The method according to claim 12 or 13,
The N-th stage,
and a third transistor controlled by the voltage of the QB node to supply the touch enable signal to the Q node. 15. The method of claim 14,
and a pull-down transistor controlled by the QB node voltage to discharge the N-th output terminal. the gate driving circuit according to claim 11;
a panel for displaying images; and
Including; a touch driving circuit for sensing a touch of the panel;
The panel includes a plurality of pixels, a plurality of pattern electrodes grouping the plurality of pixels into a plurality of pixel groups, one-to-one corresponding to each group, and a sensing line connecting each of the pattern electrodes to the touch driving circuit. Including a touch screen integrated display. 17. The method of claim 16,
The Nth stage is a dummy stage,
The display driving section includes a first display driving section before the touch driving section and a second display driving section following the touch driving section,
In the first display driving period, the Q node is charged,
outputting a carry signal to the N-th output terminal in the touch driving period;
The Q node is discharged during the second display driving period. 17. The method of claim 16,
The display driving section includes a first display driving section before the touch driving section and a second display driving section following the touch driving section,
In the first display driving period, the Q node is charged,
A touch screen-integrated display device for outputting a gate pulse to the N-th output terminal during the second display driving period. 19. The method according to claim 17 or 18,
The N-th stage,
The touch screen integrated display device further comprising a third transistor controlled by the voltage of the QB node to supply the touch enable signal to the Q node. 17. The method of claim 16,
The gate driving circuit is
and a pull-down transistor controlled by the voltage of the QB node to supply a low potential power to the N-th output terminal.

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