TWI588701B - Display device, and device and method for driving the same - Google Patents

Description

Display device, drive device of the display device, and driving method

The present invention provides a display device, a driving device of the display device, and a driving method.

The touch screen is provided to an image display device, such as a liquid crystal display, a field emission display (FED), a plasma display panel (PDP), an electroluminescence device (EL), and an input device of an electrophoretic display device. The user inputs a predetermined information to the image display device by pressing (or touching) a touch sensor included in the touch screen while viewing the image display device.

The driving circuit of a display device comprises: a pixel array for displaying images, and a data driving circuit for supplying a data signal to the data line of the pixel array, a gate driver circuit (or a scan driver circuit), A gate pulse (or a scan pulse) synchronized with the data signal is sequentially supplied to the gate line (or scan line) of the pixel array, and a timing controller for controlling the data driver circuit and the gate driver circuit .

Each pixel may include a thin film transistor (TFT) that supplies a voltage of a data line to a pixel electrode in response to a gate pulse. The gate pulse swings between a gate high voltage (VGH) and a gate low voltage (VGL). The gate high voltage (VGH) is a turn-on voltage of a transistor and is set to a voltage higher than a threshold voltage of an n-type metal oxide semiconductor field effect transistor (MOSFET). The gate high voltage (VGH) is the turn-off voltage of a transistor and is set to a voltage lower than the threshold voltage of an n-type metal oxide semiconductor field effect transistor (MOSFET).

Nowadays, a technique of accommodating a gate driving circuit and a pixel array together in a display panel has been applied. In the following, a GIP (Gate In Panel) is a gate driver circuit housed in a display panel. This gate driver circuit includes a shift register. The shift register includes a plurality of stages of cascade connections. These stages produce an output in response to a starting pulse and shift the output according to a shift clock.

The stage of the shift register includes a Q node for charging the gate line, a QB node for discharging the gate line, and a switching circuit connected to the Q node and the QB node. The switching circuit boosts the voltage of the gate line through the charging Q node in response to a starting pulse or the output of the previous stage, and discharges the QB node in response to the output of the next stage or a reset pulse. The switching circuit can be implemented using a thin film transistor (TFT) of a metal oxide semiconductor field effect transistor (MOSFET) structure.

Touch screens can be classified into add-on, on-cell, and in-cell touch screens according to their structure. An add-on touch screen is independently manufactured in accordance with the display device and the touch screen and then the touch screen is attached to the top substrate of the display device. An on-cell touch screen is constructed by forming components of a touch screen directly on the surface of a top glass substrate of a display device. An in-cell touch screen can achieve a thin display device and improve durability by embedding a touch screen in a display device. However, an add-on touch screen having a touch screen mounted on the display device increases the thickness of the display device and reduces the brightness of the display device, thereby reducing the visibility problem. Compared with an add-on touch screen, an on-cell touch screen is formed on the surface of the display device by a separate touch screen, thereby reducing the thickness of the display device, but due to the composition The driving electrodes and sensing electrodes of the touch screen and the insulating layer for insulating the driving electrodes and the sensing electrodes still have a problem that the thickness of the display device and the number of processes are increased, thereby increasing the manufacturing cost.

The in-cell touch screen can be improved in durability and its thickness can be reduced, so that the problems of add-on and on-cell touch screens can be solved. The in-cell touch screen can be classified into an optical touch screen and a capacitive touch screen.

The optical touch screen has a light sensing layer formed on a thin film transistor array of the display device such that light reflected by an object corresponding to a touch point is recognized by light or infrared light using a backlight unit. However, although the optical touch screen exhibits relatively stable driving performance in a dark environment, in a bright environment, light that is more intense than light reflected by the touch is used as noise. This is because the intensity of the light reflected by the touch is very low, and thus an identification error can be generated even when the surrounding environment is slightly bright. In particular, when the surrounding environment is exposed to sunlight, the optical touch screen has a problem that the touch may not be recognized due to the significant high intensity of the light.

Capacitive touch screens can be classified into a self-capacitance type and a mutual capacitance type. The mutual capacitance type touch screen is arranged in such a manner that a common electrode is divided into a driving electrode and a sensing electrode, so that mutual capacitance is generated between the driving electrode and the sensing electrode, so as to be used as a transmission measurement for the touch. Mutual capacitance recognition touch. However, since the mutual capacitance generated during the touch recognition process is small, and the parasitic capacitance of the gate line and the data line constituting the display device having the touch screen is very large, the mutual capacitance type touch screen cannot be correctly recognized. A touch point. In addition, since a plurality of touch driving lines for touch operation and a plurality of touch sensing lines for touch sensing need to be formed on a common electrode, the mutual capacitance type touch screen requires a very complicated interconnection. structure. In order to solve this problem, an independent display and touch driving method has been proposed. In this way, a plurality of electrodes formed to overlap a plurality of pixel electrodes in a display area of the panel are formed at the display time together with the pixels. The pixel electrode is used as a common electrode for driving the liquid crystal. At a touch time, a touch scan signal supplied from a touch driving circuit is used as a touch electrode for sensing a touch point.

In such a separate display and touch driving method, the plurality of stages of the shift register constituting a gate driver circuit includes one stage, and the stage has a Q node that remains in the standby state during the touch time. The Q node of this stage is in a floating state during the touch time, in which no power is supplied, thereby causing a voltage drop due to leakage current. Such a problem may result in an abnormal signal output to the gate line, resulting in a defect such as a horizontal line on the display panel corresponding to the gate line. In addition, the voltage drop at the Q node in the standby state level increases the touch time.

The present invention provides a display device, a driving device for the display device, and a driving method for minimizing a leakage current of a first stage in a standby state during a touch operation to maintain a voltage of a Q node of the stage.

Another object of the present invention is to provide a display device, a driving device for the display device, and a driving method. The present invention can ensure a high resolution at a time by reducing a margin between a display time and a touch time. Pulse time.

Another object of the present invention is to provide a display device, a driving device for the display device, and a driving method. The present invention increases a touch time according to a stable Q node voltage maintained by a standby stage.

In order to accomplish the object of the present invention, a gate driver circuit is provided. The gate driver circuit divides a frame time into a display time and a touch time, and one of the touch enable signals has a first level. Or a second level, the gate driver circuit includes an Nth stage, and the Nth stage includes: a first transistor controlled by an output signal of a previous stage and having a first level of touch enable The signal is supplied to a Q node; a second transistor is controlled by an output signal of the next stage and supplies a touch enable signal having a second level to the Q node; and a pull-up transistor, by the Q node a voltage control to output a first clock signal provided thereto to an Nth output terminal, wherein when the first transistor, the second transistor, and the pull-up transistor are N-type transistors, the first battery Level is a high level and the second level is a low level, and when the first transistor, the second transistor, and the pull-up transistor are P-type transistors, the first level is a low level The second level is a high level. Therefore, by supplying a high-level touch enable signal (VTEN) corresponding to a high-level power supply voltage to a source or a drain terminal opposite to a source-drain path Q node, the voltage of the Q node is self-starting. The period can be maintained and even increased without decreasing, wherein this source-drain path is the path through which the charge of the Q node can leak.

The present invention provides a gate driver circuit and a touch screen integrated display device having the gate driver circuit, which can minimize a leakage current of a first stage in a standby state during a touch operation, so that Maintaining a voltage of a Q node of this level can ensure a clock time at a high resolution and a stable Q node voltage increase according to a standby level by reducing the margin time between a display time and a touch time. Touch time.

Hereinafter, a description will be given of a gate driver circuit and a touch screen integrated body display device having the gate driver circuit according to an embodiment of the present invention with reference to the accompanying drawings. The above and other aspects of the present invention will be described in detail by the preferred embodiments thereof so that the present invention can be easily understood and implemented by those skilled in the art. The modifications of the preferred embodiment will be apparent to those skilled in the art, and the invention as described herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention and the scope of the appended claims. In the drawings, the size and thickness of a device may be exaggerated for clarity. The same numbers in the description of the drawings refer to the same elements.

The features and advantages of the present invention and the method of accomplishing the same are apparent from the accompanying drawings. However, the embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments may be provided so that the invention will be thorough and complete, and Fully convey these concepts. In the description of the drawings, the same numerals refer to the same elements. The size and relative sizes of layers and regions may be exaggerated in the drawings for clarity and convenience.

It will also be understood that when an element is referred to as being "on" another element, it can be < In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element.

In addition, relative terms such as "bottom" or "bottom" and "top" or "top" are used herein to describe the relationship of one element to another in the drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientations described in the drawings. For example, if the device is turned over in one of the figures, the elements described as "bottom" on the other elements will be directed to the "top" side of the other elements. The exemplary term "bottom" can thus include both "bottom" and "top" orientations, depending on the particular orientation of the schema.

The terms used in the description of the present invention are used for the purpose of describing the specific embodiments and are not intended to limit the invention. The use of the singular forms "a", " It will be further understood that the terms "comprising" and / or "comprising" or "having" are used in the specification to refer to the described features, regions, integers, steps, operations, components, and/or components. The existence or addition of one or more other features, regions, integers, steps, operations, components, components, and/or combinations thereof.

In a gate driver circuit of the present invention, the switching element can be implemented as an n-type or p-type metal oxide semiconductor field effect transistor (MOSFET) structure transistor. In the following embodiments, an n-type transistor is shown, but the invention is not limited thereto. The transistor is a three-electrode element comprising a gate, a source and a drain. The source is an electrode that supplies a carrier to the transistor. The carrier begins to flow from the source in the transistor. The crucible is an electrode in which the carrier is released to the outside of the transistor. That is, in a metal oxide semiconductor field effect transistor (MOSFET), carriers flow from the source to the drain. In an n-type metal oxide semiconductor field effect transistor (MOSFET) (NMOS), since the carrier is an electron, a source voltage is less than a drain voltage in order to cause electrons to flow from the source to the drain. In this n-type metal oxide semiconductor field effect transistor (MOSFET), since electrons flow from the source toward the drain, a current flows from the drain to the source. In a p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS), since the carrier is a hole, a source voltage is greater than a drain voltage in order to cause a hole to flow from the source to the drain. In a p-type metal oxide semiconductor field effect transistor (MOSFET), since a hole flows from the source toward the drain, a current flows from the source toward the drain. It should be noted that the source and drain of a metal oxide semiconductor field effect transistor (MOSFET) are not fixed. For example, the source and drain of a metal oxide semiconductor field effect transistor (MOSFET) can vary depending on an applied voltage. In the following embodiments, the present invention is not limited due to a source and a drain of the transistor.

The present invention divides a frame cycle time into at least one touch time and at least one display time to drive the pixels and the touch sensor. The display time is separated from a touch time in between. A shift register of the gate driver circuit should not generate an output during a touch time and should generate a next output when restarting from the next display time. However, a Q-node voltage of the shift register is discharged during the touch time, and when the next display time is restarted, the voltage of one gate pulse is lowered, and thus, the same gate line can be generated. The pixel's charge decreases in the form of a line of noise.

When the voltage Vgs between a gate and a source of the transistor is lower than the threshold voltage Vth, the transistor is turned off and thus a drain current Id does not flow, but a closed state or sub-valve of the transistor In the value area, a leak may occur. In fact, when Vgs is less than Vth (Vgs < Vth), a sub-threshold current is generated in a closed state or sub-threshold region of the transistor, as shown in FIG. As the voltage Vds between a drain and a source of the transistor increases with a voltage Vgs between a gate and a source, as shown in FIGS. 1 and 2, the leakage or sub-threshold current increases. Such leakage is not large, but as the flow time of the leak increases, the amount of leakage increases to adversely affect circuit operation and energy consumption. Furthermore, as the operating temperature increases, the leakage of the transistor increases, and when a semiconductor channel of the transistor is exposed, the increase in the amount of leakage is proportional to the intensity of the light.

In the present invention, in order to minimize the touch time to minimize the leakage of the transistor connected to a discharge path of a Q node, the Q node can be prevented by reducing the Vds in the off state of the transistor (Vgs < Vth). Discharge.

3 and 4 show an example of an example in which a Q node can be discharged in a gate driver circuit. 3 and 4 show an nth stage of the nth output Vout generated by operation in the forward direction mode in a bidirectional shift register of a gate driver circuit. The gate driver circuit of Figures 3 and 4 illustrates the occurrence of a discharge of the Q node therein, and it should be noted that the gate driver circuit of Figures 3 and 4 is not known in the prior art of the present invention. The transistor of FIGS. 3 and 4 is an n-type metal oxide semiconductor field effect transistor (MOSFET), but the present invention is not limited thereto.

Referring to FIG. 3 and FIG. 4, a shift register of the gate driver circuit includes a plurality of stages connected in cascade. These stages include a Q node that controls a pull-up transistor Tup, a charge/discharge unit 21 connected to the Q node, a Q-node stabilizer 22, and a QB node that controls the pull-down transistor Tdown.

The charging/discharging unit 21 includes first and second transistors T1 and T2. The first and second transistors T1 and T2 charge/discharge a Q node. When a bidirectional shift register operates in a forward direction mode, the first transistor T1 charges a Q node in response to an output (Gn-1) of an (n-1)th stage, and the second transistor The crystal T2 discharges a Q node in response to an output G(n+1) of an (n+1)th stage. The drain of the first transistor T1 is connected to a forward power supply terminal and its source is connected to a Q node. The gate of the first transistor T1 is connected to a first gate terminal. In a forward mode, a gate high voltage (VGH) is provided to the forward power supply terminal. In a reverse mode, a gate low voltage (VGL) is provided to the forward power supply terminal. A preceding clock or an output (n-1) of the (n-1)th stage is input to the first gate terminal. This preceding clock is a clock having a phase earlier than the phase of an nth clock CLK applied to the upper pull transistor Tup. A gate high voltage (VGH) is set to a voltage higher than the threshold voltages Vth of the first, second, and third transistors T1, T2, and T3. A gate low voltage (VGL) is set to a voltage lower than the threshold voltages Vth of the first, second, and third transistors T1, T2, and T3.

The drain of the second transistor T2 is connected to the Q node and its source is connected to a reverse power supply terminal. The gate of the second transistor T2 is connected to a second gate terminal. In a forward mode, a gate low voltage (VGL) is provided to a reverse power supply terminal. In a reverse mode, the gate high voltage (VGH) is supplied to a reverse power supply terminal. An output of the next clock or the (n+1)th stage, G(n+1), is input to the second gate terminal. This next clock is a clock having a phase that is later than the phase of the nth clock CLK.

The Q node is precharged using a gate high voltage (VGH) from the charge/discharge unit 21, and when an nth clock CLK is supplied to the pull-up transistor Tup, a potential thereof is turned on by pulling on the pull-up transistor. Tup rises to 2 times the gate high voltage (VGH). When an nth clock CLK of the gate high voltage (VGH) is supplied, the pull-up transistor Tup is turned on according to a Q-node voltage to boost an output Vout voltage to a gate high voltage (VGH) potential. The gate of the pull-up transistor Tup is connected to the Q node. The drain of the pull-up transistor Tup is connected to a clock terminal. The source of the pull-up transistor Tup is connected to an output terminal. An nth clock CLK is input to the pulse terminal.

The Q node stabilizer 22 includes a third transistor T3. The third transistor T3 discharges the Q node in response to a QB node. A QB control signal is input to the QB node based on an nth clock CLK and a clock supplied to the first gate terminal or a clock that does not overlap with a previously output clock (Gn-1). By simultaneously turning on the third transistor T3 and the lower pull transistor Tdown, the QB control signal pulls down the output voltage Vout while discharging the Q node. The gate of the third transistor T3 is connected to the QB node. The drain of the third transistor T3 is connected to the Q node. The source of the third transistor T3 is connected to a low potential power supply terminal. A gate low voltage (VGL) is supplied to the low potential power supply terminal.

By discharging an output terminal in response to a QB control signal, the pull-down transistor Tdown reduces the output Vout voltage to a gate low voltage (VGL). The gate of the pull-down transistor Tdown is connected to the QB node. The drain of the pull-down transistor Tdown is connected to the output terminal. The source of the pull-down transistor Tdown is connected to the low potential power supply terminal.

The touch time is longer than one horizontal time of the display time. At the touch time, a gate low voltage (VGL) is supplied to the gates of the second and third transistors T2 and T3. Therefore, for a touch time, since the Vgs of the second and third transistors T2 and T3 are 0, the current between a drain and a source should ideally not exist, but due to leakage current, current exists and A voltage of this Q node is released. For a touch time, because the voltage Vds between a drain and a source of the second and third transistors T2 and T3 is transmitted between the gate high voltage (VGH) and the gate low voltage (VGL) The difference voltage (Vds = Vq - VGL ≒ VGH - VGL) is high, so a leakage current occurs in the off state of the transistor. When the discharge time of the Q node is extended, a Q-node voltage Vq is lowered, and thus the gate driver circuit does not produce a normal output.

In FIG. 4, CLKB is an inverted clock of an nth clock CLK. Vqb is a voltage of the QB node.

In the present invention, in order to prevent such leakage at the Q node, in a turn-off state (Vgs<Vth) of the second and third transistors T2 and T3 on a discharge path of the Q node at the touch time, Vds is controlled at the minimum value (Vds = 0), as shown in Figures 5-8.

5 through 8 are diagrams showing the prevention of discharge of a Q node in accordance with an embodiment of the present invention.

Referring to FIG. 5 and FIG. 6, the present invention uses an AC signal, that is, a touch enable signal (VTEN), to prevent discharge at the Q node during a touch time. The touch enable signal (VTEN) is an AC signal, that is, a low level voltage (=VGL) is maintained for one display time, and a high level voltage (=VGH) is maintained for one touch time.

For a touch time, a gate low voltage (VGL) is supplied to the gates of the first, second, and third transistors T1, T2, and T3 to maintain an off state. For touch time, the gate high voltage (VGH) of the touch enable signal (VTEN) is supplied to the sources of the first, second, and third transistors T1, T2, and T3. The first transistor T1 charges a Q node using a gate high voltage (VGH) at a touch time. However, the second and third transistors T2 and T3 are connected to a discharge path of the Q node to suppress discharge of the Q node of the touch time. In this case, the sources of the second and third transistors T2 and T3 can be considered to be one drain. Therefore, since the Vds of each of the first, second, and third transistors T1, T2, and T3 becomes the minimum value (Vds = 0, substantially zero), there is no leakage through the transistor and thus Q The node does not discharge.

When a clock CLK is input, a voltage at the Q node rises to 2 times the gate high voltage (VGH). In this case, in order to minimize the Vds of the transistor, a voltage of the touch enable signal (VTEN) can be synchronized with the clock CLK to rise to 2 times the gate high voltage (VGH).

For a touch time, at each of the transistors T1, T2, and T3, since Vds = Vq - VGH ≒ VGH - VGH = 0, the leakage does not exist. Therefore, in the present invention, a voltage Vq of the Q node can be maintained almost constant at a touch time.

The reason why the touch enable signal (VTEN) is supplied to the first transistor T1 is to change a scan direction to a clock signal change. A virtual stage circuit of Figures 5 and 7 can be applied only to the stages of all stages of the shift register where the touch time begins and ends. Other stages should use an existing stage circuit.

The touch enable signal (VTEN) may have a higher level of time than a touch time of FIG. 6 to change in a scan direction corresponding to the shift register. When the touch enable signal (VTEN) and a voltage of the QB node simultaneously rise to a high level (=VGH), even if the first transistor T1 is not turned on, the Q node is charged through the third transistor T3, and Therefore an output Vout may rise to a high level (=VGH) at an undesired timing. With this in mind, when the touch enable signal (VTEN) continues to be wider than a touch time, the touch enable signal (VTEN) is defined as follows. The touch enable signal (VTEN) should not rise to a high level (=VGH) one pulse pulse earlier than the start of the touch time, or should not be later than the end of the touch time. 1 clock pulse width falls to a low level (= VGL). One clock pulse width is one pulse width supplied to a gate shift clock (CLK) of the shift register. In other words, when the touch enable signal (VTEN) continues to be larger than the touch time, the touch enable signal (VTEN) should be one clock later than the touch time. The time within the pulse width is raised to a gate high voltage (VGH) level and should fall to the gate low voltage (VGL) for a time within one pulse pulse width after the end of the close contact time Level.

Referring to FIGS. 7-8B, a gate high voltage (VGH) may be supplied to the drain of the first transistor T1. This embodiment can apply a circuit of all stages of the shift register to a circuit of FIG. 7, or can be applied to only a specific stage.

A high time of the touch enable signal (VTEN) can be synchronized with a touch time. The touch enable signal (VTEN) is raised to the gate high voltage (VGH) level at the beginning of the touch time and is lowered to the gate low voltage (VGL) level while the touch time is terminated.

FIG. 8A is an example of first causing a clock signal (CLK) to reach a high level before the start of the next display time after the end of one touch time.

FIG. 8B is an example of first causing a CLKB to reach a high level before the start of the next display time after the end of one touch time. The number of stages of a gate driver circuit to which the touch enable signal (VTEN) is provided requires up to one number of touch time groups within a frame period. Among these levels, from the perspective of a touch time, the voltage of the Q node should be maintained at one level, and in the remaining states in which the touch enable signal (VTEN) is provided, a Q node and a The QB node can be floated. In this case, in a state in which the charge of the Q node is injected due to an external influence, when a clock signal (CLK) is immediately enabled, an undesired output may occur. Therefore, CLKB is enabled before the clock signal (CLK) is enabled, and a display time job is started after the Q node is initialized to a gate low voltage (VGL) and the QB node is initialized to a gate high voltage (VGH). As a result, the stability of the circuit operation is improved.

A driving device of the present invention can be implemented using an integrated circuit (IC) package of the same form as that of Figs.

Referring to FIG. 9, the driving device includes a driving integrated circuit (DIC) and a touch integrated circuit (TIC).

The driving integrated circuit (DIC) includes a touch sensor channel unit 10, a Vcom buffer 11, a switch array 12, a first timing control signal generator 13, a multiplexer (MUX) 14, and a DTX compensation unit 15.

The touch sensor channel unit 10 is connected to a pattern electrode 120 of the touch sensor through a sensing line (SL) and is connected to the Vcom buffer 11 and the multiplexer 14 through the switch array 12. The multiplexer 14 connects the sensing line (SL) to the touch integrated circuit (TIC). In a 1:3 multiplexer, the multiplexer 14 connects one channel time division of the touch integrated circuit (TIC) to the three sensing lines SL, thereby reducing the touch integrated circuit (TIC). The number of channels. The multiplexer 14 selects a sensing line connected to a channel of the touch integrated circuit (TIC) in response to the MUX control signal (MUX C1-C3). The multiplexer 14 is connected to the channel of the touch integrated circuit (TIC) through a touch line.

The Vcom buffer 11 outputs a common voltage Vcom of one pixel. Under the control of the timing control signal generator 13, the switch array 12 supplies the common voltage Vcom from the Vcom buffer 11 to the touch sensor channel unit 10 at a display time. Under the control of the timing control signal generator 13, the switch array 12 connects the sensing line (SL) to the touch integrated circuit (TIC) at a touch time.

The first timing control signal generator 13 generates a timing control signal for controlling the operation timing of the display driver circuit and the touch integrated circuit (TIC). The display driver circuit includes a data driver circuit for writing data of an input image into a pixel and a gate driver circuit. The data driver circuit generates a data voltage to supply the data voltage to the data line of the display panel. The data driver circuit can be integrated into the driver integrated circuit (DIC). The gate driver sequentially supplies a gate pulse wave (or a scanning pulse wave) synchronized with a data voltage to the gate line of the display panel. The gate driver circuit can be disposed on the substrate of the display panel together with the pixels, as shown in FIGS. 12 and 15.

The first timing control signal generator 13 is substantially identical to the timing control signal generator of the timing controller 400 of FIG. The first timing control signal generator 13 drives a display driver circuit during display time and drives a touch integrated circuit (TIC) during touch time.

The first timing control signal generator 13 generates a touch enable signal (Touch EN), and the touch enable signal (Touch EN) defines a display time and a touch time to synchronize the display driver circuit and a touch integrated circuit. (TIC). The display driver circuit writes data into the pixels at a first level of the touch enable signal (Touch EN). The touch integrated circuit (TIC) drives the touch sensor in response to a second level of the touch enable signal (Touch EN) and senses a touch input. A first level of the touch enable signal (Touch EN) may be a low level, and a second level thereof may be a high level, but the first level and the first of the touch enable signal (Touch EN) The two levels can be set to the opposite.

The touch enable signal (VTEN) that suppresses the discharge of the Q node of the gate driver circuit is generated based on a touch enable signal (Touch EN) of a digital logic level generated by the first timing control signal generator 13. The timing control signal generator 13 modulates a touch enable signal by further extending the width within one pulse pulse width before and after a second level time of the touch enable signal (Touch EN). Touch EN) defines the timing of the touch enable signal (VTEN) of FIG. 6 or the timing of the touch enable signal (VTEN) of FIG. 8 by using a touch enable signal (Touch EN). Because a level shifter (not shown) cannot control the metal oxide semiconductor field of a gate driver circuit using a touch enable signal (Touch EN) of a digital logic level output from the timing control signal generator 13 Effecting transistor (MOSFET), so the level shifter shifts a level of the touch enable signal (Touch EN) to produce a swing between the gate high voltage (VGH) and the gate low voltage (VGL) A touch enable signal (VTEN). The level shifter shifts the level of the gate start pulse wave VST and the gate shift clock CLK output from the timing control signal generator 13 to a gate high voltage (VGH) and Gate low voltage (VGL). The touch enable signal (VTEN) from the level shifter, the gate start pulse VST, and the gate shift clock CLK are supplied to the shift register of the gate driver circuit.

The noise can be added to the touch sensor signal according to the change of the input image data. The DTX compensation unit 15 analyzes the input image data according to the gradation change of an input image and removes the noise component from the touch original data (TDATA), and transmits the touch original data (TDATA) to the touch integrated circuit (TIC). . DTX stands for display and touch crosstalk. In a system in which the noise of the touch sensor is not sensitively changed according to changes in an input image data, since a DTX compensation unit 15 is unnecessary, the DTX compensation unit 15 can be omitted. In Fig. 9, DTX DATA is the output data of the DTX compensation unit 15.

The touch integrated circuit (TIC) is received through the multiplexer 14 and the sensing line SL by responsive to a touch enable signal (Touch EN) from the timing control signal generator 13 to drive the multiplexer 14 at the touch time. The charge of a touch sensor. In Fig. 9, MUX C1-C3 are signals for selecting one channel of the multiplexer.

The touch integrated circuit (TIC) detects the amount of charge change before and after a touch input from a received signal of the touch sensor, compares the amount of charge change with a predetermined threshold, and determines the touch input area. The position of the touch sensor with a threshold or more charge change. The touch integrated circuit (TIC) calculates the coordinates of each touch input and transmits touch data having touch input coordinate information to an external host system. The touch integrated circuit (TIC) includes an amplifier that amplifies the charge of the touch sensor, accumulates an integrator of the charge received from the touch sensor, and converts a voltage of the integrator into a analog of the digital data to A digital converter (ADC), and an operational logic unit. The operation logic unit executes a touch recognition algorithm to compare the touch raw material (TDATA) output from the analog to digital converter (ADC) with a threshold value, and determines a touch input and calculates coordinates according to the comparison result.

The driver integrated circuit (DIC) and the touch integrated circuit (TIC) can transmit and receive signals through a series of peripheral interfaces (SPI).

A host system refers to a body of an electronic device to which the display device of the present invention can be applied. The host system can be a telephone system, a television (TV) system, a set-top box, a navigation system, a digital compact disc (DVD) player, a Blueray player, a personal computer (PC), and a home theater system. Any of them. The host system sends an input image data to a driver integrated circuit (DIC) and receives touch input data from a touch integrated circuit (TIC) to perform an application related to a touch point.

Referring to FIG. 10, a driving device includes a driving integrated circuit (DIC) and a microcontroller unit (MCU).

The driving integrated circuit (DIC) includes a touch sensor channel unit 10, a Vcom buffer 11, a switch array 12, a first timing control signal generator 13, a multiplexer 14, and a DTX compensation unit 15. a sensing unit 16, a second timing control signal generator 17, and a memory 18. Compared to the foregoing embodiment of FIG. 9, the present embodiment has a difference in that the sensing unit 16 and the second timing control generator 17 are integrated in the driving integrated circuit (DIC). The first timing control generator 17 is substantially the same as that of FIG. Therefore, the second timing control generator 17 generates timing control signals for controlling the operation timing of a display driver circuit and a touch integrated circuit (TIC).

The sensing unit 16 includes an amplifier that amplifies the charge of a touch sensor, an integrator that accumulates the charge received from the touch sensor, and an analog-to-digital conversion that converts a voltage of the integrator into digital data. (ADC). The touch raw material (TDATA) output from the analog to digital converter (ADC) is sent to the microcontroller unit (MCU). The second timing control generator 17 generates a timing control signal and a clock for controlling the operation timing of the multiplexer 14 and the sensing unit 16. The DTX compensation unit 15 can be omitted in the drive integrated circuit (DIC). The memory 18 temporarily stores touch raw material (TDATA) under the control of the second timing control generator 17.

The Drive Integrated Circuit (DIC) and Microcontroller Unit (MCU) can transmit and receive signals through a serial peripheral interface (SPI). The microcontroller unit (MCU) executes a touch recognition algorithm that compares the touch raw material (TDATA) with a threshold and determines a touch input based on the comparison result and calculates a coordinate.

Referring to FIG. 11, the driving device includes a driving integrated circuit (DIC) and a memory (MEM).

The driving integrated circuit (DIC) includes a touch sensor channel unit 10, a Vcom buffer 11, a switch array 12, a first timing control signal generator 13, a multiplexer 14, and a DTX compensation unit 15. A sensing unit 16, a second timing control signal generator 17, a memory 18, and a microcontroller unit (MCU) 19. In contrast to the previous embodiment of FIG. 10, this embodiment has the difference that the microcontroller unit (MCU) 19 is integrated in the drive integrated circuit (DIC). The microcontroller unit (MCU) 19 executes a touch recognition algorithm that compares the touch raw material (TDATA) with a threshold and determines a touch input based on the comparison result and calculates a coordinate.

The memory MEM stores a register setting associated with the timing information necessary for the display driver circuit and the operation of the sensing unit 16. When the power of the display device is turned on, a register setting value is loaded from the memory MEM to the first timing control signal generator 13 and the second timing control signal generator 17. The first timing control signal generator 13 and the second timing control signal generator 17 generate timing control signals for controlling the display driver circuit and the sensing unit 16 based on the register setting values read from the memory. By changing the register setting of the memory MEM without the structural change of the driving device, the driving device can correspond to a mode change.

FIG. 12 is a diagram showing a touch screen integrated display device including a single gate driver circuit and a driving unit thereof, and FIG. 13 is a view showing a touch screen integrated display device according to an embodiment of the invention. FIG. A pattern of a plurality of pixels of the display panel and corresponding pattern electrodes, and FIG. 14 is a diagram showing a connection of the pattern electrodes and the sensing lines. FIG. 15 is a diagram showing a touch screen integrated display device including two gate driver circuits and a driving unit 15 thereof according to an embodiment of the invention.

As shown, the display device of the present invention includes a display panel 100 for displaying images, and a timing controller 400 for receiving timing signals from the host system and generating various control signals for controlling in response to the control signals. A gate driver circuit 200 and a data driver circuit 300 of the display panel 100, and a touch driver circuit 500 for touch operation.

The display panel 100 includes K (K is a positive integer) gate lines and a plurality of data lines DL1 to DLm formed in a matrix form on a glass substrate in an intersecting manner, and is formed at the intersection of the gate lines and the data lines. The plurality of pixels 110. Each pixel 110 includes a thin film transistor (TFT), a liquid crystal capacitor, and a storage capacitor. All pixels 110 form a display area A/A. An area in which the pixel 110 is absent is defined as a non-display area N.

In addition, the display panel 100 includes a touch screen embedded therein. The touch screen senses a user's touch point. In particular, the display panel according to the present invention may include a self-capacitance in-cell touch screen. Further, the pixels 110 of the display panel 100 may be grouped into a plurality of pixel groups, and as shown in FIG. 13, the display panel 100 may further include a plurality of pattern electrodes 120 corresponding to one-to-one of the pixel groups. As shown in FIG. 14, the pattern electrode 120 can be connected to the touch driver circuit 500 through the sensing SL.

The pattern electrode 120 may be provided with a common voltage for driving the display of the display panel 100 to serve as a common electrode for driving the liquid crystal together with the pixel electrode. In addition, the pattern electrode 120 can be provided with a touch scan signal for sensing touch as a touch electrode for sensing a touch point. For example, the touch screen integrated display device according to an embodiment of the present invention performs a display job and a touch operation in a time frame manner in a frame. That is, when the display panel 100 is in a display mode, the pattern electrode 120 is provided with a common voltage for driving the common electrode of the display together with the pixel electrode, and when the display panel 100 is in a touch mode, the pattern electrode 120 A touch screen is provided for sensing touch points by providing a touch screen signal from the touch driver circuit 500. Here, the common voltage may be provided by the touch driver circuit 500 or may be directly supplied to the display panel 100 by an additional common voltage generator included in the display device without passing through the touch driver circuit 500.

The touch driver circuit 500 can include: a touch scan signal generator for generating a touch scan signal; and a touch sensor for sensing the touch using the difference between the received touch sense signals And a switch, the common voltage or touch scan signal is provided to the plurality of electrodes through the switch. The touch driver circuit 500 provides a common voltage or touch scan signal to the pattern electrode 120 through the sensing line SL according to the driving mode of the display panel 100, and receives the touch sensing signal generated according to the touch scanning signal from the pattern electrode 120, and uses The difference between the received touch sensing signals senses the presence or absence of the touch.

The pattern electrodes 120 can be grouped and sequentially operated on a group basis for one frame. The number of pattern electrodes 120 of each group may vary based on a touch time and a display time.

The timing controller 400 transmits an input video signal (RGB) received from a host system to the data driver circuit 200. The timing controller 400 generates a timing control signal for using a timing signal such as a clock signal (DCLK), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and together with the video signal (RGB). A data enable signal (DE) is received to control the gate driver circuit 200 and the data driver circuit 300.

Here, the horizontal synchronization signal (Hsync) is a signal indicating the time used to display a horizontal line of a picture, and the vertical synchronization signal (Vsync) is a signal indicating that the time corresponding to displaying an image is displayed corresponding to one frame, and the data is enabled. The signal (DE) is a signal indicating a period in which one of the data voltages is supplied to the pixels of the display panel 100.

In addition, the timing controller 400 generates a control signal GCS of the gate driver circuit 200 and a control signal DCS of the data driver circuit 300 in synchronization with the timing signal input thereto.

Further, the timing controller 400 generates a plurality of clock signals for determining the driving timing of each stage of the gate driver circuit 200, and supplies the driving timing to the gate driver circuit 200. The timing controller 400 arranges and modulates the video material RGB input thereto into a form that can be processed by the data driver circuit 300 and outputs the modulated video material. The arranged video material may have the form in which a color coordinate correction algorithm is applied.

The timing controller 400 generates a touch enable signal (Touch EN) for a touch operation. A touch enable signal (Touch EN) is provided to the touch driver circuit 500. A touch enable signal (Touch EN) is supplied to the gate driver circuit 200 through a level shifter 402. The touch driver circuit 500 is driven when a high level touch enable signal (Touch EN) is supplied to sense a touch input.

The data driver circuit 300 generates a sample signal by shifting a source start pulse (SSP) signal supplied from the timing controller 400 according to a source shift clock (SSC) signal shift. In addition, the data driver circuit 300 latches the video data input to the source shift clock (SSC) signal according to the sampling signal to convert the video data into a data signal, and then responds to a source output enable ( The SOE) signal provides the data signal to the data line DL on a horizontal line basis. To this end, the data driver circuit 300 can include a data sampling unit, a latch unit, a digital to analog converter, an output buffer, and the like.

The gate driver circuit 200 shifts a gate start pulse wave (GSP) transmitted from the timing controller 400 according to a gate shift clock (GSC), and sets a gate high voltage (VGH) level. The gate pulse signals are sequentially supplied to the gate lines GL1 to GLn. The gate driver circuit 200 supplies a gate low voltage VGL to the gate lines GL1 to GLn during a period in which no gate pulse signal is supplied.

Although the gate driver circuit 200 applied to the present invention can be configured as a separate panel and electrically connected to the panel in various ways, the gate driver circuit 200 can be set as a non-display area by the GIP method during manufacture of the substrate of the display panel 100. A film pattern in N. In this case, a clock signal CLK and a start signal VST for driving a first operational stage of the shift register may be gate control signals for controlling the gate driver circuit 200.

Referring to FIG. 15, two gate driver circuits 200a and 200b may be disposed on the non-display area N on both sides of the display panel 100, and the first and second gate driver circuits 200a and 200b constitute a shift register. The composition of multiple levels. The first and second gate driver circuits 200a and 200b alternately output gate pulse waves through the gate lines GL1 to GLn formed in the display panel 100 in response to the gate control signal GCS supplied from the timing controller 400. Here, the output gate pulse waves may overlap at a predetermined horizontal period of the precharge gate lines GL1 to GLn to charge a more stable pixel when a data voltage is supplied.

16A, 16B, 17A, and 17B show connections of a plurality of stages constituting a shift register in accordance with various embodiments of the present invention. Fig. 18A shows the forward and reverse gate scans of the stages constituting the shift register shown in Figs. 16A and 17A, and Fig. 18B shows the stages constituting the shift register shown in Figs. 16B and 17B. Medium forward and reverse gate scans. Fig. 19 is a timing chart showing time division display and touch drive operation.

As shown in FIG. 18A, these stages are driven in the order of B, C (virtual stage) and A during the forward drive operation, and are driven in the order of A, C (virtual stage) and B during the reverse drive operation. In the forward driving operation, B is a level that outputs the last gate pulse before the touch operation, C is a virtual level that maintains the charging state of its Q node during the touch time, and A is in the touch operation. The first step of the first gate pulse is output after completion. In the reverse driving operation, A is a level that outputs the last gate pulse before the touch operation, C is a virtual level that maintains the charging state of its Q node during the touch time, and B is in the touch operation. The first step of the first gate pulse is output after completion.

As shown in Fig. 18B, these stages are driven in the order of B and A during the forward drive operation, and are driven in the order of A and B during the reverse drive operation. In the forward driving operation, B is a level at which the last gate pulse is output before the touch operation, and A is to maintain the state of charge of the Q node during the touch time and output the first gate after the touch operation is completed. The first level of the pulse wave. In the reverse driving operation, A is a level at which the last gate pulse is output before the touch operation, and B is a state in which the Q node is maintained during the touch operation and the first gate is output after the touch operation is completed. The first level of the pulse wave.

Figure 18C shows an example where no virtual level exists in a single direction. A is a level at which a Q node remains charged during touch driving and outputs a first gate pulse after the touch drive is completed.

Fig. 18D shows an example in which a dummy level C is added when a gate is driven in two directions (forward direction, reverse direction).

For the sake of convenience, the following description is based on a Nth (N is a positive integer) level connection in these stages, and outputs a gate high pulse (VGH) level gate pulse signal from the Nth stage to the Nth stage. A corresponding gate line.

<First and Third Shift Registers>

Referring to FIG. 16A and FIG. 16B, a shift register 210 according to the first and second embodiments is a shift register included in the gate driver circuit 200 according to the first embodiment as shown in FIG. 1. . Referring to FIGS. 17A and 17B, a shift register 210 according to the third and fourth embodiments is a shift temporarily included in the gate driver circuits 200a and 200b according to the second embodiment as shown in FIG. Save.

16A and 17A show the Nth, (N+1)th, and (N+2)th stages and a virtual stage as a plurality of stages constituting the shift register according to the first and third embodiments. Each of the Nth, (N+1)th, and (N+2)th stages may pass a clock signal CLK line (shift temporary storage included in the gate driver circuits 200a and 200b according to the second embodiment) In the case of the first and second clock signals CLK1 and CLK2 lines, at least two clock signals are provided, one of the output signals of the adjacent stages is received as an activation signal, and another output of the adjacent stage is received. The signal is used as a reset signal. OUT in Figures 16A-17B is an output of this stage of the shift register.

The virtual stage can receive at least two clock signals from the clock signal CLK line, receive a touch enable signal Touch EN (VTEN, VTEN1, VTEN2) from a touch enable signal line, and receive output signals of adjacent stages. One of the other output signals, which is a start signal VST and receives the adjacent stage, is used as a reset signal RST.

These stages can perform an operation for supplying a gate pulse signal upon receiving the start signal VST, and perform an operation for discharging the gate line upon receiving the reset signal RST.

In particular, the Nth stage includes an enable signal VST input terminal and a reset signal RST input terminal, and receives a gate outputted from an output terminal G(n-1) of the (N-1)th stage through the start signal VST input terminal. a pulse wave, and receiving a carry signal Vc outputted from an output terminal G(n+1/2) of the virtual stage through the reset signal RST input terminal, wherein the (N-1)th stage is the previous stage and the virtual stage is the lower stage Level one.

The virtual stage includes an activation signal VST input terminal and a reset signal RST input terminal, and receives a gate pulse wave outputted from an output terminal G(n) of the Nth stage through the start signal VST input terminal, and passes the reset signal RST input terminal. Receiving a scan signal outputted from an output terminal G(n+1) of the (N+1)th stage, wherein the Nth stage is the previous stage and the (N+1)th stage is the next stage.

In particular, the virtual stage can use a gate high voltage (VGH) level touch enable signal (TEN) to maintain a voltage charged at the Q node during a touch time while preventing leakage current, and in this touch At the end of the control time, the clock signal in response to the gate high voltage (VGH) level supplied thereto is outputted to the next stage, the (N+1)th stage through the output terminal G(n+1/2).

The (N+1)th stage includes an enable signal VST input terminal and a reset signal RST input terminal, and receives a carry signal Vc outputted from the output terminal G(n+1/2) of the virtual stage through the start signal VST input terminal, and A scan signal outputted from an output terminal G(n+2) of the (N+2)th stage is received through the reset signal RST input terminal, wherein the virtual level is the previous stage and the (N+2)th stage is the next stage.

The (N + 2)th stage includes an enable signal VST input terminal and a reset signal RST input terminal, and receives the gate output from the (N+1)th output terminal G(n+1) through the start signal VST input terminal. a pulse wave, and receiving, by the reset signal RST input terminal, a scan signal outputted from an output terminal G(n+3) of the (N+3)th stage, wherein the (N+1)th stage is the previous stage, the (Nth) +3) The level is the next level.

As described above, the shift register according to an embodiment of the present invention may include a plurality of virtual stages. For example, as shown in FIG. 18A, the shift register may include a single virtual level disposed between the first to the sixty-fourth and the sixty-fifth to the twenty-eighth, wherein One to sixty-fourth stages are used to sequentially supply the gate pulse waves to the first to sixty-fourth gate lines GL1 to GL64, and the sixty-fifth to one hundred and twenty-eighth stages are used for the gate pulse wave It is sequentially supplied to the 65th to 128th gate lines GL65 to GL128. Although the number of gate lines per group is 64, the present invention is not limited thereto, and among the plurality of display times P1 and P3 in one frame, the level of the gate line activated corresponding to one display time may be Grouped, and a virtual level can be placed between these groups, as shown in FIG.

Although the above description has been described based on the forward operation performed from the first stage to the last stage, the present invention is not limited thereto and is applicable to the reverse operation performed from the last stage to the first stage, for example, where (N+1) The gate pulse output of the stage is followed by the operation of the virtual stage, followed by the operation of the Nth stage.

Each of these stages can be synchronized with a clock signal CLK to output a gate pulse signal to a gate line of the plurality of gate lines GL1 to GLn.

In addition, all stages can be supplied with a high supply voltage (VDD) from a high voltage source, a gate low voltage (VGL) from a low voltage source, a forward voltage FWD and a reverse voltage REV, and A touch enable signal can be provided for all virtual levels. The forward voltage FWD is generated as a gate high voltage (VGH) level in a forward scan mode and as a gate low voltage (VGL) level in a reverse scan mode. In contrast, the reverse voltage REV is generated as a gate high voltage (VGH) level in a reverse scan mode and as a gate low voltage (VGL) level in a forward scan mode.

<second and fourth shift register>

16B and 17B show the Nth, (N+1)th, (N+2)th, and (N+3)th stages as a plurality of shift registers constituting the second and fourth embodiments. level.

The Nth, (N+1)th, (N+2)th, and (N+3)th stages may pass the clock signal CLK line (in accordance with the second embodiment having the gate driver circuits 200a and 200b) In the case of the first and second clock signals CLK1 and CLK2 lines, at least two clock signals are provided. The first and second clock signals can have opposite logic levels. Each stage can receive one of the output signals of the adjacent stage as an activation signal VST, and receive another output signal of the adjacent stage as the reset signal RST.

A portion of these stages functions as a standby stage that maintains a Q node voltage during touch time. The standby stage can receive at least two clock signals through the clock signal line CLK, and receive the touch enable signals Touch EN (VTEN, VTEN1, VTEN2) through the touch enable signal line, and receive the output signals of the adjacent stages. One acts as a start signal VST and receives another output signal of the adjacent stage as the reset signal RST.

These stages can perform an operation for supplying a gate pulse signal upon receiving the start signal VST, and an operation for discharging the corresponding gate line upon receiving the reset signal RST.

In particular, the Nth stage includes an enable signal VST input terminal and a reset signal RST input terminal, and receives a gate outputted from an output terminal G(n-1) of the (N-1)th stage through the start signal VST input terminal. The pole scans the pulse wave signal, and receives a gate pulse signal outputted from an output terminal G(n+1) of the (N+1)th stage through the reset signal RST input terminal, wherein the (N-1)th stage is The first level, the (N+1) level is the next level.

The (N+1)th stage includes an activation signal VST input terminal and a reset signal RST input terminal, and receives a gate pulse wave signal outputted from an output terminal G(n) of the Nth stage through the start signal VST input terminal. And receiving, by the reset signal RST input, a scan signal outputted from an output terminal G(n+2) of the (N+2)th stage, wherein the Nth stage is the previous stage, and the (N+2)th stage is the next stage. .

The (N+2)th stage includes an activation signal VST input terminal and a reset signal RST input terminal, and receives an output from an output terminal G(n+1) of the (N+1)th stage through the start signal VST input terminal. a gate pulse signal, and receiving, by the reset signal RST input, a scan signal outputted from an output terminal G(n+3) of the (N+3)th stage, wherein the (N+1)th stage is the previous stage, The (N+3)th level is the next level.

In particular, the (N+1)th stage of these stages set to a standby stage can maintain its Q node using a gate high voltage (VGH) level touch enable signal (VTEN) during touch time. a voltage while preventing leakage current, and at the end of the touch time, in response to a clock signal of a gate high voltage (VGH) level supplied thereto, the gate scan signal is output through the output terminal G(n+1) Output to the next level, the (N + 2) level.

As described above, the shift register 210 according to an embodiment of the present invention may include a plurality of spare stages. For example, as shown in FIG. 18B, the shift register may have a sixty-fifth level as a backup level from the first to the sixty-fourth to the sixty-fifth to the twenty-eighth. The first to the sixty-fourth stages are for sequentially supplying a gate pulse signal to the first to sixty-fourth gate lines GL1 to GL64, and the sixty-fifth to one hundred and twenty-eighth stages are used for The gate pulse signals are sequentially supplied to the 65th to 128th gate lines GL65 to GL128. Although the number of gate lines per group is 64, the present invention is not limited thereto, and the number of gate lines of each group may be differently set based on one touch time and one driving period.

Each of the above stages can be synchronized with a clock signal CLK to output a gate pulse signal to a gate line of the gate lines GL1 to GLn.

In addition, the stages may be supplied with a high supply voltage (VDD) from a high voltage source, a gate low voltage (VGL) from a low voltage source, a forward voltage FWD and a reverse voltage REV, and All virtual levels can be provided with touch enable signals.

<Circuit diagram of the nth stage>

Figure 20 is a circuit diagram of an Nth stage constituting a shift register in accordance with an embodiment of the present invention.

Referring to FIG. 20, the Nth stage is not a standby stage or a virtual stage, and the stage of charging the Q node and sequentially outputting the gate pulse signal in synchronization with an input clock signal at the display time. The Nth stage may include a pull-up transistor Tup, a pull-down transistor Tdown, a first capacitor CQ, and a second capacitor CQB and additionally include a charge/discharge unit 211 and a Q-node stabilizer 212.

The above elements of the Nth stage are coupled as follows. The pull-up transistor Tup has a gate terminal coupled to a Q node, a terminal connected to a supply terminal of the first clock signal CLK1, and a source coupled to the output terminal G(n) of the Nth stage. extreme. A pull-down transistor for stably discharging the output during the discharge time has a gate terminal coupled to a QB node, a gate terminal coupled to the output terminal G(n) of the Nth stage, and coupled to the gate A source terminal of the input of the low voltage (VGL). The first capacitor CQ can be coupled to the input of the QB node and the gate low voltage (VGL). The second capacitor CQB can be coupled to the input of the Q node and the gate low voltage (VGL).

The charging/discharging unit 211 can charge or discharge the Q node. The charging/discharging unit 211 may include first and second transistors T1 and T2. The first transistor T1 has a gate terminal coupled to the output terminal G(n-1) of the (N-1)th stage, coupled to a terminal of an input terminal of the forward voltage FWD, and coupled to the Q A source extreme of a node. The second transistor T2 has a gate terminal coupled to the output terminal G(n+1) of the (N+1)th stage, coupled to a terminal of an input terminal of the reverse voltage REV, and coupled to the Q A source extreme of a node.

The Q node stabilizer 212 discharges the Q node and may include a third transistor T3. The third transistor T3 has a gate terminal coupled to the QB node, a terminal connected to the Q node, and a source terminal coupled to the input terminal of the gate low voltage (VGL). As shown in the figure, the QB node can be provided with a second clock signal CLK2 or can be coupled to a terminal for supplying the output signal or the Q node discharge time of the next stage in synchronization with the third transistor T3. A voltage. The second clock signal may be a clock signal having a level and a timing for controlling the third transistor T3 to be turned off when the first transistor T1 is turned on to charge the Q node, and according to the Q node self-starting when the Q node is in the gate When the pole pulse signal is discharged to the corresponding output terminal and discharged immediately, the third transistor T3 is controlled to be turned on.

Figure 21 is a circuit diagram of a standby stage.

<standby level>

Referring to FIG. 21, the standby stage (which is the standby stage of the standby stage provided in the shift register shown in FIG. 16B or FIG. 17B) maintains a charged Q node voltage at a touch time, and when this touches When the control time is terminated, a gate pulse signal is output through its output terminal in synchronization with an input clock signal. The standby stage may include a pull-up transistor Tup, a pull-down transistor Tdown, a first capacitor CQ, and a second capacitor CQB and additionally include a charge/discharge unit 211 and a Q-node stabilizer 212.

The components of the Nth stage as the standby stage are coupled as follows. The pull-up transistor Tup has a gate terminal coupled to a Q node, a terminal connected to a supply terminal of the first clock signal CLK1, and a source coupled to the output terminal G(n) of the Nth stage. extreme. The pull-down transistor has a gate terminal coupled to a QB node, a terminal connected to the output terminal G(n) of the Nth stage, and a terminal coupled to an input of a gate low voltage (VGL) The source is extreme. The first capacitor CQ can be coupled to the input of the QB node and the gate low voltage (VGL). The second capacitor CQB can be coupled to the input of the Q node and the gate low voltage (VGL).

The charging/discharging unit 211 can charge or discharge the Q node. The charging/discharging unit 211 may include first and second transistors T1 and T2. The first transistor T1 has a gate terminal coupled to the output terminal G(n-1) of the (N-1)th stage, coupled to the input of the touch enable signal (VTEN) or a forward voltage FWD. An extreme, and a source extreme coupled to the Q node. The second transistor T2 has a gate terminal coupled to the output terminal G(n+1) of the (N+1)th stage, coupled to a terminal of the input end of the touch enable signal (VTEN), and coupled Connect to a source terminal of the Q node.

The Q node stabilizer 212 discharges the Q node and may include a third transistor T3. The third transistor T3 has a gate terminal coupled to the supply end of the second clock signal CLK2, a terminal connected to the Q node, and a source terminal coupled to the input end of the touch enable signal (VTEN). .

Figure 22 is a circuit diagram of a virtual stage.

<virtual level>

Referring to FIG. 22, the virtual stage is provided at the level of the shift register of FIG. 16A or FIG. 17A, and is disposed between the Nth stage and the (N+1)th stage. The dummy stage may include a pull-up transistor Tup, a pull-down transistor Tdown, a first capacitor CQ, and a second capacitor CQB and additionally include a charge/discharge unit 211 and a Q-node stabilizer 212.

The components of the virtual stage are coupled as follows. The pull-up transistor Tup has a gate terminal connected to a Q node, a terminal connected to a supply terminal of the first clock signal CLK1, and a source connected to the output terminal G(n+1/2) of the virtual stage. extreme. The pull-down transistor has a gate terminal coupled to a QB node, a terminal connected to the output terminal G(n+1/2) of the dummy stage, and an input coupled to the gate low voltage (VGL) One source extreme of the end. The first capacitor CQ can be coupled to the input of the QB node and the gate low voltage (VGL). The second capacitor CQB can be coupled to the input of the Q node and the gate low voltage (VGL).

The charging/discharging unit 211 can charge or discharge the Q node. The charging/discharging unit 211 may include first and second transistors T1 and T2. The first transistor T1 has a gate terminal coupled to the output terminal G(n) of the Nth stage, coupled to a terminal of an input end of the touch enable signal (VTEN), and coupled to the Q node. One source is extreme. The second transistor T2 has a gate terminal coupled to the output terminal G(n+1) of the (N+1)th stage, coupled to a terminal of the input end of the touch enable signal (VTEN), and coupled Connect to a source terminal of the Q node.

The Q node stabilizer 212 discharges the Q node and may include a third transistor T3. The third transistor T3 has a gate terminal coupled to the supply end of the second clock signal CLK2, a terminal connected to the Q node, and a source terminal coupled to the input end of the touch enable signal (VTEN). .

<level forward and reverse drive method>

Figure 23 is a diagram showing the operation of the Q-node charging and the gate pulse output of the Nth stage in the forward driving operation. Figure 24 is a diagram showing the Q-node discharge and QB node charging of the Nth stage in the forward drive operation.

<display drive period: forward drive>

For a first period of display time P1, the first transistor T1 can be turned on by the output signal of the (N-1)th stage, so that the forward voltage FWD is supplied to the Q node, and the pull-up transistor Tup can be responsive according to The gate low voltage (VGL) level of the first clock signal CLK1 is turned on by self-activation, and thus the gate pulse wave of the gate high voltage (VGH) level is output to the output terminal G of the Nth stage ( n).

For a second period after the first period in the display time P1, the second transistor T2 is turned on by the output signal of the (N+1)th stage, so that the reverse voltage REV is supplied to the Q node to discharge the Q node, and The QB node is charged by a second clock signal CLK2 of a gate high voltage (VGH) level to turn on the third transistor T3 and the pull-down transistor Tdown, so that the output terminal G(n) of the Q node of the Nth stage They can be discharged by the gate low voltage (VGL).

Figure 25 is a diagram showing the Q-node charging and gate pulse wave output operation of the Nth stage in the reverse driving operation, and Figure 26 is a diagram showing the Q-node discharge and QB node charging of the Nth stage.

<display drive period: reverse drive>

For the first time period of the display time P1, the second transistor T2 may be turned on by the output signal of the (N+1)th stage, so that the reverse voltage REV is supplied to the Q node and the pull-up transistor Tup may be responsive to the first time. The gate low voltage (VGL) level of the pulse signal CLK1 is turned on by itself, and thus the gate pulse wave of the gate high voltage (VGH) level is output to the output terminal G(n) of the Nth stage.

For the second period after the first period in the display time P1, the first transistor T1 is turned on by the output signal of the (N-1)th stage, so that the forward voltage FWD is supplied to the Q node to discharge the Q node, and the QB node Charging by a second clock signal CLK2 of a gate high voltage (VGH) level to turn on the third transistor T3 and the pull-down transistor Tdown, so that the Q node and the output terminal G(n) of the Nth stage are respectively It can be discharged by the gate low voltage (VGL).

Only one of the first and second transistors T1 and T2 can operate in forward or reverse operation of the gate driver circuit 200 to provide a forward voltage FWD or a reverse voltage REV to the Q node. The forward voltage FWD may be higher than the reverse voltage REV during the forward drive operation and may be lower than the reverse voltage REV during the reverse drive operation.

<Forward-level forward drive method>

Figure 27 is a diagram showing the charging of the Q-th node of the Nth stage as a standby stage in the forward driving operation, Figure 28 is a diagram showing the holding time in which the Q-node voltage is held, and Figure 29 is a diagram showing the gate pulse. A diagram of the wave output operation. Fig. 30 is a diagram showing the discharge operation of the Q node and the output terminal, and Fig. 31 is a waveform diagram showing the standby stage for driving.

- Q node charging time

Referring to FIG. 27 and FIG. 31, at the display time P1 (or P3) before the contact control time P2 (or P4), the gate pulse signal can be output from the (N-1)th stage and the touch enable signal ( VTEN) can transition to a gate low voltage (VGL) level. Here, the first transistor T1 is turned on by the output signal of the (N-1)th stage, and thus the touch enable signal (VTEN) that transitions to a gate high voltage (VGH) level is supplied to the Q node for charging Q. node.

- Q-node voltage hold time (= touch time)

Referring to FIG. 28 and FIG. 31, the touch time P2 (or P4) starts and the voltage charged at the Q node is maintained at the touch time P2 (or P4). Here, the touch enable signal (VTEN) maintains a gate low voltage (VGL) level, and thus a gate low voltage (VGL) level voltage is supplied to the source terminal of the first transistor T1, and the second transistor T2 The 汲 extreme, and the source terminal of the third transistor T3. In this manner, the source-drain paths of the first, second, and third transistors T1, T2, and T3 can be removed by supplying a high-level voltage to their source or drain terminal, where the first, This source-drain path of the second and third transistors T1, T2, and T3 is the path through which leakage current can flow.

- Output time

Referring to FIG. 29 and FIG. 31, for the display time P3 after the touch time P2, the pull-up transistor Tup is turned on according to the self-activation of the gate low voltage (VGL) level of the first clock signal CLK1, and thus The gate pulse of the gate high voltage (VGH) level can be stably outputted through the output terminal G(n) of the Nth stage.

- Discharge time

Referring to FIG. 30 and FIG. 31, for the discharge time after the output time, the second transistor T2 is turned on by the (N+1)th output signal, so that the gate low voltage (VGL) level touch enable is enabled. A signal (VTEN) is supplied to the Q node to discharge the Q node, and a second clock signal CLK2 at a high level charges the QB node to turn on the third transistor T3 and the pull-down transistor Tdown, and thus the Q node of the Nth stage And the output terminal G(n) can be discharged by the gate low voltage (VGL).

<Virtual level forward drive method>

32 is a diagram showing charging of a virtual node Q node in a forward driving operation, FIG. 33 is a diagram showing a Q node voltage holding, and FIG. 34 is a diagram showing a gate pulse output operation. Fig. 35 is a view showing a discharge operation of the Q node and the output terminal, and Fig. 36 is a view showing a drive waveform of the virtual stage.

- Q node charging time

Referring to FIG. 32 and FIG. 36, for a first time period of the display time P1 immediately before the touch time P2, the gate pulse signal can be output from the Nth stage and the touch enable signal (VTEN) can be transitioned to a gate. Very high voltage (VGH) level. Here, the first transistor T1 is turned on by the output signal of the Nth stage, and thus the gate enable signal (VTEN) of the gate high voltage (VGH) level is supplied to the Q node to charge the Q node.

- Q node voltage hold time (= touch time)

Referring to FIG. 33 and FIG. 36, a voltage at which the touch time P2 starts and is charged at the Q node is maintained at the touch time P2. Here, the touch enable signal (VTEN) maintains a gate high voltage (VGH) level, and thus a gate high voltage (VGH) level voltage is supplied to the source terminal of the first transistor T1, and the second transistor T2 The 汲 extreme, and the source terminal of the third transistor T3. In this manner, the source-drain paths of the first, second, and third transistors T1, T2, and T3 can be removed by supplying a high-level voltage to their source or drain terminal, where the first, This source-drain path of the second and third transistors T1, T2, and T3 is the path through which leakage current can flow.

- Output time

Referring to FIG. 34 and FIG. 36, at the end of the touch time P2, the pull-up transistor Tup is turned on according to the self-activation of the gate low voltage (VGL) level in response to the first clock signal CLK1, and thus the gate is turned on. The carry signal Vc of the very high voltage (VGH) level can be stably outputted through the output terminal G (n + 1/2) of the virtual stage.

- Discharge time

Referring to FIG. 35 and FIG. 36, for the display time P3 after the output time, the second transistor T2 is turned on by the output signal of the (N+1)th stage, so that the gate low voltage (VGL) level touch is enabled. A power signal (VTEN) is supplied to the Q node to discharge the Q node, and a second clock signal CLK2 of a gate high voltage (VGH) level charges the QB node to turn on the third transistor T3 and the pull-down transistor Tdown, and thus The output of the virtual stage G(n+1/2) is discharged through the gate low voltage (VGL) at the Q node and the output.

In the case of the shift register according to the second and fourth embodiments (using a standby stage in which the touch time is the hold state without including a dummy stage), the Q node voltage hold time corresponds to the touch time, and In the case of the shift register according to the first and third embodiments (using a dummy stage in which the touch time is the hold state), the Q node voltage hold time and the output time correspond to the touch time.

Figure 37 is a waveform diagram showing a Q node voltage during operation of a standby stage or a dummy stage.

Referring to FIG. 37, the standby or virtual stage can maintain its voltage at the Q point and pass the touch enable signal (VTEN) corresponding to the gate high voltage (VGH) level of the high level power supply voltage during self-starting. This voltage can be increased by supplying a source or drain terminal opposite the Q node to a source-drain path, where the source-drain path is the path through which the Q-node can be charged. Therefore, a gate pulse signal output of a gate high voltage (VGH) level can eliminate the dimming phenomenon in which a horizontal line appears.

As described above, since a voltage of the Q node of the standby or virtual level can be maintained for one touch time, the number of touch times of one frame can be reduced and the duration of the touch time can be increased. In addition, a clock time at high resolution can be guaranteed by the margin between display time and touch time.

Although the respective stages of the transistor and the thin film transistor (TFT) of the display panel 100 described above are N-type transistors, the present invention is not limited thereto, and the first, second, and third transistors T1 in the stage of the display panel 100 are not limited thereto. T2 and T3, pull-up transistor Tup and pull-down transistor Tdown and thin film transistor (TFT) may be P-type transistors. In this case, the logic high or low level of all the above signals becomes logic low or high. Therefore, current leakage can be prevented by maintaining the source-drain voltages of the first, second, and third transistors T1, T2, and T3, thereby stably maintaining the voltage of the Q node of the corresponding stage during touch.

It will be appreciated by those skilled in the art that the present invention may be practiced otherwise than as specifically described herein without departing from the spirit and scope of the invention. The above-described embodiments are therefore to be considered in all respects illustrative illustrative The scope of the present invention is to be determined by the scope of the appended claims and the scope of the appended claims.

10‧‧‧Touch sensor channel unit
11‧‧‧Vcom buffer
12‧‧‧Switch array
13‧‧‧First timing control signal generator
14‧‧‧Multiplexer
15‧‧‧DTX compensation unit
16‧‧‧Sensor unit
17‧‧‧Second timing control signal generator
18‧‧‧ memory
19‧‧‧Microcontroller unit
21‧‧‧Charging/discharging unit
22‧‧‧Q node stabilizer
100‧‧‧ display panel
110‧‧‧ pixels
120‧‧‧pattern electrode
200, 200a, 200b‧‧‧ gate driver circuit
210‧‧‧Shift register
211‧‧‧Charging/discharging unit
212‧‧‧Q node stabilizer
300‧‧‧Data Drive Circuit
400‧‧‧Time Controller
402‧‧‧Level shifter
500‧‧‧Touch Driver Circuit
Tup‧‧‧ Pull-up crystal
Tdown‧‧‧ pull-down transistor
T1‧‧‧first transistor
T2‧‧‧second transistor
T3‧‧‧ third transistor
P1, P3‧‧‧ shows time
P2, P4‧‧‧ touch time
VGH‧‧‧ gate high voltage
VGL‧‧‧ gate low voltage
VTEN, VTEN1, VTEN2‧‧‧ touch enable signal
G(n)‧‧‧N-level output
Output of G(n-1)‧‧‧ (N-1)
G(n+1)‧‧‧ (N+1) output
G(n+1/2)‧‧‧ virtual stage output
Output of G(n+2)‧‧‧ (N+2)
Output of G(n+3)‧‧‧ (N+3)
CLK‧‧‧ clock signal
CLK1‧‧‧ first clock signal
CLK2‧‧‧ second clock signal
FWD‧‧‧ forward voltage
REV‧‧‧reverse voltage
CQ‧‧‧first capacitor
CQB‧‧‧second capacitor
GL1 to GLn‧‧‧ gate line
DL1 to DLm‧‧‧ data line
RST‧‧‧Reset signal
VST‧‧‧ start signal
Touch EN‧‧‧ touch enable signal
A‧‧‧
B‧‧‧
C‧‧‧Virtual level
GCS‧‧‧ gate control signal
DCS‧‧‧ control signal
N‧‧‧ non-display area
RGB‧‧‧ video data
DE‧‧‧ data enable signal
Hsync‧‧‧ horizontal sync signal
Vsync‧‧‧ vertical sync signal
DCLK‧‧‧ clock signal
SL‧‧‧Sensing line
A/A‧‧‧ display area
MEM‧‧‧ memory
DIC‧‧‧ drive integrated circuit
MCU‧‧‧Microcontroller Unit
TIC‧‧‧ touch integrated circuit
MUX C1-C3‧‧‧ signal
DTX DATA‧‧‧Output data
Vcom‧‧‧Common voltage
Vout‧‧‧ output
OUT‧‧‧ output
CLKB‧‧‧ clock
Vq‧‧‧Q node voltage
Vqb‧‧‧ voltage
Vds‧‧‧ voltage
Vgs‧‧‧ voltage
Vth‧‧‧ threshold voltage
Id‧‧‧汲polar current
DTX DATA‧‧‧Surface measuring device

1 is a diagram showing the Id of Vgs according to an n-type metal oxide semiconductor field effect transistor (MOSFET). 2 is a diagram showing the Id of Vgs according to a sub-threshold region of an n-type metal oxide semiconductor field effect transistor (MOSFET). 3 and 4 show an example of an example in which a Q node can be discharged in a gate driver circuit. 5, 6, 7, 8A, and 8B are diagrams showing the prevention of discharge of a Q node in accordance with an embodiment of the present invention. 9, 10 and 11 are views showing a driving device according to an embodiment of the present invention. FIG. 12 is a diagram showing a touch screen integrated display device including a single gate driver circuit and a driving unit thereof according to an embodiment of the invention. Figure 13 is a diagram showing a plurality of pixels of a display panel and corresponding pattern electrodes. Fig. 14 is a view showing the connection of a pattern electrode and a sensing line. FIG. 15 is a diagram showing a touch screen integrated display device including two gate driver circuits and a driving unit thereof according to an embodiment of the invention. Figure 16A is a diagram showing the connection of a plurality of stages constituting a shift register according to a first embodiment of the present invention. Figure 16B is a diagram showing the connection of a plurality of stages constituting a shift register according to a second embodiment of the present invention. Figure 17A is a diagram showing the connection of a plurality of stages constituting a shift register according to a third embodiment of the present invention. Figure 17B is a diagram showing the connection of a plurality of stages constituting a shift register according to a fourth embodiment of the present invention. Fig. 18A shows a diagram of forward and reverse gate scanning of the shift register according to the first and third embodiments. Fig. 18B shows a diagram of forward and reverse gate scanning of the shift register according to the second and fourth embodiments. Fig. 18C shows an example in which no virtual stage exists in a single direction (forward direction). Figure 18D is a diagram showing an example in which a shift register is added to a virtual stage C when driven in two directions. Fig. 19 is a timing chart showing time division display and touch drive operation. Figure 20 is a circuit diagram of an Nth stage constituting a shift register in accordance with an embodiment of the present invention. Figure 21 is a circuit diagram of a standby stage. Figure 22 is a circuit diagram of a virtual stage. Figure 23 is a diagram showing the operation of the Q-node charging and the gate pulse output of the Nth stage in the forward driving operation. Figure 24 is a diagram showing the Q-node discharge and QB node charging of the Nth stage in the forward drive operation. Figure 25 is a diagram showing the operation of the Q-node charging and the gate pulse output of the Nth stage in the reverse driving operation. Figure 26 is a diagram showing the Q-node discharge and QB node charging of the Nth stage in the reverse drive operation. Figure 27 is a diagram showing the charging of the Nth node of the Nth stage as a standby stage in the forward drive operation. Fig. 28 is a diagram showing the hold time in which the Q node voltage is held. Fig. 29 is a view showing a gate pulse wave output operation. Figure 30 is a diagram showing the discharge operation of the Q node and the output terminal. Figure 31 is a waveform diagram showing the driving of this standby stage. Figure 32 is a diagram showing the charging of a virtual node Q node in a forward drive operation. Figure 33 is a diagram showing the retention of a Q node voltage. Fig. 34 is a view showing a gate pulse wave output operation. Figure 35 is a diagram showing the discharge operation of the Q node and the output terminal. Fig. 36 is a view showing a driving waveform of a virtual stage. And Figure 37 is a waveform diagram showing a Q node voltage during operation of a standby stage or a virtual stage.

100‧‧‧ display panel

200‧‧ ‧ gate driver circuit

300‧‧‧Data Drive Circuit

400‧‧‧Time Controller

402‧‧‧Level shifter

500‧‧‧Touch Driver Circuit

N‧‧‧ non-display area

RGB‧‧‧ video data

DE‧‧‧ data enable signal

Hsync‧‧‧ horizontal sync signal

Vsync‧‧‧ vertical sync signal

DCLK‧‧‧ clock signal

GCS‧‧‧ gate control signal

DCS‧‧‧ control signal

A/A‧‧‧ display area

GL1 to GLn‧‧‧ gate line

DL1 to DLm‧‧‧ data line

Claims (20)

A display device includes: a display panel, wherein a plurality of data lines and a plurality of gate lines intersect and a plurality of pixels are arranged in a matrix form, the display panel includes a plurality of touch sensors; and a touch driver a circuit for driving the touch sensors; a data driver circuit for supplying a data signal to the data lines; and a gate driver circuit for supplying a plurality of gate pulses to the gate using a shift register And a timing controller that supplies data of an input image to the data driver circuit and controls operation of the data driver circuit and the gate driver circuit, wherein the timing controller generates a display time and a touch enable signal of a touch time, and the shift register includes a first stage in which the touch enable signal is input, wherein the stage includes: a Q node, controlling a pull-up transistor; and an electric The crystal includes a drain and a source connected to the Q node, and a high level voltage of the touch enable signal is supplied to the source during the touch time. The display device of claim 1, wherein a voltage between a gate and a source of the transistor during the touch time is lower than a threshold voltage of the transistor, and The voltage between the drain and the source of the transistor is zero during the touch time. The display device of claim 2, wherein the touch enable signal comprises a high level time that is further expanded compared to the touch time, and the touch enable signal is phased at the high level Compared with the start of the touch time, the time within one pulse pulse width is raised to the high level voltage, and within one pulse pulse width immediately after the end of the touch time The time drops to a low level, and in addition to the high level time, a low power time of the touch enable signal is the display time. The display device of claim 2, wherein the touch enable signal comprises a high level time, and the touch enable signal rises to the high level voltage when the touch time starts at the high level And when the touch time is terminated, it drops to a lower level to have the same time as the touch time. A driving device for a display device, the display device comprising a gate driver circuit, the gate driver circuit dividing a frame time into a display time and a touch time and supplying a gate pulse wave to the display device The driving device includes: a timing control circuit for generating a touch enable signal for defining the display time and the touch time, wherein during the touch time, the touch enable signal is high The gate voltage is supplied to the gate driver circuit, and the gate driver circuit includes a transistor, the transistor includes a drain connected to the Q node and a source, and the touch enable signal during the touch time A high level voltage is supplied to the source. The driving device of claim 5, wherein a voltage between a gate and a source of the transistor is lower than a threshold voltage of the transistor during the touch time, and the transistor A voltage between the gate and the source is at a minimum. The driving device of claim 6, wherein the touch enable signal is raised to a high level voltage from a time shorter than one pulse pulse width later than the start of the touch time, and The time within one pulse pulse width immediately after the end of the touch time drops to a low level. The driving device of claim 7, wherein the touch enable signal rises to the high level voltage when the touch time starts, and drops to a lower level when the touch time is terminated. A driving method of a display device, the display device divides a frame into a display time and a touch time driven by a time division, and the driving method of the display device includes: generating a touch that defines the display time and the touch time Controlling the enable signal; and reducing a discharge connected to the Q node by supplying a high level voltage of the touch enable signal to the gate driver circuit during the touch time according to a voltage of a Q node a voltage between a drain and a source of a transistor of the path, wherein the gate driver circuit is configured to supply a gate pulse wave to a gate line of the display device. The driving method of the display device of claim 9, wherein a voltage between a gate and a source of the transistor is lower than a threshold voltage of the transistor during the touch time, and The voltage between the gate and the source of the transistor is zero. A gate driver circuit divides a frame time into a display time and a touch time, and a touch enable signal becomes a first level or a second level during the touch time. The gate driver circuit includes: a shift register, wherein an Nth (N is a positive integer) level of the shift register comprises: a first transistor controlled by an output signal of a previous stage The touch enable signal having the first level is supplied to a Q node; a second transistor is controlled by an output signal of the next stage to enable the touch enable signal having the second level Supplying to the Q node; and a pull-up transistor controlled by a voltage of the Q node to output a first clock signal provided thereto to an Nth output terminal, wherein when the first transistor, the first transistor When the second transistor and the pull-up transistor system are N-type transistors, the first level is a high level and the second level is a low level, and when the first transistor When the second transistor and the pull-up transistor system are P-type transistors, the first level is A low level and the second level is a high level. The gate driver circuit of claim 11, wherein the Nth stage is a virtual level, and the display time includes a first display time before the touch time and a second time after the touch time. Displaying time, wherein the Q node is charged during the first display time, a carry signal is output through the Nth output during the touch time, and the Q node is discharged during the second display time. The gate driver circuit of claim 11, wherein the display time includes a first display time before the touch time and a second display time after the touch time, wherein the Q node is at the first Charging during the display time, and the gate pulse is output to the Nth output during the second display time. The gate driver circuit of claim 12, wherein the Nth stage further comprises a third transistor, the third transistor being controlled by the voltage of the Q node to supply the touch enable signal to the Q node. The gate driver circuit of claim 14, further comprising a pull-down transistor controlled by a voltage of a QB node to discharge the Nth output terminal. A touch screen integrated display device comprising: the gate driver circuit of claim 11; a panel for displaying an image; and a touch driver circuit for sensing a touch provided on the panel, wherein The panel includes a plurality of pixels grouped into a plurality of pixel groups, a plurality of pattern electrodes corresponding to the pixel groups, and the pattern electrodes are respectively connected to the sensing lines of the touch driver circuit. The touch screen integrated display device of claim 16, wherein the Nth level is a virtual level, and the display time includes a first display time before the touch time and after the touch time a second display time, wherein the Q node is charged during the first display time, a carry signal is output through the Nth output during the touch time, and the Q node is discharged during the second display time. The touch screen integrated display device of claim 16, wherein the display time includes a first display time before the touch time and a second display time after the touch time, wherein the Q node is Charging during the first display time, and the gate pulse is output to the Nth output during the second display time. The touch screen integrated display device of claim 17, wherein the Nth stage further comprises a third transistor, wherein the third transistor is controlled by a voltage of a QB node to supply the touch enable signal To the Q node. The touch screen integrated display device of claim 16, wherein the gate driver circuit further comprises a pull-down transistor controlled by the voltage of the QB node to supply a low level voltage to the gate Nth output.