TWI682379B - Gate driving circuit and display panel thereof - Google Patents

Abstract

A gate driving circuit and a display panel thereof are provided. The gate drive circuit includes a plurality of shift registers for providing a plurality of gate signals. Each of the shift registers includes a shift drive circuit, a first output transistor, a second output transistor, and a pull-down circuit. The shift drive circuit provides a first control voltage and a second control voltage. The first output transistor receives a clock signal and the first control voltage, and provides a corresponding gate signal. The second output transistor coupled to the first output transistor, and receives the second control voltage and a gate low voltage. The pull-down circuit receives a pull-down signal and the gate low voltage to align the falling time point of the corresponding gate signal to turn on the corresponding gate signal and the gate low voltage.

Description

Gate drive circuit and its display panel

The invention relates to a driving circuit, and in particular to a gate driving circuit and a display panel thereof.

In an active display panel, the gate drive circuit provides gate signals to the pixels to control the pixels to turn on and off. Moreover, as the resolution of the display panel increases, the delay of the gate signal (that is, the rise time and fall time) must be reduced to allow the pixels to have sufficient charging time. Generally speaking, the gate signal delay can be reduced by increasing the size of the output stage transistor, but this method is mainly to reduce the impedance of the output stage transistor itself, and when the size of the transistor reaches a certain level, The effect of reducing the delay time is not good, but it has a great impact on the border. Therefore, a new gate drive circuit is still needed to effectively shorten the delay time of the gate signal.

The invention provides a gate driving circuit and a display panel thereof, which can effectively reduce the delay of the gate signal.

The gate drive circuit of the present invention includes multiple displacement registers. These displacement registers are used to provide multiple gate signals. Each displacement register includes a displacement driving circuit, a first output transistor, a second output transistor, and a pull-down circuit. The displacement driving circuit provides a first control voltage and a second control voltage. The first output transistor has a first terminal that receives the clock signal, a control terminal that receives the first control voltage, and a second terminal that provides the corresponding gate signal. The second output transistor has a first end coupled to the second end of the first output transistor, a control end receiving the second control voltage, and a second end receiving the gate low voltage. The pull-down circuit receives the pull-down signal and the gate low voltage to align the corresponding gate signal's falling time point to turn on the corresponding gate signal and gate low voltage.

The display panel of the present invention includes the above-mentioned gate driving circuit, a plurality of pixels and a plurality of gate lines. The gate drive circuit is used to provide multiple gate signals. The gate lines are coupled to the gate driving circuit to individually receive one of the gate signals, and are individually coupled to some pixels.

Based on the above, the gate driving circuit and the display panel of the embodiment of the present invention pull down the corresponding gate signal through the pull-down circuit that receives the gate low voltage as a DC level, so as to effectively shorten the decline of the gate signal Time, which can effectively reduce the delay of the gate signal.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, and/or Or part should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, "first element", "component", "region", "layer" or "portion" discussed below may be referred to as a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, unless the content clearly indicates, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one." "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the term "comprising" and/or "comprising" specifies the features, regions, wholes, steps, operations, presence of elements and/or components, but does not exclude one or more The presence or addition of other features, regions as a whole, steps, operations, elements, components, and/or combinations thereof.

FIG. 1 is a system schematic diagram of a gate driving circuit according to an embodiment of the invention. Please refer to FIG. 1, in this embodiment, the gate driving circuit 100 is suitable for being configured on a display panel, and includes a plurality of shift registers (such as 110_n-1~110_n+1) connected in series, where n is a Guide number. Each shift register (such as 110_n-1~110_n+1) provides a corresponding gate signal (such as SROUT[n-1]~SROUT[n+1]). Each shift register (such as 110_n-1~110_n+1) includes a displacement driving circuit 111, a first output transistor MO1, a second output transistor MO2, and a pull-down circuit 113.

The displacement driving circuit 111 receives the gate signal (such as SROUT[n-1]) provided by the previous stage displacement register (such as 110_n-1) and the gate signal provided by the next stage displacement register (such as 110_n+1) ( For example, SROUT[n+1]), to provide the first control voltage Q and the second control voltage P, where the first control voltage Q and the second control voltage P enable at most one of them.

The first output transistor MO1 has a first terminal that receives a clock signal (such as CLK, XCLK), a control terminal that receives a first control voltage Q, and a second terminal that provides a corresponding gate signal (such as SROUT[n]). The second output transistor MO2 has a first terminal coupled to the second terminal of the first output transistor MO1, a control terminal receiving the second control voltage P, and a second terminal receiving the gate low voltage VGL.

The pull-down circuit 113 receives the pull-down signal SX and the gate low voltage VGL to align the corresponding gate signal (such as SROUT[n]) and turn on the corresponding gate signal (such as SROUT[n]) and the gate Very low voltage VGL, where the pull-down signal SX may be provided by an external control circuit outside the display panel configured with the gate driving circuit 100. Since the gate low voltage VGL is a direct current (DC) level, that is, there is no load effect, it can effectively shorten the fall time of the gate signal (such as SROUT[n-1]~SROUT[n+1]), which can be effectively Reduce the delay of the gate signal (such as SROUT[n-1]~SROUT[n+1]).

In this embodiment, the first control voltage Q and the second control voltage P enable at most one of them, that is, the first output transistor MO1 and the second output transistor MO2 are turned on at most one of them. In addition, the first control voltage Q may be related to the gate signal (such as SROUT[n-1]) provided by the previous stage shift register (such as 110_n-1), and the second control voltage P may be related to the next stage shift register The gate signal (such as SROUT[n+1]) provided by the device (such as 110_n+1), but the embodiment of the present invention is not limited to this.

FIG. 2 is a timing diagram of FIG. 1 according to an embodiment of the invention for pulling down a signal. Please refer to FIGS. 1 and 2. In this embodiment, the pull-down signal SX is aligned with the falling time point TA of the corresponding gate signal (such as SROUT[n]) to enable (for example, switch from the low voltage level to the high voltage level Bit) to turn on the pull-down circuit 113; and, the pull-down signal SX is aligned with the rise time of the gate signal (eg SROUT[n+1]) of the next stage following the corresponding gate signal (eg SROUT[n]) The point TB is disabled (for example, switching from a high voltage level to a low voltage level) to cut off the pull-down circuit 113.

In the embodiment of the present invention, the pull-down signal SX can be disabled earlier than the rising time point TB of the gate signal of the next stage (such as SROUT[n+1]), which corresponds to what the pull-down circuit 113 can provide The on-current (or driving capability) and the load effect of the output terminal of the displacement register (such as 110_n-1~110_n+1) are determined, and the embodiments of the present invention are not limited thereto.

FIG. 3 is a system schematic diagram of a shift register according to an embodiment of the invention. 1 and 3, in this embodiment, the pull-down circuit 113a of the shift register 110a includes the first transistor M1. The first transistor M1 has a first terminal coupled to the corresponding gate signal (such as SROUT[n]), a control terminal receiving the pull-down signal SX, and a second terminal receiving the gate low voltage VGL.

FIG. 4 is a system schematic diagram of a shift register according to another embodiment of the invention. Please refer to FIGS. 1 and 4. In this embodiment, the pull-down circuit 113 b of the shift register 110 b further receives the first control voltage P, and is turned on in response to the pull-down signal SX and the first control voltage Q. Further, the pull-down circuit 113b includes a second transistor M2 and a third transistor M3. The second transistor M2 has a first terminal coupled to a corresponding gate signal (such as SROUT[n]), a control terminal, and a second terminal that receives the gate low voltage VGL. The third transistor M3 has a first terminal receiving the pull-down signal SX, a control terminal receiving the first control voltage Q, and a second terminal coupled to the control terminal of the second transistor M2.

According to the above, when the first control voltage Q is enabled, the pull-down circuit 113b will operate. In other words, when the shift register 110b is in an operating state, the pull-down circuit 113b included in the shift register 110b is activated, so that the pull-down circuit 113b in operation can be reduced, thereby reducing the overall power consumption.

In this embodiment, since the second transistor M2 is a voltage-controlled element, the current requirement is low, that is, the third transistor M3 has a low conduction requirement, so the aspect ratio of the third transistor M3 It may be much smaller than the aspect ratio of the second transistor M2.

5 is a schematic diagram of a system of a display panel according to an embodiment of the invention. Please refer to FIG. 5. In this embodiment, the display panel 10 includes a pixel array 11 and a gate driving circuit 12. The gate driving circuit 12 is used to provide a plurality of gate signals (such as SG1~SGm), and includes a plurality of shift registers (such as SR_1~SR_m) connected in series, where m is a positive integer. The pixel array 11 includes a plurality of pixels PX arranged in an array and a plurality of gate lines GL, wherein the gate lines GL are coupled to the gate driving circuit 12 to individually receive one of the gate signals (such as SG1~SGm) One, and each pixel PX is individually coupled to individually transmit gate signals (such as SG1~SGm) to the corresponding pixel PX.

In this embodiment, the shift registers (such as SR_1~SR_m) may refer to FIG. 1, FIG. 3, or FIG. 4, which will not be repeated here. In addition, the i-1th shift register and the ith shift register in the shift registers (such as SR_1~SR_m) receive the same pull-down signal (such as SX1~SXj), where i is greater than or equal to 2 Even number, j is m/2. For example, the first shift register SR_1 and the second shift register SR_2 jointly receive the same pull-down signal SX1, and so on for the rest. According to the above, the number of pull-down signals required by the display panel 10 is m/2, thereby reducing the power consumption of the pull-down circuits (such as 113, 113a, and 113b).

6 is a schematic diagram of a system of a display panel according to another embodiment of the invention. Referring to FIGS. 5 and 6, in this embodiment, the display panel 20 is substantially the same as the display panel 10, and the difference is the gate drive circuit 22 of the display panel 20. In this embodiment, multiple odd-numbered shift registers (such as SR_1, SR_3, ..., etc.) in the shift registers (such as SR_1~SR_m) jointly receive the first pull-down signal SXa as the received pull-down signal , And multiple even-numbered shift registers (such as SR_2, SR_4, ..., etc.) in the shift registers (such as SR_1~SR_m) jointly receive the second pull-down signal as SXb as the received pull-down signal. In this embodiment, the enable period of the first pull-down signal SXa does not overlap in timing with the enable period of the second pull-down signal SXb, and the number of pull-down signals required by the display panel 20 is 2, This can reduce the wiring quantity and complexity of the pull-down circuits (such as 113, 113a, and 113b).

In summary, the gate driving circuit and the display panel of the embodiment of the present invention pull down the corresponding gate signal through the pull-down circuit that receives the gate low voltage as a DC level, so as to effectively shorten the gate signal The fall time can further effectively reduce the delay of the gate signal.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10.20‧‧‧Display panel 11‧‧‧Pixel array 100, 12, 22 ‧‧‧ gate drive circuit 110_n-1~110_n+1, 110a, 110b, SR_1~SR_m‧‧‧shift register 111‧‧‧ Displacement drive circuit 113, 113a, 113b ‧‧‧ pull down circuit CLK, XCLK‧‧‧clock signal GL‧‧‧Gate line M1‧‧‧ First transistor M2‧‧‧second transistor M3‧‧‧The third transistor MO1‧‧‧ First output transistor MO2‧‧‧Second output transistor P‧‧‧ Second control voltage PX‧‧‧ pixels Q‧‧‧ First control voltage SROUT[n-1]~SROUT[n+1], SG1~SGm‧‧‧‧Gate signal SX, SX1~SXj ‧‧‧ pull low signal SXa‧‧‧First pull down signal SXb‧‧‧Second pull low signal TA‧‧‧drop time TB‧‧‧ rise time VGL‧‧‧gate low voltage

FIG. 1 is a system schematic diagram of a gate driving circuit according to an embodiment of the invention. FIG. 2 is a timing diagram of FIG. 1 according to an embodiment of the invention for pulling down a signal. FIG. 3 is a system schematic diagram of a shift register according to an embodiment of the invention. FIG. 4 is a system schematic diagram of a shift register according to another embodiment of the invention. 5 is a schematic diagram of a system of a display panel according to an embodiment of the invention. 6 is a schematic diagram of a system of a display panel according to another embodiment of the invention.

100‧‧‧ gate drive circuit

110_n-1~110_n+1‧‧‧shift register

111‧‧‧ Displacement drive circuit

113‧‧‧Pull down circuit

CLK, XCLK‧‧‧clock signal

MO1‧‧‧ First output transistor

MO2‧‧‧Second output transistor

P‧‧‧ Second control voltage

Q‧‧‧ First control voltage

SROUT[n-1]~SROUT[n+1]‧‧‧Gate signal

SX‧‧‧Pull down signal

VGL‧‧‧gate low voltage

Claims (11)

A gate drive circuit includes: a plurality of displacement registers for providing a plurality of gate signals, and each of the displacement registers includes: a displacement drive circuit that provides a first control voltage and a second control voltage A first output transistor with a first terminal to receive a clock signal, a control terminal to receive the first control voltage and a second terminal to provide the corresponding gate signal; a second output transistor with A first terminal coupled to the second terminal of the first output transistor, a control terminal receiving the second control voltage, and a second terminal receiving a gate low voltage; and a pull-down circuit to receive a pull-down circuit The low signal and the gate low voltage are turned on to align the corresponding gate signal with the gate low voltage in accordance with a falling time point of the corresponding gate signal. The gate drive circuit as described in item 1 of the patent application range, wherein the pull-down circuit includes: a first transistor having a first end coupled to the corresponding gate signal, and a control to receive the pull-down signal Terminal and a second terminal receiving the gate low voltage. The gate drive circuit as described in item 1 of the patent application range, wherein the pull-down circuit further receives the first control voltage to turn on in response to the pull-down signal and the first control voltage. The gate drive circuit as described in item 3 of the patent application range, wherein the pull-down circuit includes: a second transistor having a first terminal coupled to the corresponding gate signal, a control terminal, and receiving the gate A second terminal of low voltage; and a third transistor having a first terminal receiving the pull-down signal, a control terminal receiving the first control voltage, and a control terminal coupled to the second transistor The second end. The gate drive circuit as described in item 4 of the patent application range, wherein the aspect ratio of the third transistor is much smaller than the aspect ratio of the second transistor. The gate drive circuit as described in item 1 of the patent application range, wherein the odd-numbered shift registers in the shift registers collectively receive a first pull-down signal as the received pull-down signal, and The even-numbered shift registers in the shift registers collectively receive a second pull-down signal as the received pull-down signal. The gate drive circuit as described in item 6 of the patent application range, wherein the enable period of the first pull-down signal does not overlap with the enable period of the second pull-down signal in timing. The gate drive circuit as described in item 1 of the patent application scope, wherein the i-1th shift register and the ith shift register in the shift registers jointly receive the same pull-down signal, where i It is an even number greater than or equal to 2. The gate driving circuit as described in item 1 of the patent application range, wherein the pull-down circuit is aligned at a rising time point of the next gate signal following the corresponding gate signal in timing and is turned off. The gate drive circuit as described in item 1 of the patent application range, wherein the pull-down signal is provided by an external control circuit. A display panel, including: a gate drive circuit as described in item 1 of the patent application scope for providing a plurality of gate signals; a plurality of pixels; and a plurality of gate lines coupled to the gate drive circuit One of the gate signals is individually received, and the pixels are partially coupled.

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