KR101666298B1 - Shift register, driving device based on direct current type and method thereof - Google Patents

Abstract

The present invention relates to an oscillator circuit comprising: a charging section for charging a first node to a gate high voltage (VGH) level by a start signal or a drive signal of a first stage shift register and a first clock signal; A bootstrap portion for bootstrapping a first node charged to the gate high voltage level by a signal to the gate high voltage level or higher, a bootstrap portion for bootstrapping a bootstrapped first node (VGL) to the bootstrapped first node and the output signal by a first clock inversion signal and a second clock inversion signal, And a discharging unit for discharging the discharging current to the level, the driving apparatus and the operation method thereof.

Description

Technical Field [0001] The present invention relates to a direct current type shift register, a direct current type shift register,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct current type shift register, a driving apparatus, and a method of operating the same, and more particularly, to a direct current type shift register, a driving apparatus and a method of operating the same.

An alternating current (AC) type shift register is formed based on a plurality of thin film transistors (TFT), and a pull-up TFT and a clock signal are connected to the output terminal.

In addition, the AC type shift register can increase the voltage to the Q node using the bootstrapping effect of the pull-up thin film transistor, and the degree of freedom with respect to the pulse width of the output can be increased.

On the other hand, the AC type shift register has a problem that the power consumption of the pull-up thin film transistor increases due to the capacitive load existing in the clock signal.

In order to solve the above-described problems, a direct current type shift register technique has been developed in which a direct current (DC) type power source of fixed voltage is connected instead of a clock signal to an output terminal.

A DC type shift register technique using a thin film transistor including amorphous silicon (Prior Art 1) and a conventional technology in which a DC type power source of fixed voltage is connected to an output terminal instead of a clock signal, There is a direct current type shift register technology using a thin film transistor including silicon oxide (prior art 2).

The prior arts 1 and 2 reduce the capacitive load present in the clock signal and reduce the power consumption of the clock signal end.

However, in the prior arts 1 and 2, there is still a problem in that power consumption is increased by using many thin film transistors such as 11 and 22, and the overlap control between the output signals present in the neighboring thin film transistors There was a difficult problem.

Accordingly, it is an object of the present invention to solve the problem of reducing the power consumption due to the clock signal of the AC type shift register, the power consumption caused by the plurality of thin film transistors of the DC type, and adjusting the overlap between the output signals in the DC type shift register We need means.

The present invention provides a DC type shift register, a driving device, and an operation method thereof, which reduces power consumption caused by a clock signal by connecting a DC type power supply having a fixed voltage to an output terminal.

The present invention provides a DC type shift register, a driving apparatus, and an operation method thereof, which are driven with low power using at least two thin film transistors suitable for operating characteristics of a low temperature polycrystalline silicon.

The present invention relates to a direct current type shift register, a driving device, and a method of operating the same, which adjust an overlap between output signals without a circuit change by a predetermined delay of input clock signals such as a first clock signal and a second clock signal to increase an output time to provide.

The DC type shift register according to an embodiment of the present invention includes a charging unit for charging a first node to a gate high voltage (VGH) level by a driving signal of a start signal or a first-stage shift register and a first clock signal, A bootstrap section for bootstrapping a first node charged to the gate high voltage level by a second clock signal having a more predetermined delay than the gate high voltage level, A charge holding unit for holding an output signal output from the bootstrapped first node at the gate high voltage level during a bootstrapped first node and a bootstrapped first node by a first clock inversion signal and a second clock inversion signal, And discharging the output signal to a gate low voltage (VGL) level.

A DC type shift register according to an embodiment of the present invention includes first through ninth switching thin film transistors (TFTs) including low temperature polycrystalline silicon (LTPS) and a bootstrap capacitor, And a gate-low voltage is selectively supplied.

The first switching TFT is turned on to supply the start signal or the driving signal of the first-stage shift register and the first clock signal to the first node, and the third switching TFT is turned off the first node is turned off to charge the first node to the gate high voltage level, and the sixth switching TFT is turned on by the charged first node to turn on the bootstrap existing between the first node and the second node, The fourth switching TFT and the fifth switching TFT are turned on to discharge the third node to the gate low voltage level, and the seventh switching TFT and the fifth switching TFT are turned off by the discharged third node, The ninth switching TFT is turned off and the eighth switching TFT is turned on by the charged first node to charge the output signal, It can be filled with the difference between the pressure level and the threshold voltage of the eighth switching TFT.

Wherein the bootstrap portion is configured such that the first switching TFT and the third switching TFT are turned off to float the charged first node and the sixth switching TFT is turned on to turn the second clock signal to the second node And bootstrapping the floating first node by the bootstrap capacitor to charge the floating node to the gate high voltage level or higher and turning on the eighth switching TFT by the bootstrapped first node, Output signal to the gate high voltage level.

Wherein the discharging portion supplies the first clock inverted signal and the second clock inverted signal to the third switching TFT when the second switching TFT is turned on and the third switching TFT is turned on, The sixth switching TFT and the eighth switching TFT are turned off by a first node discharged at the gate low voltage level, and the fourth switching TFT is turned on to charge the third node , The seventh switching TFT and the ninth switching TFT may be turned on by the charged third node to discharge the second node and the output signal to the gate low voltage level.

The driving apparatus according to the embodiment of the present invention includes N shift registers in which a part of the driving signals for the neighboring shift registers overlap.

In the N shift registers, the nth shift register (where n is a natural number equal to or greater than 1 and equal to or smaller than N) is connected to the first node by the start signal or the (n-1) th drive signal and the first clock signal, A bootstrap for bootstrapping a first node charged to the gate high voltage level by the second clock signal having a predetermined delay than the first clock signal to the gate high voltage level or higher, A charge hold unit for holding the nth drive signal output from the bootstrapped first node during the supply of the second clock signal to the gate high voltage level, and a second clock inversion signal generating unit for generating a first clock inversion signal and a second clock inversion signal, And a discharging unit discharging the bootstrapped first node and the nth driving signal to a gate low voltage level.

The DC type driving apparatus according to another embodiment of the present invention in which a part of the driving signals for the neighboring shift registers overlap in the plurality of shift registers may include a plurality of shift registers and a predetermined number of shift registers in consideration of the characteristics of the low temperature polycrystalline silicon A power supply for supplying the DC type power to each shift register including a switching TFT and a bootstrap capacitor, and a clock for performing at least one of charging, bootstrapping, charge holding and discharging in each shift register And a clock generator for generating a signal.

The driving apparatus according to another embodiment of the present invention may further include a controller for controlling the DC type power supply and the generated clock signal to be provided to the plurality of shift registers.

The clock generator includes a first clock generator for generating a first clock signal for charging the first node to a gate high voltage level in each shift register, a first clock generator for generating a first high- A second clock generator for generating a second clock signal having a predetermined delay than the first clock signal for bootstrapping the first clock signal, the second clock generator generating a first clock inversion signal that is an inverted signal of the first clock signal And a second inverted clock generator for generating a second inverted clock signal which is an inverted signal of the second clock signal.

The control unit controls the selected delay to overlap a part of the driving signal with respect to the neighboring shift register by the predetermined delay, and generates, based on the first clock inversion signal and the second clock inversion signal in each shift register The bootstrapped first node and the drive signal to be discharged to a gate low voltage level.

A method of operating a direct current type shift register according to an embodiment of the present invention includes charging a first node to a gate high voltage level by a start signal or a drive signal of a first stage shift register and a first clock signal, Bootstrapping a first node charged to the gate high voltage level by a second clock signal having a more predetermined delay than the gate high voltage level, Maintaining the output signal from the first node at the gate high voltage level, and maintaining the bootstrapped first node and the output signal at a gate low voltage level by a first clock inversion signal and a second clock inversion signal, .

The operation method of the DC type driving apparatus according to the embodiment of the present invention includes a method of operating N shift registers in which a part of driving signals for neighboring shift registers overlap.

The operation method of the n-th shift register (where n is a natural number equal to or greater than 1 and equal to or smaller than N) in the N shift registers is performed by the start signal or the (n-1) Charging a first node charged with the gate high voltage level by a second clock signal having a predetermined delay to the gate high voltage level, Maintaining the nth drive signal output at the bootstrapped first node at the gate high voltage level while the second clock signal is being supplied, and maintaining the first clock inversion signal and the second clock inversion signal at And discharging the bootstrapped first node and the nth drive signal to a gate low voltage level.

A method of operating a direct current type driving device according to another embodiment of the present invention in which a part of a driving signal for a neighboring shift register overlaps in a plurality of shift registers according to another embodiment of the present invention includes a predetermined number of switching TFTs considering characteristics of low temperature polycrystalline silicon, Supplying the DC type power to each shift register including a bootstrap capacitor, and generating a clock signal for performing at least one of charging, bootstrapping, charge holding, and discharging in each shift register .

The present invention can reduce the power consumption due to the clock signal by connecting a DC voltage source of fixed voltage to the output terminal.

The present invention can be driven with low power using at least two thin film transistors suitable for the operating characteristics of the low temperature polycrystalline silicon.

The present invention can increase the output time by adjusting the overlap between the output signals without changing the circuit by the predetermined delay of the input clock signals such as the first clock signal and the second clock signal.

1A is a block diagram illustrating an AC type driving apparatus.
FIG. 1B is a diagram illustrating the AC type shift register circuit of FIG. 1A.
1C is a diagram illustrating a timing diagram for the AC type shift register of FIG. 1A.
2A is a diagram illustrating an output stage for an AC type shift register.
2B is a diagram illustrating an output stage for a DC type shift register.
3A is a diagram illustrating a DC type shift register circuit using a thin film transistor including amorphous silicon.
3B is a diagram illustrating a DC type shift register circuit using a thin film transistor including an oxide silicon.
4 is a block diagram illustrating a DC type shift register according to an embodiment of the present invention.
5 is a diagram illustrating a circuit for the DC type shift register of FIG.
6A is a diagram illustrating the operation of the circuit for the charging period of FIG.
FIG. 6B is a diagram illustrating the operation of the circuit for the bootstrap section of FIG.
6C is a diagram illustrating the operation of the circuit for the charge hold period of FIG.
6D is a diagram illustrating the operation of the circuit for the discharge interval of FIG.
FIG. 6E is a diagram illustrating a timing diagram for the four sections of FIG. 5. FIG.
7 is a block diagram showing a DC type driving apparatus according to an embodiment of the present invention.
8 is a block diagram illustrating a direct current type driving apparatus according to another embodiment of the present invention.
9A is a diagram illustrating a circuit for a direct current type driving apparatus including the sixteen shift registers of FIG.
FIG. 9B is a diagram illustrating an output waveform of the tenth shift register in the DC type driving apparatus of FIG. 8; FIG.
10 is a flowchart illustrating an operation method of a direct current type shift register according to an embodiment of the present invention.
11 is a flowchart illustrating an operation method of a DC type driving apparatus according to an embodiment of the present invention.
12 is a flowchart illustrating an operation method of a direct current type driving apparatus according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and accompanying drawings, but the present invention is not limited to or limited by the embodiments.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terminology used herein is a term used for appropriately expressing an embodiment of the present invention, which may vary depending on the user, the intent of the operator, or the practice of the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

FIG. 1A is a block diagram illustrating an AC type driving apparatus, FIG. 1B is a diagram illustrating an AC type shift register circuit of FIG. 1A, and FIG. 1C is a diagram illustrating a timing diagram of the AC type shift register of FIG. 1A .

Referring to FIG. 1A, an alternating current (AC) type driving apparatus includes a plurality of AC type shift registers, a power supply unit (not shown), and a clock generating unit (not shown).

Each AC type shift register may include a plurality of thin film transistors (N1 to N8) as shown in FIG. 1B, and a pull-up TFT (N7 And a clock signal CLK may be connected.

The power supply unit may supply AC type power to each AC type shift register including a plurality of thin film transistors.

The clock generator may supply a clock signal to an output terminal connected to the pull-up thin film transistor N7 of each AC type shift register.

Here, the AC type shift register can increase the voltage to the Q node Q [n] using the bootstrapping effect of the pull-up thin film transistor N7, and the degree of freedom with respect to the pulse width of the output can be increased have.

For example, referring to FIG. 1C, an AC type shift register can provide a clock signal to a desired line through a clock generator, and a rising transition occurs in a floating state of a Q node, An effect may be generated and the voltage for the Q node becomes higher than the power supply level by the bootstrapping effect so that the power supply level can be matched with the voltage G [n] for the output signal.

On the other hand, the AC type shift register has a problem that the power consumption of the pull-up thin film transistor increases due to the capacitive load existing in the clock signal. Hereinafter, a DC type shift register to which a direct current (DC) type power supply with a fixed voltage is connected will be described in detail with reference to FIGS. 2A, 2B, 3A and 3B in order to solve the above problems.

FIG. 2A is a diagram illustrating an output terminal for an AC type shift register, and FIG. 2B is a diagram illustrating an output terminal for a DC type shift register.

2A, an advantage of the AC type shift register is that the voltage to the Q node can be increased by using the bootstrapping effect of the pull-up thin film transistor, and the degree of freedom with respect to the pulse width of the output can be increased.

On the other hand, the AC type shift register can increase the power consumption of the pull-up thin film transistor due to the capacitive load present in the clock signal.

Referring to FIG. 2B, an advantage of the direct current type shift register is that the direct current type power supply (VGH) having a fixed voltage is connected to the output terminal to reduce a capacitive load existing in the clock signal, thereby reducing power consumption.

A DC type shift register may have a separate bootstrap capacitor to bootstrap the voltage at the Q node.

A disadvantage of the direct current type shift register is that the number of thin film transistors can be increased, so that power consumption due to the plurality of thin film transistors can be increased, and the area of the circuit can be increased.

3A is a diagram illustrating a DC type shift register circuit using a thin film transistor including amorphous silicon, and FIG. 3B is a diagram illustrating a DC type shift register circuit using a thin film transistor including an oxide silicon.

3A and 3B, a direct current type shift register circuit (Prior Art 1) using a thin film transistor including amorphous silicon (a-Si) includes 11 thin film transistors (M1 to M11 in FIG. 3A) And a direct current type shift register circuit using a thin film transistor including oxide silicon (Prior Art 2) may include 22 thin film transistors (N1 to N22 in FIG. 3B).

The prior arts 1 and 2 reduce the capacitive load present in the clock signal and reduce the power consumption of the clock signal end.

However, in the prior arts 1 and 2, there is a problem that power consumption is still increased by using many thin film transistors such as 11 and 22, and the overlap control between the output signals existing in the neighboring thin film transistors This difficult problem may exist.

Hereinafter, embodiments of the present invention in which the power consumption due to the clock signal of the AC type shift register is reduced, the power consumption caused by the plurality of thin film transistors of the DC type is reduced, and the overlap between the output signals in the DC type shift register is controlled Will be described in detail.

4 is a block diagram illustrating a DC type shift register according to an embodiment of the present invention.

4, the direct current type shift register 400 includes a charging unit 410, a bootstrap unit 420, a charge holding unit 430, and a discharging unit 440. Here, the charging part 410, the boot strap part 420, the charge holding part 430 and the discharge part 440 of the DC type shift register 400 use a plurality of switching TFTs (thin film transistors) and bootstrap capacitors .

5 is a diagram illustrating a circuit for the DC type shift register of FIG.

Referring to FIG. 5, the circuit for the DC type shift register 400 includes first through ninth switching TFTs T1, T2, ..., T9 including low temperature polycrystalline silicon (LTPS) And the gate high voltage (VGH) and the gate low voltage (VGL) are selectively supplied using the capacitor (C1).

The DC type shift register 400 includes four clock signals such as a first clock signal CLK1, a second clock signal CLK2, a first clock inversion signal CLK1b, and a second clock inversion signal CLK2b, The first through ninth switching TFTs T1, T2, ..., T9 and the bootstrap capacitor C1 can be operated by two direct current type power supplies such as a high voltage VGH and a gate low voltage VGL, It can be divided into four operation sections (charge section, bootstrap section, charge maintenance section, discharge section, etc.).

5, the first switching TFT T1 is switched by the start signal or the driving signal Q [n-1] of the previous-stage shift register, and one end of the first switching TFT T1 is turned off 1 clock signal, and the other end may be connected to the first node Q [n].

The second switching TFT T2 is switched by the second clock inversion signal CLK2b and one end of the second switching TFT T2 is connected to the first clock inversion signal CLK1b and the other end is connected to the third switching TFT T3.

The third switching TFT T3 is switched by the inverted signal A [n] applied from the second switching TFT T2 and the other end of the third switching TFT T3 is switched to the first node Q [n] And the other end may be connected to the gate-low voltage VGL.

The fourth switching TFT T4 is switched by the gate high voltage VGH and one end of the fourth switching TFT T4 is connected to the gate high voltage VGH and the other end is connected to the third node Qb [n] Lt; / RTI >

The fifth switching TFT T5 is switched by the first node Q [n], one end of the fifth switching TFT T5 is connected to the third node Qb [n], and the other end is switched to the gate low voltage (VGL).

The sixth switching TFT T6 is switched by the first node Q [n], one end of the sixth switching TFT T6 is connected to the second clock signal CLK2, and the other end is connected to the second node B [n]).

The seventh switching TFT T7 is switched by the third node Qb [n], one end of the seventh switching TFT T7 is connected to the second node B [n] (VGL).

The eighth switching TFT T8 is switched by the first node Q [n], one end of the eighth switching TFT T8 is connected to the gate high voltage VGH and the other end is connected to the ninth switching TFT T9 .

The ninth switching TFT T9 is switched by the third node Qb [n], one end of the ninth switching TFT T9 is connected to the eighth switching TFT T8 and the other end is connected to the gate low voltage VGL, Lt; / RTI > At this time, the output signal V _g [n] may exist between the other end of the eighth switching TFT T8 and one end of the ninth switching TFT T9.

One end of the bootstrap capacitor C1 may be connected to the first node Q [n] and the other end may be connected to the second node B [n].

Here, the first node Q [n] includes a first switching TFT T1, a third switching TFT T3, a fifth switching TFT T5, a sixth TFT switching TFT T6, an eighth switching TFT, And may be connected to the bootstrap capacitor C1.

In addition, the second node B [n] is connected to the sixth switching TFT T6, the seventh switching TFT T7 and the bootstrap capacitor C1, and the third node Qb [n] And may be connected to the switching TFT T4, the fifth switching TFT T5, the seventh switching TFT T7, and the ninth switching TFT T9.

Hereinafter, the DC type shift register 400 will be described in detail with reference to FIGS. 6A to 6E.

6A is a diagram illustrating the operation of the circuit for the charging period of FIG.

Referring to FIG. 6A, the charger 410 converts the first node Q [n] into a gate signal by the start signal or the drive signal Q [n-1] of the immediately prior stage shift register and the first clock signal CLK1. Charge at a high voltage (VGH) level.

For example, when the direct current type shift register 400 is the first register to be started, the first node Q [n] is switched to the gate high voltage VGH (VGH) by the charging unit 410 start signal and the first clock signal CLK1 ) Level.

When the DC type shift register 400 is not the first register to be started, the drive signal Q [n-1] of the immediately preceding shift register of the charger unit 410 and the first clock signal CLK1, (Q [n]) to the gate high voltage level (VGH).

Here, n is a natural number equal to or greater than 1 and equal to or less than N, the direct current type shift register 400 is the nth register, and the total number of shift registers is N.

According to the embodiment, the charging unit 410 includes a first switching TFT T1, a fourth switching TFT T4, a fifth switching TFT T5, a sixth switching TFT 6, an eighth switching TFT T8, And a bootstrap capacitor C1.

For example, the charging unit 410 is turned on when the first switching TFT T1, the fourth switching TFT T4, the fifth switching TFT T5, the sixth switching TFT 6, and the eighth switching TFT T8 are turned on to turn on the first node to the gate high voltage (VGH) level. At this time, the third switching TFT T3, the seventh switching TFT T7, and the ninth switching TFT T9 are turned off.

More specifically, the charging unit 410 turns on the first switching TFT Tl to turn on the start signal or the drive signal Q [n-1] of the previous-stage shift register and the first clock signal CLK1 to the first node (Q [n]), the third switching TFT T3 is turned off to charge the first node Q [n] to the gate high voltage level VGH, and the charged first node Q [ n] turns on the bootstrap capacitor C1 between the first node Q [n] and the second node B [n] by turning on the gate high voltage level VGH and the fourth switching TFT T4 and the fifth switching TFT T5 are turned on to discharge the third node Qb [n] to the gate low voltage (VGL) level. At this time, the sixth switching TFT T6 may be turned on by the first node Q [n] charged in the second node B [n] to become the gate-low voltage (VGL) level.

In addition, the charging unit 410 turns off the seventh switching TFT T7 and the ninth switching TFT T9 by the discharged third node Qb [n], and the charged first node Q [n] ) a eighth charge the switching TFT (T8) is turned on the output signal (V _g [n]) by the output signal (V _g [n]) is a gate high voltage level (VGH) and the threshold of the eighth switching TFT And the voltage V _TH8 .

According to the embodiment, in the case of the AC type shift register, the output terminal of the DC type shift register 400 of the present invention is connected to the DC type power source while the output terminal of the DC type shift register is connected to the clock signal.

Therefore, the direct current type shift register 400 can reduce the power consumption due to the clock signal by connecting a DC voltage source of fixed voltage to the output terminal.

FIG. 6B is a diagram illustrating the operation of the circuit for the bootstrap section of FIG.

6B, the bootstrap unit 420 includes a first node Q (Q) charged to a gate high voltage (VGH) level by a second clock signal CLK2 having a predetermined delay than the first clock signal CLK1, [n]) to the gate high voltage (VGH) level or higher.

The selected delay is a time delay T _d (n) between the output signal V _g [n] output from the first node Q [n] and the drive signal V _g [n + 1] ) And may be the difference (T _d ) between the time of the first clock signal CLK1 and the time of the second clock signal CLK2.

According to the embodiment, the bootstrap portion 420 includes a fourth switching TFT T4, a fifth switching TFT T5, a sixth switching TFT T6, an eighth switching TFT T8, and a bootstrap capacitor C1. . ≪ / RTI >

For example, the bootstrap section 420 is turned on when the fourth switching TFT T4, the fifth switching TFT T5, the sixth switching TFT T6, and the eighth switching TFT T8 are turned on and the first node Q [n]) can be bootstrapped to charge the gate high voltage (VGH) level or higher. At this time, the first to third switching TFTs (T1 to T3), the seventh switching TFT (T7), and the ninth switching TFT (T9) are turned off since they are at the gate low voltage (VGL) level.

More specifically, the bootstrap portion 420 floats the charged first node Q [n] by turning off the first switching TFT Tl and the third switching TFT T3, 6 switching TFT T6 is turned on to supply the second clock signal CLK2 to the second node B [n] and the first node Q [n] floated by the bootstrap capacitor C1 And the eighth switching TFT T8 is turned on by the bootstrapped first node Q [n] to charge the output signal to the gate high voltage VGH, Level.

6C is a diagram illustrating the operation of the circuit for the charge hold period of FIG.

6C, the charge holding unit 430 outputs the output signal Vg [n] output from the first node Q [n] bootstrapped while the second clock signal CLK2 is supplied to the gate High voltage (VGH) level.

The operation of each of the switching TFTs T1 to T9 in the charge holding unit 430 may be the same as the operation of the switching TFTs T1 to T9 in the bootstrap unit 430. [

Therefore, the direct current type shift register 400 of the present invention is capable of outputting the output signal V _g [n] and the output signal V _g [n] immediately after the timing of the first clock signal CLK1 and the second clock signal CLK2, The driving signal V _g [n + 1]

6D is a diagram illustrating the operation of the circuit for the discharge interval of FIG.

Referring to Figure 6d, a discharge part 440 includes a first clock inverted signal (CLK1b) and second ping bootstrapping by the clock inverted signal (CLK2b) a first node (Q [n]) and the output signal (V _g [n]) to the gate-low voltage (VGL) level.

Here, the first clock inversion signal CLK1b is an inversion signal for the first clock signal CLK1, and the second clock inversion signal CLK2b is an inversion signal for the second clock signal CLK2.

According to the embodiment, the discharger 440 may include the second to fourth switching TFTs T2 to T4, the seventh switching TFT T7, and the ninth switching TFT T9.

For example, the discharging unit 440 may be configured such that the second to fourth switching TFTs T2 to T4, the seventh switching TFT T7, and the ninth switching TFT T9 are turned on and the first Node Q [n] and the output signal V _g [n] to the gate-low voltage (VGL) level. At this time, the first switching TFT (T1), the fifth switching TFT (T5), the sixth switching TFT (T6) and the eighth switching TFT (T8) are turned off.

More specifically, the discharger 440 turns on the second switching TFT T2 to supply the first clock inversion signal CLK1b and the second clock inversion signal CLK2b to the third switching TFT T3, The first node Q [n] discharged at the gate low voltage (VGL) level discharges the first node Q [n] to the gate low voltage (VGL) level when the third switching TFT T3 is turned on, The sixth switching TFT T6 and the eighth switching TFT T8 are turned off and the fourth switching TFT T4 is turned on to charge the third node Qb [n] The seventh switching TFT T7 and the ninth switching TFT T9 are turned on by the gate signal line Qb [n] and the second node B [n] and the output signal V _g [n] VGL) level.

FIG. 6E is a diagram illustrating a timing diagram for the four sections of FIG. 5. FIG.

Referring to FIG. 6E, the DC type shift register 400 may be classified into a Q-charging, a bootstrapping, a holding period, and a discharging interval (Q-discharging) .

The DC type shift register 400 of the present invention is configured such that the output signal V _g [n] and the output signal V _g [n] are output at the timing immediately after the first clock signal CLK1 and the second clock signal CLK2, The overlapping time between the driving signals V _g [n + 1] of the shift register can be adjusted.

7 is a block diagram showing a DC type driving apparatus according to an embodiment of the present invention.

Referring to FIG. 7, the DC type driver 700 includes N shift registers in which a portion of the drive signals for neighboring shift registers overlap.

The nth shift register (n is a natural number equal to or greater than 1) in the N shift registers includes a charging unit 710n, a bootstrap unit 720n, a charge holding unit 730n, and a discharger 740n. Here, the charging unit 710n, the bootstrap unit 720n, the charge holding unit 730n, and the discharge unit 740n of the nth shift register 700n can operate using a plurality of switching TFTs and bootstrap capacitors .

More specifically, the nth shift register 700n may selectively supply the gate high voltage and the gate low voltage using the first to ninth switching TFTs including the low-temperature polycrystalline silicon and the bootstrap capacitor. have.

The n-th shift register 700n can operate the first to ninth switching TFTs and the bootstrap capacitor by four clock signals and two DC-type power supplies. The n-th shift register 700n has four operation periods (charge period, A charge storage section, a discharge section, etc.).

Here, the operation of each component of the nth shift register 700n will be described with reference to FIGS. 4 and 5 described above.

8 is a block diagram illustrating a direct current type driving apparatus according to another embodiment of the present invention.

8, the direct current type driving apparatus 800 includes a plurality of shift registers 810-1, 810-2, ..., 810-N, a power supply unit 820, and a clock generating unit 830. [

The plurality of shift registers 810-1, 810-2, ..., and 810-N may use a plurality of switching TFTs including low-temperature polycrystalline silicon.

More specifically, each of the shift registers 810-1, 810-2, ..., and 810-N uses the first to ninth switching TFTs including the low-temperature polycrystalline silicon and the bootstrap capacitor, (Charge section, bootstrap section, charge maintenance section, discharge section, etc.).

Here, the four operation periods of the shift registers 810-1, 810-2, ..., and 810-N will be described with reference to FIGS. 4 and 5, respectively.

The power supply unit 820 supplies a DC type power source to each of the shift registers 810-1, 810-2, ..., 810-N including a predetermined number of switching TFTs and bootstrap capacitors taking into consideration the characteristics of the low temperature polycrystalline silicon Supply.

The clock generating unit 830 generates a clock signal for performing at least one of charging, bootstrapping, charge holding, and discharging in each shift register.

The clock generator 830 may include a first clock generator, a second clock generator, a first inverted clock generator, and a second inverted clock generator.

The first clock generator may generate a first clock signal for charging the first node to the gate high voltage level in each shift register.

The second clock generator may generate a second clock signal having a predetermined delay over the first clock signal for bootstrapping the first node charged to the gate high voltage level above the gate high voltage level.

The predetermined delay may be a time overlapping between the output signal output from the first node and the driving signal of the immediately-after shift register immediately after the first clock signal, and may be a difference between the time of the first clock signal and the second clock signal time.

The first inverted clock generator may generate a first clock inverted signal, which is an inverted signal of the first clock signal, and the second inverted clock generator may generate a second clock inverted signal, which is an inverted signal of the second clock signal.

The driving apparatus 800 according to another embodiment of the present invention may further include a controller 840 for controlling the DC type power supply and the generated clock signal to be provided to the plurality of shift registers.

The control unit 840 controls the shift register 810 to overlap the driving signals for the neighboring shift registers by a predetermined delay and controls the shift registers 810-1, 810-2, ..., and 810- The first node bootstrapped based on the inverted signal and the second clock inversion signal, and the drive signal to be discharged to the gate low voltage level.

More specifically, the control unit 840 may control the overlap time of the driving signals for the adjacent shift registers to overlap each other to increase the output time by the predetermined delay.

9A is a diagram illustrating a circuit for a direct current type driving apparatus including the sixteen shift registers of FIG.

Referring to FIG. 9A, the DC type driving device 800 can supply DC type power to each shift register including a predetermined number of switching TFTs and bootstrap capacitors considering the characteristics of the low-temperature polycrystalline silicon.

Each shift register may include nine switching TFTs (T1 to T9) and one bootstrap capacitor, and the channel widths of the nine switching TFTs (T1 to T9) may be shown in Table 1.

[Table 1]

Referring to Table 1, the channel widths of the first to third switching TFTs (T1 to T3), the sixth switching TFT (T6) and the seventh switching TFT (T7) may be 20 us. The channel width of the fourth switching TFT T4 may be 10us and the channel width of the fifth switching TFT T5 may be 100us. The channel width of the eighth switching TFT T8 and the ninth switching TFT 9 The channel width may be 1000us.

The channel width of the switching TFT can be variously set according to the embodiment, but is not limited thereto.

The DC type driver 800 may generate a clock signal for performing at least one of charging, bootstrapping, overlapping, and discharging in each shift register.

Here, the clock signal may be a first clock signal (CLK1), a second clock signal (CLK2), a first clock inversion signal (CLK1b) and a second clock inversion signal (CLK2b) 4 and 5, respectively.

FIG. 9B is a diagram illustrating an output waveform of the tenth shift register in the DC type driving apparatus of FIG. 8; FIG.

Each shift register may overlap between the output signal output at the first node bootstrapped by the predetermined delay that is the difference between the time of the first clock signal and the time of the second clock signal and the drive signal of the immediately- .

For example, the tenth shift register may be configured to receive a bootstrap by a predetermined delay that is the difference (T _d = 2us) between the time of the first clock signal CLK1 and the time of the second clock signal CLK2, The output signal V _g [10] output from the first node Q [10] that is strapped can be overlapped with the drive signal V _g [11] of the 11th shift register.

9B, the following experimental values (threshold voltage, mobility, bootstrap capacitance, channel length of TFT, channel width of TFT, line time and frame time) can be applied and variously applied , But is not limited thereto.

The threshold voltage was 1.94 V, the mobility was 37.907 cm ² , the bootstrap capacitance was 0.16 fF / um, the channel length of the TFT was 5.5 us, the line time was 8 us, the frame time was 8 ms, and the channel width of the TFT was Table 1 described above can be applied.

Referring to FIG. 8 again, the DC type driver 800 may reduce the power consumption due to the clock signal by connecting a DC voltage source having a fixed voltage to the output terminal. Hereinafter, power consumption between the DC type driving apparatus 800 and the AC type driving apparatus of the present invention will be described with reference to Table 2. [

Table 2 shows an example of power consumption comparison between a DC type driving device including 50 shift registers and an AC type driving device including 50 shift registers.

Referring to Table 2, it can be seen that the DC type driving device 800 of the present invention consumes less power than the AC type driving device. Particularly, it can be seen that the DC type driving device 800 consumes less power of the clock signal than the AC type driving device.

10 is a flowchart illustrating an operation method of a direct current type shift register according to an embodiment of the present invention.

Referring to FIG. 10, in step 1010, the DC type shift register charges the first node to the gate high voltage level by the start signal or the driving signal of the first-stage shift register and the first clock signal.

More specifically, in step 1010, the DC type shift register supplies the start signal or the drive signal of the first-stage shift register and the first clock signal to the first node, and the third switching TFT turns on Off to charge the first node to the gate high voltage level and the sixth switching TFT is turned on by the charged first node to charge the bootstrap capacitor present between the first node and the second node to the gate high voltage level , The fourth switching TFT and the fifth switching TFT may be turned on to discharge the third node to the gate low voltage level. At this time, the sixth node may be turned on by the first node charged to the gate-low voltage level.

Further, in the DC type shift register, the seventh switching TFT and the ninth switching TFT are turned off by the discharged third node in Step 1010, and the eighth switching TFT is turned on by the charged first node to charge the output signal , But the output signal can be charged by the difference between the gate high voltage level and the threshold voltage of the eighth switching TFT.

The DC type shift register bootstrapped the first node charged to the gate high voltage level by the second clock signal having a predetermined delay than the first clock signal at the gate high voltage level or higher in step 1020.

More specifically, in step 1020, the DC type shift register floats the first node charged by turning off the first switching TFT and the third switching TFT, turns on the sixth switching TFT to turn on the second clock signal to the second And bootstrapping the first node floated by the bootstrap capacitor to charge the node to a level above the gate high voltage level, and the eighth switching TFT is turned on by the bootstrapped first node, Voltage level.

The predetermined delay may be a time overlapping between the output signal output from the first node and the driving signal of the immediately-after shift register immediately after the first clock signal, and may be a difference between the time of the first clock signal and the second clock signal time.

The DC type shift register maintains the output signal output at the first node bootstrapped at the gate high voltage level during the supply of the second clock signal in step 1030.

The DC type shift register discharges the first node bootstrapped by the first clock inversion signal and the second clock inversion signal and the output signal to the gate low voltage level in step 1040.

Here, the first clock inversion signal is an inversion signal for the first clock signal, and the second clock inversion signal is an inversion signal for the second clock signal.

According to the embodiment, in step 1040, the DC type shift register supplies the first clocked inverted signal and the second clocked inverted signal to the third switching TFT by turning on the second switching TFT, turning on the third switching TFT, Discharges the node to the gate low voltage level, the sixth switching TFT and the eighth switching TFT are turned off by the first node discharged at the gate low voltage level, the fourth switching TFT is turned on to charge the third node, The seventh switching TFT and the ninth switching TFT are turned on by the charged third node to discharge the second node and the output signal to the gate low voltage level.

11 is a flowchart illustrating an operation method of a DC type driving apparatus according to an embodiment of the present invention.

The direct current type driving apparatus includes N shift registers in which a part of the driving signals for the neighboring shift registers overlap.

11, an n-th shift register (n is a natural number equal to or greater than 1 and equal to or less than N) in the N shift registers is supplied with the start signal or the (n-1) Signal to charge the first node to the gate high voltage level.

The nth shift register, in step 1120, bootstrap the first node charged to the gate high voltage level by a second clock signal having a predetermined delay than the first clock signal, above the gate high voltage level.

The nth shift register maintains the nth drive signal output at the first node bootstrapped during the supply of the second clock signal at the gate high voltage level,

The nth shift register discharges the first node and the nth drive signal bootstrapped by the first clock inversion signal and the second clock inversion signal to a gate low voltage level in step 1140.

12 is a flowchart illustrating an operation method of a direct current type driving apparatus according to another embodiment of the present invention.

Referring to FIG. 12, in step 1210, the DC type driver supplies a DC type power source to each shift register including a predetermined number of switching TFTs and bootstrap capacitors taking into account the characteristics of the low temperature polycrystalline silicon.

In step 1220, the DC type driver generates a clock signal for performing at least one of charging, bootstrapping, charge holding, and discharging in each shift register.

Wherein the clock signal comprises a first clock signal for charging a first node to a gate high voltage level in each shift register, a first clock signal for charging a first node charged to a gate high voltage level to a first high- A second clock signal having a predetermined delay than the clock signal, a first clock inversion signal that is an inverted signal of the first clock signal, and a second clock inversion signal that is an inverted signal of the second clock signal.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

400: DC type shift regulator
410:
420: Bootstrap part
430: Charge holding section
440:

Claims (14)

A charging unit charging the first node to a gate high voltage (VGH) level by a start signal or a driving signal of the first stage shift register and a first clock signal;
A bootstrap portion bootstrapping a first node charged to the gate high voltage level by a second clock signal having a predetermined delay than the first clock signal to the gate high voltage level or higher;
A charge holding unit for holding an output signal output from the bootstrapped first node at the gate high voltage level while the second clock signal is supplied; And
A first node that is bootstrapped by a first clock inversion signal and a second clock inversion signal and a discharge node that discharges the output signal to a gate low voltage (VGL)
A DC type shift register. The method according to claim 1,
Characterized in that the gate high voltage and the gate low voltage are selectively supplied using first to ninth switching TFTs (thin film transistors) including low temperature polycrystalline silicon (LTPS) and bootstrap capacitors DC type shift register. 3. The method of claim 2,
The charging unit
Wherein the first switching TFT is turned on to supply the start signal or the driving signal of the direct previous shift register and the first clock signal to the first node,
The third switching TFT is turned off to charge the first node to the gate high voltage level,
The sixth switching TFT is turned on by the charged first node to charge the bootstrap capacitor existing between the first node and the second node to the gate high voltage level,
The fourth switching TFT and the fifth switching TFT are turned on to discharge the third node to the gate low voltage level,
The seventh switching TFT and the ninth switching TFT are turned off by the discharged third node,
The eighth switching TFT is turned on by the charged first node to charge the output signal,
The output signal is charged by a difference between the gate high voltage level and the threshold voltage of the eighth switching TFT
DC type shift register. 3. The method of claim 2,
The boot strap portion
The first switching TFT and the third switching TFT are turned off to float the charged first node,
The sixth switching TFT is turned on to supply the second clock signal to the second node,
And bootstrapping the floating first node by the bootstrap capacitor to charge the gate high voltage level or higher,
The eighth switching TFT is turned on by the bootstrapped first node to charge the output signal to the gate high voltage level
DC type shift register. 3. The method of claim 2,
The discharge unit
The second switching TFT is turned on to supply the first clock inversion signal and the second clock inversion signal to the third switching TFT,
The third switching TFT is turned on to discharge the first node to the gate low voltage level,
The sixth switching TFT and the eighth switching TFT are turned off by a first node discharged to the gate low voltage level,
The fourth switching TFT is turned on to charge the third node,
The seventh switching TFT and the ninth switching TFT are turned on by the charged third node to discharge the second node and the output signal to the gate low voltage level
DC type shift register. In a direct current type driving apparatus in which a part of driving signals for neighboring shift registers overlap in N shift registers,
The nth shift register (where n is a natural number of 2 or more and N or less)
A charging unit charging the first node to a gate high voltage level by an n-1th driving signal and a first clock signal of an (n-1) th shift register;
A bootstrap portion bootstrapping a first node charged to the gate high voltage level by a second clock signal having a predetermined delay than the first clock signal to the gate high voltage level or higher;
A charge holding unit for holding an nth drive signal output from the bootstrapped first node at the gate high voltage level while the second clock signal is supplied; And
A first node which is bootstrapped by a first clock inversion signal and a second clock inversion signal and a discharging unit which discharges the nth driving signal to a gate low voltage level
Type drive unit. A direct current type driving apparatus in which a part of driving signals for adjacent shift registers overlap in a plurality of shift registers,
A plurality of shift registers;
A power supply unit for supplying the direct current type power to each shift register including a predetermined number of switching TFTs and bootstrap capacitors taking into account characteristics of the low temperature polycrystalline silicon; And
And a clock generating unit for generating a clock signal for performing at least one of charging, bootstrapping, charge holding, and discharging in each shift register,
The clock generator
A first clock generator for generating a first clock signal for charging the first node to a gate high voltage level in each shift register;
A second clock generator for generating a second clock signal having a predetermined delay than the first clock signal for bootstrapping a first node charged with the gate high voltage level to the gate high voltage level or higher;
A first inverted clock generator for generating a first clock inverted signal which is an inverted signal of the first clock signal; And
And a second inverted clock generating unit for generating a second clock inverted signal, which is an inverted signal of the second clock signal,
Type drive unit. 8. The method of claim 7,
A controller for controlling the DC type power supply and the generated clock signal to be provided to the plurality of shift registers,
Further comprising: delete 9. The method of claim 8,
The control unit
Controlling a portion of the driving signal for the neighboring shift register to overlap with each other by the predetermined delay,
And controlling the first bootstrapped node and the drive signal to be discharged to a gate low voltage level based on the first clock inversion signal and the second clock inversion signal in each shift register
DC type drive device. Charging a first node to a gate high voltage level by a start signal or a drive signal of a first stage shift register and a first clock signal;
Bootstrapping a first node charged to the gate high voltage level by a second clock signal having a predetermined delay to the gate high voltage level or higher than the first clock signal;
Maintaining an output signal from the first bootstrapped node at the gate high voltage level while the second clock signal is being supplied; And
Discharging the bootstrapped first node and the output signal to a gate low voltage level by a first clock inversion signal and a second clock inversion signal,
Wherein the DC-type shift register comprises: A method of operating a direct current type driver in which a portion of a drive signal for neighboring shift registers overlaps in N shift registers,
The operation method of the n-th shift register (where n is a natural number of 2 or more and N or less)
Charging the first node to a gate high voltage level by an n-1 < th > drive signal and an n-1 < th > shift register and a first clock signal;
Bootstrapping a first node charged to the gate high voltage level by a second clock signal having a predetermined delay to the gate high voltage level or higher than the first clock signal;
Maintaining an nth driving signal output from the first bootstrapped node at the gate high voltage level while the second clock signal is supplied; And
Discharging said bootstrapped first node and said nth drive signal to a gate low voltage level by a first clock inversion signal and a second clock inversion signal,
Type drive device. There is provided a method of operating a direct current type driving apparatus in which a part of driving signals for neighboring shift registers overlap in a plurality of shift registers,
Supplying power of the direct current type to each of the shift registers including a predetermined number of switching TFTs and bootstrap capacitors taking into account characteristics of the low temperature polycrystalline silicon; And
And generating a clock signal for performing at least one operation of charging, bootstrapping, charge holding, and discharging in each shift register,
The step of generating the clock signal
Generating a first clock signal to charge a first node to a gate high voltage level in each shift register;
Generating a second clock signal having a predetermined delay over the first clock signal for bootstrapping a first node charged to the gate high voltage level above the gate high voltage level;
Generating a first clock inversion signal that is an inverted version of the first clock signal; And
Generating a second clock inversion signal that is an inverted signal of the second clock signal
Type drive device. A computer-readable recording medium on which a program for carrying out the method according to any one of claims 11 to 13 is recorded.

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