TWI767740B - Circuit for gate drivers on arrays with dummy output signals - Google Patents

Abstract

The invention related to a circuit for gate drivers on arrays with dummy output signals, in which the final stage driving circuit of the gate drivers on arrays is further coupled to a plurality of last two stage output units of a last two stage driving circuit to receive a plurality of last two stage gate driving signals, and further coupled to at least one virtual circuit to receive at least one virtual signal, for controlling levels of An signals corresponding to the gate driving signals of the final stage driving circuit going up or going down. Thus, the error outputting and the VSTOP signals inputted to the final stage driving circuit are reduced.

Description

Gate driver circuit on array with virtual output

The present invention relates to a control circuit, in particular to a gate driving circuit on an array with reduced cut-off signal input.

Thin Film Transistor Liquid Crystal Displays (TFT-LCDs, Thin Film Transistor Liquid Crystal Displays) have become the mainstream of modern display technology products, especially used in mobile phones, which are light and easy to carry. Compared with polysilicon thin film transistors (Poly-Si TFT), displays made of amorphous silicon thin film transistors (a-Si TFT) can reduce production costs and can be fabricated on large-area glass substrates at low temperatures , increase the production rate.

With the concept of system-on-glass (SOG, System-on-Glass) being put forward one after another, many products have recently integrated the gate scan driver circuit (Gate driver or Scan driver) in the display driver circuit on the glass, that is, GOA (Gate-Driver-on-Array) circuit, GOA circuit has many advantages, in addition to reducing the area of the display frame to achieve a thin frame, it can also reduce the use of gate scan driver IC, reduce the cost of purchasing IC and avoid glass The problem of disconnection when it is attached to the IC is used to improve the product yield. At present, it has been widely used in small and medium-sized displays such as mobile phones and notebook computers, and even products using GOA circuits for large-scale displays have come out in recent years.

In response to changes in consumer usage habits, products are gradually evolving towards high reliability, wide-area operation, and narrow bezels. The traditional GOA circuit can be divided into a signal transmission part, an anti-noise part, and a gate pulse output part. The signal transmission part is used to transmit the input signal required for the internal operation of the GOA circuit, which is related to the signal transmission of the GOA circuit. The anti-noise part is the internal circuit of the GOA circuit to maintain the stability of the output signal, which is related to its reliability. The gate pulse output part is the output signal of the GOA circuit to the gate line. However, taking the single-stage eight-output GOA circuit as an example, the single-stage GOA circuit repeatedly generates the output signal eight times, and the signal transmission part and the anti-noise part occupy most of the area of the eight-output GOA circuit. If this can be reduced The layout area of the functional circuit can achieve the effect of narrow frame, but the GOA circuit of the last stage has the problem of erroneous output due to too many sharing cut-off signals.

Based on the above problems, the present invention provides a gate driver circuit on an array with virtual output, which simplifies the connection relationship of the gate driver circuit on the array and avoids the excessively long clearing time of the synthesized signal by the circuit design of the virtual circuit. Reduce the circuit area related to false output and cut-off signal.

The main purpose of the present invention is to provide an upper gate driving circuit with a dummy output, which is coupled to at least one dummy circuit through the last stage driving circuit, so as to simplify the last stage driving circuit and avoid excessively long clearing time of the synthesized signal, thereby reducing the The related circuit area of the wrong output and cut-off signal to the last-stage driver circuit.

The invention discloses an upper gate driving circuit with dummy output, which has a plurality of driving circuits, wherein a first-level driving circuit is coupled to an external integrated circuit, a second-level driving circuit and a third-level driving circuit A driving circuit, the plurality of driving circuits are respectively coupled from the second-level driving circuit to an upper-level driving circuit and a lower-level driving circuit to a penultimate third-level driving circuit, so as to respectively receive a plurality of upper-level gate driving signals and A plurality of next-level gate drive signals and next-next-level gate drive signals of the next-level gate drive circuit, these drive circuits up to the penultimate third stage are respectively based on these previous-level gate drive signals, these The next-level gate drive signal and the next-level gate drive signals are used to control the potential rise or potential drop of the composite signal corresponding to the gate drive signals; the last-level drive circuit of the drive circuits further is coupled to the penultimate-level driving circuit and coupled to at least one dummy circuit and the external integrated circuit to receive a plurality of penultimate-level gate driving signals, at least one dummy signal of the dummy circuit and the external integrated circuit A cut-off signal is used to control the potential rise or potential drop of the composite signal corresponding to a plurality of last-stage gate driving signals of the last-stage driving circuits of the driving circuits. At least one dummy circuit is coupled to the above-mentioned last-stage driving circuit, so as to reduce the related circuit area of the erroneous output and the cut-off signal.

In order to make your examiners have a further understanding and understanding of the features of the present invention and the effects achieved, I would like to assist with the examples and cooperation descriptions, and the descriptions are as follows:

In view of the fact that the conventional signal transmission occupies part of the area of the GOA circuit, if the circuit layout area related to the cut-off signal can be reduced, the narrow frame effect can be achieved. Accordingly, the present invention proposes an array gate with reduced cut-off signal input. A pole drive circuit is used to solve the circuit area problem caused by the prior art.

Below, the present invention will further describe the characteristics and the matched structure of the gate driver circuit on an array with virtual output:

First, please refer to the first A to the first F, which are a schematic diagram of a gate driving circuit, a schematic diagram of a first-stage driving circuit, a schematic diagram of a single-stage driving circuit, a schematic diagram of a final-stage driving circuit, and a schematic diagram of a virtual circuit according to an embodiment of the present invention . As shown in Fig. 1 A, the gate driving circuit 1 on the array with dummy output of the present invention includes a plurality of driving circuits 10-1 to 10-n and at least one dummy circuit DUMMY. In this embodiment, a dummy circuit is used. The circuit DUMMY is used as an example, and the number can be adjusted according to the needs of use. Each driving circuit 10 is respectively coupled to a plurality of input signals. For example, the first-stage driving circuit 10-1 is coupled to an external integrated circuit (not shown) to receive a start signal VSTART and a plurality of clock signals CLK4 to CLK11 , and the first-level driving circuit 10-1 is coupled to the next-level driving circuit and the next-next-level driving circuit, that is, the second-level driving circuit 10-2 and the third-level driving circuit (not shown), and thus receive the first The gate driving signals G9 to G16 output by the second-stage driving circuit 10-2, the gate driving signal G17 output by the third-stage driving circuit, and the first-stage driving circuit 10-1 according to the start signal VSTART of the external integrated circuit The clock signals CLK4 to CLK11 sequentially control the potential rise of the composite signals AN1-AN8 corresponding to the plurality of gate driving signals G1-G8 of the first-stage driving circuit 10-1, and simultaneously through the second-stage driving circuit 10-1. The gate driving signals G10 to G16 output by the driving circuit 10-2 and the gate driving signal G17 output by the third-stage driving circuit pull down the potentials of the composite signals AN1-AN8 corresponding to the gate driving signals G1-G8.

Starting from the second-stage driving circuit 10-2, each stage of the driving circuit is coupled to the previous-stage driving circuit, the next-stage driving circuit and the next-next-stage driving circuit until the penultimate third-stage driving circuit (not shown), so the second-stage driving circuit The driving circuit 10-2 is coupled to the first-level driving circuit 10-1 and is coupled to the third-level driving circuit (not shown) and the fourth-level driving circuit (not shown), and thus receives the first-level driving circuit 10-1 The gate driving signals G1 to G8 are used to control the potential rise of the synthesized signals AN9 to AN16 corresponding to the gate driving signals G9 to G16 of the second-stage driving circuit 10-2, and receive the gate driving signals of the third-stage driving circuit G18 to G24 and the gate driving signal G25 of the fourth-stage driving circuit are used to control the potential pull-down of the synthesized signals AN9-AN16 corresponding to the gate driving signals G9-G16 of the second-stage driving circuit 10-2. Until the penultimate third-level driving circuit (not shown) is still coupled to the previous-level driving circuit, the next-level driving circuit and the next-next-level driving circuit, that is, the penultimate fourth-level driving circuit (not shown) and the penultimate driving circuit are coupled. The detailed coupling method of the second-stage driving circuit 10-n-1 and the last-stage driving circuit 10-n is the same as that of the second-stage driving circuit, and thus will not be repeated here. And, the penultimate level driving circuit 10-n-1 is coupled to the penultimate third level driving circuit and is coupled to the last level driving circuit 10-n and a dummy circuit DUMMY, so as to receive the gate of the penultimate third level driving circuit The driving signals GN-23 to GN-16 are used to control the potential rise of the synthesized potentials ANN-15 to ANN-8 corresponding to the gate driving signals GN-15 to GN-8 of the penultimate stage driving circuit 10-n-1, and receives the gate driving signals GN-6 to GN of the last stage driving circuit 10-n and a first dummy signal D1 provided by the dummy circuit DUMMY to control the gate of the penultimate stage driving circuit 10-n-1 The synthetic potentials ANN-15 to ANN-8 corresponding to the driving signals GN-15 to GN-8 are pulled down.

Referring back to FIG. 1A, the last stage driving circuit 10n of the present invention is coupled to the external integrated circuit and the dummy circuit DUMMY to receive a stop signal VSTOP of the external integrated circuit and a first level provided by the dummy circuit DUMMY. Two dummy signals D2, and the last stage driving circuit 10n is coupled to the penultimate stage driving circuit 10-n-1 to receive the gate driving signals GN-15 to GN-8 of the penultimate stage driving circuit 10-n-1 Therefore, the last stage driving circuit 10-n controls the synthesis signals ANN-7 to ANN corresponding to the gate driving signals GN-7 to GN of the last stage driving circuit 10-n according to the gate driving signals GN-15 to GN-8. The potential rises, and according to a second dummy signal D2 provided by the dummy circuit DUMMY, the synthesis signals ANN-7 to ANN-5 corresponding to the gate driving signals GN-7 to GN-5 of the last stage driving circuit 10-n are controlled. The potential is pulled down, and the potential pull-down of the synthesized signals ANN-4 to ANN corresponding to the gate driving signals GN-4 to GN is further controlled according to the cutoff signal VSTOP. In this embodiment, the gate drive is controlled by the cutoff signal VSTOP and the second dummy signal D2. The potentials of the composite signals ANN-7 to ANN corresponding to the signals GN-7 to GN are pulled down, and the composite signals ANN-7 to ANN- corresponding to the gate driving signals GN-7 to GN-5 can be directly controlled by the second virtual signal D2. The potential of 5 is pulled down, thus avoiding the potential pull-down of the gate drive signals GN-7 to GN-5 corresponding to the synthesized signals ANN-7 to ANN-5, which may lead to false output due to long waiting time, and the use of the common stop signal VSTOP saves external The circuit area of the input signal.

As shown in the first diagram A and the first diagram B, the first-stage driving circuit 10 - 1 includes a plurality of charging and discharging units 20 and a plurality of output units 30 . The first-stage driving circuit 10-1 is connected to the signal transmission part BUS to receive the start signal VSTART and a plurality of clock signals CLK4-CLK11 transmitted by the signal transmission part BUS. The signal transmission part BUS can further transmit the low frequency alternating current signal AC to The first-stage driving circuit 10-1 is used to control the pre-charging of the composite signals AN1 to AN8. Since the low-frequency alternating current signal AC controls the composite signals AN1 to AN8 in the prior art, it is not repeated here. The present embodiment takes 8 charging and discharging units 20 and 8 output units 30 as an example, but the present invention is not limited to 8, and the output unit 30 can be designed to have 2, 4, 16 or even 32 outputs according to the needs of use The unit 30, or shared by a plurality of output units 30, this embodiment is based on the current technology, the signal response is better, and the circuit is relatively simplified as an example, so in this embodiment, 8 charge and discharge units 20 and 8 are used as an example. The output unit 30 is illustrated by way of example.

Continuing from the above, since the first-stage driving circuit 10-1 does not have an upper-stage driving circuit, each charge-discharge unit 20 receives the start signal VSTART to generate the corresponding composite signals AN1-AN8, and each output unit 30 receives the start signal VSTART. That is, it receives the composite signals AN1~AN8 corresponding to the clock signals CLK4-CLK11 and the circuit, wherein the composite signals AN1~AN8 correspond to the clock signals CLK4-CLK11, so that the output units 30 are respectively connected to a plurality of output terminals GP1~GP8 generate gate driving signals G1~G8, that is, the potentials of the synthesized signals AN1~AN8 correspond to the potentials of the gate driving signals G1~G8 of the output terminals GP1~GP8, and the first stage driving circuit 10-1 is below the potential of the gate driving signals G1~G8. The first-level driving circuit is the second-level driving circuit 10-2, and the next-level driving circuit is the third-level driving circuit (not shown). Therefore, the first-level driving circuit 10-1 further receives the second-level driving circuit 10- 2. The gate driving signals G10 to G16 outputted and the gate driving signal G17 output by the third-stage driving circuit, that is, the charging and discharging units 20 receive the gate driving output by the second-stage driving circuit 10-2. The signals G10 to G16 and the gate drive signal G17 output by the third-stage drive circuit are used to pull down the potentials of the composite signals AN1~AN8 corresponding to the gate drive signals G1-G8, thereby allowing the composite signals to form a sequential potential rise with a potential pull-down.

Referring to the first A and the first C, the charging and discharging units 20 from the second-stage driving circuit 10-2 to the penultimate third-stage driving circuit are all coupled to a plurality of driving circuits in the previous stage The output unit of the previous stage and the plurality of output units of the next stage of the driving circuit of the next stage and the output cells of the next stage of the driving circuit of the next stage, therefore, as shown in the first C diagram, from the second stage driving circuit 10-2 to Each stage of the drive circuit 10 of the penultimate stage receives a plurality of gate drive signals G-8 of the previous stage (not shown) and the next-stage drive circuit and the next-stage drive circuit (not shown) The plurality of next-level gate driving signals G+9, for example: for the gate driving signal G9, G-8 is the G1 of the first-level driving circuit 10-1, and G+9 is the third-level driving circuit ( For the gate driving signal G16, G-8 is G8 of the first-stage driving circuit 10-1, and G+9 is the gate driving signal of the fourth-stage driving circuit (not shown). G25, instead of receiving the start signal VSTART or the stop signal VSTOP, the output unit 30 receives the composite signal AN generated by the charging and discharging unit 20, and the charging and discharging unit 20 receives the upper-level gate driving signal G-8 and the lower-level gate driving signal G+9 is used to generate the corresponding composite signal AN, and the potential of the composite signal AN corresponding to the gate driving signal G is raised by the gate driving signal G-8 of the previous stage, and the gate driving signal G of the next stage is used to increase the potential of the composite signal AN. +9 pulls down the potential of the composite signal AN corresponding to the gate driving signal G. Therefore, the output unit 30 can respectively generate the corresponding gate driving signal G at the signal output terminal GP according to the corresponding composite signal AN and the corresponding clock signal CLK. In this embodiment, a single-stage driving circuit 10 is provided with 8 output terminals GP and correspondingly outputs 8 gate driving signals G for illustration. The synthetic signal AN inside the driving circuit 10 corresponds to the clock signal CLK, so the gate The driving signal G corresponds to the timing of the clock signal CLK.

Please refer to the first diagram A and the first diagram D together, the penultimate stage driving circuit 10-n-1 of the present invention has a plurality of charging and discharging units 20 and a plurality of output units 30, and the charging and discharging units 20 are respectively coupled to The penultimate third stage driving circuit is connected to receive the corresponding gate driving signals GN-23 to GN-16. The charging and discharging unit 20 is further coupled to the last stage driving circuit 10n and the dummy circuit DUMMY, especially corresponding to the gate driving signals The charging and discharging unit 20 of GN-8 is coupled to the dummy circuit DUMMY, and thus receives the first dummy signal D1 of the dummy circuit DUMMY, and the remaining charging and discharging units 20 are coupled to the last-stage driving circuit 10-n to receive the last-stage driving circuit 10 -n gate drive signal GN-6 to GN. The charging and discharging unit 20 respectively generates corresponding composite signals ANN-15 to ANN-8 for the output unit 30 to generate according to the clock signals CLKN-15 to CLKN-8 and the corresponding composite signals ANN-15 to ANN-8 respectively The corresponding gate drive signals GN-15 to GN-8.

Referring to the first A and the first E together, the last stage driving circuit 10-n of the present invention is respectively coupled to the penultimate second stage driving circuit 10-n-1, the dummy circuit DUMMY and the external integrated circuit, so The charging and discharging unit 20 of the last-stage driving circuit 10-n receives the second dummy signal D2 and the gate driving signals GN-15 to GN-8 of the penultimate-stage driving circuit 10-n-1, and the last-stage driving circuit 10- n further receives the clock signals CLKN-7 to CLKN provided by the external integrated circuit transmitted by the signal transmission unit BUS, and further receives the low frequency AC signal AC, and the output unit 30 of the last stage driving circuit 10-n receives the clock signal CLKN-7 to CLKN and composite signals ANN-7 to ANN are used to output gate driving signals GN-7 to GN at corresponding output terminals GPN-7 to GPN, wherein these composite signals ANN to ANN are corresponding to clock signals CLKN-7 to CLKN.

Furthermore, in the present invention, the charging and discharging units 20 corresponding to the last-stage driving circuits 10-n are further coupled to the dummy circuit DUMMY and the cut-off signal VSTOP, so that some of the charging and discharging units 20 are coupled to the second dummy signal D2, and some of the charging and discharging units 20 are coupled to the second dummy signal D2. The charge-discharge unit 20 shares the stop signal VSTOP, and the potentials of the gate drive signals GN-7 to GN-5 corresponding to the output terminals GPN-7 to GPN-5 are controlled so that the charge-discharge unit 20 pulls down the synthesized signal ANN- according to the second virtual signal D2 The potential of 7 to ANN-5 makes the potential of the corresponding gate drive signals GN-7 to GN-5 pull down, and the potential of the gate drive signals GN-4 to GN of the corresponding output terminals GPN-4 to GPN is controlled to be charged. The discharge unit 20 pulls down the potentials of the synthesized signals ANN-4 to ANN according to the stop signal VSTOP, so as to pull down the potentials of the corresponding gate driving signals GN-4 to GN, for example: the present embodiment is the synthesized signals ANN-7 to ANN-5 The corresponding charge and discharge unit 20 is coupled to the second dummy signal D2, and the charge and discharge units 20 corresponding to the composite signals ANN-4 to ANN are coupled to the stop signal VSTOP to pull down the potential of the composite signals ANN-7 to ANN, so the last stage driving circuit 10-n can be directly controlled by the second virtual signal D2 to control the potential pull-down of the synthesized signals ANN-7 to ANN-5 corresponding to the gate drive signals GN-7 to GN-5, thus avoiding the gate drive signals GN-7 to GN The potential pull-down time of the composite signals ANN-7 to ANN-5 corresponding to -5 is too long, and the potential pull-down function of the composite signals ANN-4 to ANN can be achieved by receiving a single cutoff signal VSTOP, thus avoiding the false output of the gate drive signal GN -7, while reducing the circuit area related to the input of the cut-off signal VSTOP to the last-stage driving circuit 10-n. In addition, the stop signal VSTOP supports the potential pull-down of the synthesized signal corresponding to at most 7 gate drive signals.

As shown in Figure 1 F, the dummy circuit DUMMY is similar to the driving circuit 10 , and the dummy circuit DUMMY includes a first charge and discharge unit 22 , a second charge and discharge unit 24 , a first dummy unit 32 and a second dummy unit 34 , the first charging and discharging unit 22 is respectively coupled to the first output unit 30 of the last-stage driving circuit 10-n (that is, the output unit 30 corresponding to the gate driving signal GN-7) to generate the combined signal AND1 and the first output unit 30 respectively. The two charge-discharge units 24 are coupled to a fourth output unit of the last-stage driving circuit 10-n (that is, the output unit 30 corresponding to the gate driving signal GN-4) to respectively generate the combined signal AND2, the first dummy unit 32 is an eighth charge/discharge unit (ie, the charge/discharge unit 20 corresponding to the composite signal ANN-8) coupled to the first charge/discharge unit 22 and the penultimate second-stage driving circuit 10-n-1, and receives the composite signal AND1 and the clock signal CLKN-7 to generate the first dummy signal D1 to the charge-discharge unit 20 corresponding to the composite signal ANN-8, the second dummy unit 34 is for coupling the second charge-discharge unit 24 and the last-stage driving circuit 10-n The first to third charge-discharge units (that is, the charge-discharge unit 20 corresponding to the composite signals ANN-7, ANN-6 and ANN-5) receive the composite signal AND2 and the clock signal CLK-4 to generate the second The dummy signal D2 is sent to the charge-discharge unit 20 corresponding to the composite signals ANN-7, ANN-6 and ANN-5.

However, the dummy circuit DUMMY is not used for driving the display panel (not shown), but outputs the first dummy signal D1 and the second dummy signal D2 to the penultimate level driving circuit 10-n-1 and the last level driving circuit 10- n. The first dummy signal D1 is only used to pull down the composite signal ANN-8 corresponding to the gate driving signal GN-8, and the second dummy signal D2 is only used to pull down the composite signal ANN-8 corresponding to the gate driving signals GN-7 to GN-5. The synthesized signals ANN-7~ANN-5 do not affect the display effect, that is, the first dummy signal D1 and the second dummy signal D2 are not output to the thin film transistors of the pixels of the display panel.

The control of the first dummy signal D1 output from the output terminal DP1 is that the first charge and discharge unit 22 controls the potential of the synthesized signal AND1 to rise according to the gate drive signal GN-7 of the last stage drive circuit 10-n, and the first dummy unit 32 According to the combined signal AND1 and the clock signal CLKN-6, the potential of the first dummy signal D1 of the first dummy unit 32 is driven to rise, and the corresponding first dummy signal D1 is generated to the penultimate level driving circuit 10-n- 1. It is used to control the charging and discharging unit 20 corresponding to the gate driving signal GN-8, so that the potential of the corresponding composite signal ANN-8 is pulled down, and the potential of the second virtual signal D2 output by the second dummy unit 34 is controlled to be the second The charge-discharge unit 24 controls the potential rise of the composite signal AND2 according to the gate driving signal GN-4 of the last stage driving circuit 10-n, and the second dummy unit 34 drives one of the second dummy units 34 according to the composite signal AND2. The potential of the dummy signal D2 rises to generate the corresponding second dummy signal D2 to the last-stage driving circuit 10-n for controlling the charging and discharging units 20 corresponding to the gate driving signals GN-7, GN-6, GN-5, so that the corresponding The synthesized signals ANN-7~ANN-5 are pulled down.

The first dummy unit 32 and the second dummy unit 34 control the potential pull-down of the synthetic signals AND1 and AND2 corresponding to the first dummy signal D1 and the second dummy signal D2 according to the stop signal VSTOP, so as to drive the first dummy signal D1 and the second dummy signal D2 , The potentials of the first and second dummy signals D1 and D2 of the second dummy units 32 and 34 are pulled down.

Therefore, the present invention uses the first dummy signal D1 and the second dummy signal D2 output by the dummy circuit DUMMY to pull down the synthesized signals ANN-8~ANN-5 corresponding to the gate driving signals GN-8 to GN-5, thereby avoiding sharing the cutoff signal VSTOP. Too much will cause the potential pull-down time of the composite signals ANN-8~ANN-5 corresponding to the gate driving signals GN-8 to GN-5 to be too long, and the single stop signal VSTOP can support the entire last stage driving circuit 10-n. The potentials of the composite signals ANN-4-ANN corresponding to some of the gate driving signals GN-4 to GN are pulled down, thereby reducing false output and reducing the circuit area related to the input of the cut-off signal VSTOP to the last-stage driving circuit 10-n. In addition, the dummy circuit DUMMY can further adjust the corresponding number of dummy signals according to the number of output terminals of the last-stage driving circuit 10-n, so that the last-stage driving circuit 10-n can pull down regardless of the number of output signals.

Please refer to the second figure A, which is a waveform diagram of the synthesized signal corresponding to the output gate driving signal of the unused virtual circuit. As shown in the figure, the composite signal corresponding to the gate driving signal output by the last stage driving circuit is all coupled to a single cut-off signal (not shown), for example: the composite signal corresponding to the gate driving signal GN-8 waits for a potential pull-down Therefore, in the signal end area C of the synthetic signal ANN-8 corresponding to the gate driving signal GN-8, there will be additional warpage, thus causing the corresponding gate driving signal GN-8 to be output incorrectly, and the gate driving The pixel controlled by the signal GN-8 does not normally output the display signal. As shown in the second B picture, for the first dummy unit 32 or the second dummy unit 34, the synthetic signal AND and the dummy signal D are corresponding Signal, the first dummy unit 32 or the second dummy unit 34 share the cut-off signal VSTOP. If the first dummy unit 32 will cause a false output due to the long waiting time of the node of the synthetic signal AND, it will form an error before the cut-off signal VSTOP. The normally warped signal waveform will form noise noise, and will cause the virtual signal D to be output incorrectly. For example, the first virtual signal D1 will be incorrectly output, which will cause the corresponding gate driving signal GN-8 to be incorrectly output.

Referring to the third diagram A, it is a waveform diagram of the synthesized signal corresponding to the output gate driving signal of the present invention. As shown in the figure, the present invention utilizes the synthetic signals AND1 and AND2 corresponding to the first dummy signal D1 and the second dummy signal D2 of the dummy circuit DUMMY, so that the signal waveform has a boundary in the end region C, that is, as shown in Figure 3A The signal end region C of the second dummy signal D2 is vertically pulled down by the cut-off signal VSTOP. As shown in Figure 3 B, due to the boundary of the signal, the noise is reduced and the turn-on timing of the cut-off signal VSTOP is adjusted forward by a time zone The segment GAP, that is, the synthetic signal AND2 corresponding to the second virtual signal D2, is close to the cut-off signal VSTOP in timing, and does not warp abnormally as shown in the second picture B, thus avoiding the gate drive signals GN-7 to GN- 5. The corresponding control pixel does not normally output the display signal, thereby improving the reliability of wide temperature operation.

To sum up, the gate driving circuit on the array with dummy output of the present invention is coupled to the penultimate level driving circuit and the last level driving circuit through the dummy circuit, so that the penultimate level driving circuit and the last level driving circuit The circuit uses the virtual signal provided by the virtual circuit to control the potential pull-down of the composite signal corresponding to the gate driving signal and the corresponding timing of the cut-off signal, thus avoiding the potential pull-down of the composite signal corresponding to the gate driving signal due to the excessive sharing of the cut-off signal VSTOP. The waiting time is too long to reduce false output, and by sharing the cut-off signal, the related circuit area of the input cut-off signal to the last-stage driving circuit is further reduced.

Therefore, the present invention is indeed novel, progressive and available for industrial use, and it should meet the requirements of patent application in my country's patent law.

However, the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention. All changes and modifications made in accordance with the shape, structure, features and spirit described in the scope of the patent application of the present invention are equivalent. , shall be included in the scope of the patent application of the present invention.

1: Gate driver circuit on the array

10-1---10-n: drive circuit

10: Drive circuit

20: Charge and discharge unit

22: The first charge and discharge unit

24: The second charge and discharge unit

30: Output unit

32: First virtual unit

34: Second virtual unit

AC: low frequency alternating current signal

AN: composite signal

AN1~ANN: composite signal

AND: synthetic signal

AND1: The first composite signal

AND2: The second composite signal

AC: low frequency alternating current signal

BUS: Signal transmission part

D1: The first virtual signal

D2: Second virtual signal

DP1: output terminal

DP2: output terminal

DUMMY: virtual circuit

CLK4~CLKN: Clock signal

G1~GN: Gate drive signal

BUS: Signal transmission part

GAP: time period

GP: output terminal

GP0: output terminal

GP1: output terminal

GP2: output terminal

GP3: output terminal

GP4: output terminal

GP5: output terminal

GP6: output terminal

GP7: output terminal

GPN-7: Output

GPN-6: Output

GPN-6: Output

GPN-5: Output

GPN-4: Output

GPN-3: Output

GPN-2: Output

GPN-1: Output

GPN: output

NOISE: noise

VSTART: start signal

VSTOP: Stop signal

Figure 1 A: It is a schematic diagram of an upper gate driving circuit of an array according to an embodiment of the present invention; Figure 1 B: it is a schematic diagram of a first-stage driving circuit according to an embodiment of the present invention; The first figure C: it is a schematic diagram of a single-stage driving circuit according to an embodiment of the present invention; The first D figure: it is a schematic diagram of the penultimate stage driving circuit according to an embodiment of the present invention; The first E figure: it is a schematic diagram of the last stage driving circuit according to an embodiment of the present invention; Figure F: It is a schematic diagram of a virtual circuit according to an embodiment of the present invention; The second picture A: it is the waveform diagram of the output gate driving signal without dummy signal; The second picture B: it is the waveform diagram of the unbounded synthetic signal and the virtual signal to the cut-off signal; Figure 3 A: it is a waveform diagram of the output gate driving signal of the present invention; and Figure 3 B: It is a waveform diagram of the synthetic signal and the virtual signal paired with the cut-off signal of the present invention.

1: Gate drive circuit

10-1---10-n: drive circuit

AN1---ANN: synthetic signal

AND1: synthetic signal

AND2: synthetic signal

D1: The first virtual signal

D2: Second virtual signal

DUMMY: virtual circuit

G1---GN: gate drive signal

VSTART: start signal

VSTOP: Stop signal

CLK4---CLKN: Clock signal

Claims (6)

A gate driving circuit on an array with dummy output, comprising: a plurality of driving circuits, wherein a first-level driving circuit of the driving circuits is coupled to an external integrated circuit, a second-level driving circuit and a first-level driving circuit Three-stage driving circuit; the plurality of driving circuits are respectively coupled to an upper-stage driving circuit and a lower-stage driving circuit from the second-stage driving circuit to a third-to-last driving circuit; one of the driving circuits is an inverse The second-level driving circuit is coupled to the penultimate third-level driving circuit and is coupled to a last-level driving circuit and a dummy circuit; the last-level driving circuit of the plurality of driving circuits is coupled to the penultimate-level driving circuit and is coupled to the dummy circuit and the external integrated circuit; wherein the first-stage driving circuit controls the potential rise of a plurality of composite signals corresponding to a plurality of first gate driving signals according to a start signal of the external integrated circuit, and according to A plurality of second gate driving signals of the second-stage driving circuit and a third gate driving signal of the third-stage driving circuit control the potentials of the composite signals corresponding to the first gate driving signals Pull down; the driving circuits from the second-stage driving circuit until the penultimate third-stage driving circuit are based on a plurality of upper-stage gate driving signals of the upper-stage driving circuit and a plurality of next-stage gates of the lower-stage driving circuit The gate driving signal and the next-level gate driving signal are used to control the driving circuits from the second-level driving circuit to the third-to-last driving circuit. The potential is pulled down; the penultimate second-stage driving circuit is based on a plurality of penultimate third gate driving signals of the penultimate third-stage driving circuit, a plurality of last-stage gate driving signals of the last-stage driving circuit and a first gate driving signal of the virtual circuit. A dummy signal controls the potential rise or potential drop of a plurality of composite signals corresponding to a plurality of second-to-last gate driving signals; the last-stage driving circuit is based on the last-to-last gates of the second-to-last-stage driving circuit a driving signal, a second virtual signal of the virtual circuit and a cutoff signal of the external integrated circuit signal, and control the potential rise or potential pull-down of a plurality of composite signals corresponding to the last-stage gate drive signals of the last-stage drive circuit, and the vertical pull-down of the signal end region of the second virtual signal makes one of the cut-off signals conduct Move forward in time. The on-array gate driver circuit as claimed in claim 1, wherein the driver circuits respectively comprise a plurality of charge-discharge units and a plurality of output units, from the second-level driver circuit to the third-to-last driver circuit. The charging and discharging units are coupled to a plurality of upper-level output units of the upper-level driving circuit and are coupled to a plurality of lower-level output units and a next-lower-level output unit of the lower-level driving circuit, so as to generate the corresponding synthetic signals to the corresponding output units, so as to further generate the gate driving signals according to the corresponding clock signals. The on-array gate driving circuit according to claim 1, wherein the driving circuits are further coupled to a plurality of clock signals and a plurality of low-frequency AC signals, respectively. The gate driver circuit on the array as claimed in claim 1, wherein the dummy circuit comprises: a first charge-discharge unit coupled to a first output unit of the last-stage driver circuit and the cut-off signal to generate a first composite signal; a first dummy unit, coupled to the first charge and discharge unit, to generate the first dummy signal; a second charge and discharge unit, coupled to a fourth output unit of the last-stage driving circuit and the cut-off signal, to generate a second composite signal; and a second dummy unit coupled to the second charge-discharge unit to generate the second dummy signal; wherein the first charge-discharge unit corresponds to the first output unit of the last-stage driving circuit The last stage gate driving signal controls the potential of the first composite signal to rise to drive the potential of the first dummy signal to rise, and the second charge and discharge unit is based on the last stage of the fourth output unit of the last stage driving circuit. The first-level gate drive signal controls the potential of the corresponding second composite signal to rise, so as to drive the potential of the second dummy signal to rise. The first dummy unit and the second dummy unit control the first dummy signal and the second dummy unit according to the cut-off signal. The first composite signal and the second composite signal corresponding to the second virtual signal The potential of the signal is pulled down to drive the potential of the first and second dummy signals of the first and second dummy units to be pulled down. The gate driving circuit on the array according to claim 4, wherein the last stage driving circuit controls the potential pull-down of the composite signal corresponding to the last stage gate driving signals according to the second dummy signal and the cutoff signal. The gate driving circuit on the array as claimed in claim 1, wherein the cut-off signal supports a pull-down potential of a composite signal corresponding to a maximum of seven gate driving signals.

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