TWM618569U - Circuit for gate drivers on arrays with dummy output signals - Google Patents

Abstract

The utility model is related to a circuit for gate drivers on arrays with dummy output signals, in which the final stage driving circuit of the gate drivers on arrays is further coupled to a plurality of last two stage output units of a last two stage driving circuit to receive a plurality of last two stage gate driving signals, and further coupled to at least one virtual circuit to receive at least one virtual signal, for controlling levels of An signals corresponding to the gate driving signals of the final stage driving circuit going up or going down. Thus, the error outputting and the VSTOP signals inputted to the final stage driving circuit are reduced.

Description

Gate driving circuit on array with virtual output

This creation is related to a control circuit, especially a gate drive circuit on the array with virtual output.

Thin Film Transistor Liquid Crystal Displays (TFT-LCDs, Thin Film Transistor Liquid Crystal Displays) have become the mainstream of modern display technology products, especially used in mobile phones, which are lightweight and easy to carry. Compared with Poly-Si TFT, the display made of amorphous silicon thin film transistor (a-Si TFT) can reduce production cost and can be fabricated on large-area glass substrate at low temperature. , Improve production rate.

As the concept of System-on-Glass (SOG, System-on-Glass) has been put forward one after another, recently many products integrate the gate driver or scan driver in the display driver circuit on the glass, which is GOA (Gate-Driver-on-Array) circuit. GOA circuit has many advantages. In addition to reducing the area of the display frame to achieve a thin frame, it can also reduce the use of gate scan driver ICs, reduce the cost of purchasing ICs, and avoid glass The problem of disconnection when bonding with IC is used to improve product yield. At present, it has been widely used in small and medium-sized displays such as mobile phones, notebook computers, etc., and even large-scale displays using GOA circuits have also come out in recent years.

In response to changes in consumer usage habits, products are gradually evolving toward high reliability, wide area operation, and narrow bezels. The traditional GOA circuit can be divided into a signal transmission part, an anti-noise part, and a gate pulse output part. The signal transmission part transmits the input signal required for the internal operation of the GOA circuit, which is related to the signal transmission of the GOA circuit. The anti-noise part is a circuit inside the GOA circuit that maintains the stability of the output signal, which is critical to its reliability. The gate pulse output part is the GOA circuit that outputs the signal to the gate line. However, take a single-stage eight-output GOA circuit as an example. The single-stage GOA circuit repeats the output signal eight times. The signal transmission part and the anti-noise part occupy most of the area of the eight-output GOA circuit. If this can be reduced The layout area of the functional circuit can achieve the effect of narrow frame, but the last-stage GOA circuit has too many cut-off signals, and the problem of wrong output occurs.

Based on the above-mentioned problems, the present invention provides a gate drive circuit on the array with virtual output, which simplifies the connection relationship of the gate drive circuit on the array and avoids too long time for the composite signal to be cleared by the circuit design of the virtual circuit. Reduce the circuit area related to false output and cut-off signals.

The main purpose of this creation is to provide a gate driver circuit on the array with virtual output, which is coupled to at least one virtual circuit by the last-stage driver circuit, so as to simplify the last-stage driver circuit and avoid the synthesis signal clearing time is too long, thereby reducing Error output and cut-off signal to the relevant circuit area of the last stage of the drive circuit.

This creation discloses a gate drive circuit on an array with virtual output, which has a plurality of drive circuits, including a first-level drive circuit, coupled to an external integrated circuit, a second-level drive circuit, and a third-level drive circuit A driving circuit, the driving circuits are respectively coupled to an upper-level driving circuit and a lower-level driving circuit from the second-level driving circuit to a penultimate third-level driving circuit to respectively receive a plurality of upper-level gate driving signals and The plurality of next-stage gate drive signals of the next-stage gate drive circuit and the next-stage gate-drive signals of the next-stage gate drive circuit. The next-stage gate drive signal and the next-stage gate drive signals are used to control the potential rise or fall of the composite signal corresponding to the gate drive signals; the last-stage drive circuit of the drive circuits further Coupled to the penultimate level driving circuit and coupled to at least one virtual circuit and the external integrated circuit to receive a plurality of penultimate level gate driving signals, at least one virtual signal of the virtual circuit, and the external integrated circuit One of the cut-off signals is used to control the potential rise or fall of the composite signal corresponding to the plurality of last-stage gate drive signals of the last-stage drive circuit of the drive circuits. The above-mentioned last-stage driving circuit is coupled to at least one dummy circuit, so as to reduce the relevant circuit area of false output and cut-off signal.

In order to enable your review committee to have a better understanding and understanding of the characteristics of this creation and the effects achieved, I would like to provide examples and supporting instructions. The explanation is as follows:

In view of the fact that the conventional signal transmission occupies part of the area of the GOA circuit, if the relevant circuit layout area of the cutoff signal can be reduced, the narrow frame effect can be achieved. Based on this, the author proposes a virtual output gate drive circuit on the array , In order to solve the circuit area problem caused by the conventional technology.

In the following, we will further explain the characteristics and structure of a gate drive circuit on an array with virtual output disclosed in this creation:

First of all, please refer to the first A to the first F, which are schematic diagrams of the gate drive circuit, the first-stage drive circuit, the single-stage drive circuit, the last-stage drive circuit, and the virtual circuit diagram of an embodiment of the creation. . As shown in Figure 1A, the gate driver circuit 1 on the array with virtual output of the present creation includes a plurality of driver circuits 10-1 to 10-n and at least one virtual circuit DUMMY. This embodiment uses a virtual The circuit DUMMY is taken as an example, and the quantity can be adjusted according to usage requirements. Each driving circuit 10 is respectively coupled to a plurality of input signals, for example: the first-level driving circuit 10-1 is coupled to an external integrated circuit (not shown) to receive a start signal VSTART and a plurality of clock signals CLK4 to CLK11 , And the first-level drive circuit 10-1 is coupled to the next-level drive circuit and the next-level drive circuit, that is, is coupled to the second-level drive circuit 10-2 and the third-level drive circuit (not shown), thus receiving the first The gate drive signals G9 to G16 output by the second-level drive circuit 10-2, the gate drive signals G17 output by the third-level drive circuit, and the first-level drive circuit 10-1 according to the start signal VSTART of the external integrated circuit In accordance with the clock signals CLK4 to CLK11, the potentials of the synthesized signals AN1-AN8 corresponding to the gate driving signals G1-G8 of the first-stage driving circuit 10-1 are controlled to rise in sequence, and at the same time, the second-stage The gate driving signals G10 to G16 output by the driving circuit 10-2 and the gate driving signal G17 output by the third-level driving circuit pull down the potentials of the composite signals AN1-AN8 corresponding to the gate driving signals G1-G8.

Starting from the second-level driving circuit 10-2, each level of driving circuit is coupled to the upper-level driving circuit, the next-level driving circuit, and the next-next-level driving circuit up to the penultimate third-level driving circuit (not shown), so the second-level The driving circuit 10-2 is coupled to the first-level driving circuit 10-1 and coupled to the third-level driving circuit (not shown) and the fourth-level driving circuit (not shown), thereby receiving the first-level driving circuit 10-1 The gate drive signals G1 to G8 of the second-level drive circuit 10-2 are used to control the potential rise of the synthesized signals AN9 to AN16 corresponding to the gate drive signals G9 to G16 of the second-level drive circuit 10-2, and receive the gate drive signals of the third-level drive circuit G18 to G24 and the gate drive signal G25 of the fourth-level drive circuit are used to control the potential pull-down of the synthesized signals AN9 to AN16 corresponding to the gate drive signals G9 to G16 of the second-level drive circuit 10-2. Until the penultimate third-level drive circuit (not shown) is still coupled to the upper-level drive circuit and the next-level drive circuit and the next-next-level drive circuit, that is, the penultimate fourth-level drive circuit (not shown) and the penultimate The detailed coupling method of the second-level driving circuit 10-n-1 and the last-level driving circuit 10-n is the same as that of the second-level driving circuit, so it will not be repeated. However, the penultimate level driving circuit 10-n-1 is coupled to the penultimate level driving circuit and coupled to the last level driving circuit 10-n and a dummy circuit DUMMY to receive the gate of the penultimate level driving circuit The driving signals GN-23 to GN-16 are used to control the potential rise of the synthesized potentials ANN-15 to ANN-8 corresponding to the gate driving signals GN-15 to GN-8 of the penultimate drive circuit 10-n-1, And receive the gate drive signals GN-6 to GN of the last-level drive circuit 10-n and a first virtual signal D1 provided by the virtual circuit DUMMY to control the gate of the penultimate drive circuit 10-n-1 The driving signals GN-15 to GN-8 correspond to the synthetic potentials ANN-15 to ANN-8 corresponding to the potential pull-down.

Referring back to Figure 1A, the last stage of the drive circuit 10n of this creation is to couple the external integrated circuit and the dummy circuit DUMMY to receive a cut-off signal VSTOP of the external integrated circuit and one of the first stages provided by the dummy circuit DUMMY. Two dummy signals D2, and the last-stage driving circuit 10n is coupled to the penultimate stage driving circuit 10-n-1 to receive the gate driving signals GN-15 to GN-8 of the penultimate stage driving circuit 10-n-1 , Therefore the last-stage drive circuit 10-n controls the synthesized signals ANN-7 to ANN corresponding to the gate drive signals GN-7 to GN of the last-stage drive circuit 10-n according to the gate drive signals GN-15 to GN-8 The potential rises, and according to a second virtual signal D2 provided by the virtual circuit DUMMY, the combined signals ANN-7 to ANN-5 corresponding to the gate drive signals GN-7 to GN-5 of the last-stage drive circuit 10-n are controlled The potential pull-down is further controlled according to the cut-off signal VSTOP and the potential pull-down of the synthesized signals ANN-4 to ANN corresponding to the gate drive signals GN-4 to GN. In this embodiment, the gate drive is controlled by the cut-off signal VSTOP and the second virtual signal D2 Signals GN-7 to GN correspond to the corresponding synthetic signals ANN-7 to ANN's potential pull-down, and the second virtual signal D2 can directly control the gate drive signals GN-7 to GN-5 corresponding to the synthetic signals ANN-7 to ANN- The potential pull-down of 5 prevents the composite signal ANN-7 to ANN-5 corresponding to the gate drive signals GN-7 to GN-5 from being pulled down for a long time and causing false output, and it saves external power by sharing the cut-off signal VSTOP The circuit area of the input signal.

As shown in the first A and the first B, the first-stage driving circuit 10-1 includes a plurality of charging and discharging units 20 and a plurality of output units 30. The first-level drive circuit 10-1 is connected to the signal transmission part BUS to receive the start signal VSTART and a plurality of clock signals CLK4-CLK11 transmitted by the signal transmission part BUS. The signal transmission part BUS can further transmit the low-frequency AC signal AC to The first-stage driving circuit 10-1 controls the pre-charging of the synthesized signals AN1 to AN8. Since the low-frequency AC signal AC controls the synthesized signals AN1 to AN8 as a conventional technology, it will not be repeated. Among them, this embodiment takes 8 charging and discharging units 20 and 8 output units 30 as examples, but this creation is not limited to 8, and the output unit 30 can be designed to have 2, 4, 16 or even 32 outputs according to the needs of use. Unit 30, or a plurality of output units 30 are shared, this embodiment is based on the current technology, the signal response is better, and a more simplified circuit as an example, so this embodiment uses 8 charging and discharging units 20 and 8 The output unit 30 is taken as an example.

Following the above, since the first-level driving circuit 10-1 does not have the upper-level driving circuit, each charging and discharging unit 20 receives the start signal VSTART to generate the corresponding composite signal AN1~AN8, and each output unit 30 That is, receiving the synthesized signals AN1~AN8 corresponding to the clock signal CLK4-CLK11 and the circuit, where the synthesized signals AN1~AN8 correspond to the clock signal CLK4-CLK11, so that the output units 30 are connected to a plurality of output terminals respectively. GP1~GP8 generate gate drive signals G1~G8, that is, the potentials of the synthesized signals AN1~AN8 correspond to the potentials of the gate drive signals G1~G8 of the output terminals GP1~GP8, and the first-level drive circuit 10-1 The first-level driving circuit is the second-level driving circuit 10-2, and the next-next-level driving circuit is the third-level driving circuit (not shown), so the first-level driving circuit 10-1 further receives the second-level driving circuit 10- 2 The output gate drive signals G10 to G16 and the gate drive signal G17 output by the third-level drive circuit, that is, the charge and discharge units 20 receive the gate drive output from the second-level drive circuit 10-2 The signals G10 to G16 and the gate drive signal G17 output by the third-level drive circuit are used to pull down the potentials of the composite signals AN1~AN8 corresponding to the gate drive signals G1-G8, so that the composite signals form a sequential potential rise Pull down with potential.

As shown in the first A and the first C, the charging and discharging units 20 from the second-level driving circuit 10-2 to the penultimate third-level driving circuit are all coupled to the plurality of driving circuits of the upper level A plurality of next-stage output units of the upper-level output unit and the next-stage drive circuit, and a plurality of next-stage output units of the next-next-stage drive circuit, so as shown in Figure 1C, from the second-level drive circuit 10-2 to Each drive circuit 10 of the third-to-last stage receives a plurality of previous gate drive signals G-8 from the previous drive circuit (not shown), the next drive circuit and the next next drive circuit (not shown) For the gate driving signal G9, G-8 is the G1 of the first-level driving circuit 10-1, and G+9 is the third-level driving circuit ( G18 of the gate drive signal G16; G-8 is G8 of the first-level drive circuit 10-1, and G+9 is the gate drive signal of the fourth-level drive circuit (not shown) G25, instead of receiving the start signal VSTART or the stop signal VSTOP, the output unit 30 receives the composite signal AN generated by the charging and discharging unit 20, and the charging and discharging unit 20 receives the upper-level gate drive signal G-8 and the lower-level gate drive signal G+9, to generate the corresponding composite signal AN, and increase the potential of the composite signal AN corresponding to the gate drive signal G by the upper-level gate drive signal G-8, and use the lower-level gate drive signal G +9 pulls down the potential of the synthesized signal AN corresponding to the gate drive signal G. Therefore, the output unit 30 can generate the corresponding gate drive signal G at the signal output terminal GP according to the corresponding synthesized signal AN and the corresponding clock signal CLK. In this embodiment, the single-stage driving circuit 10 is provided with 8 output terminals GP and correspondingly outputting 8 gate driving signals G. The synthetic signal AN inside the driving circuit 10 corresponds to the clock signal CLK, so the gate The driving signal G corresponds to the timing of the clock signal CLK.

Please refer to the first A and the first D, the penultimate drive circuit 10-n-1 of this creation, which has a plurality of charging and discharging units 20 and a plurality of output units 30, the charging and discharging units 20 are respectively coupled Connected to the penultimate third-level driving circuit to receive the corresponding gate driving signals GN-23 to GN-16, and the charging and discharging unit 20 is further coupled to the last-level driving circuit 10n and the dummy circuit DUMMY, especially corresponding to the gate driving signal The charging and discharging unit 20 of the GN-8 is coupled to the dummy circuit DUMMY and therefore receives the first dummy signal D1 of the dummy circuit DUMMY. The remaining charging and discharging units 20 are coupled to the last-stage driving circuit 10-n to receive the last-stage driving circuit 10 -n's gate drive signal GN-6 to GN. The charging and discharging unit 20 respectively generates corresponding synthesized signals ANN-15 to ANN-8 for the output unit 30 to generate according to the clock signals CLKN-15 to CLKN-8 and the corresponding synthesized signals ANN-15 to ANN-8, respectively Corresponding gate drive signals GN-15 to GN-8.

Referring to the first A and the first E, the last-stage driving circuit 10-n of this creation is respectively coupled to the penultimate-stage driving circuit 10-n-1 and the dummy circuit DUMMY and the external integrated circuit. The charging and discharging unit 20 of the last-stage driving circuit 10-n receives the second dummy signal D2 and the gate driving signals GN-15 to GN-8 of the penultimate second-stage driving circuit 10-n-1, and the last-stage driving circuit 10-n n It also receives the clock signals CLKN-7 to CLKN provided by the external integrated circuit transmitted by the signal transmission part BUS, and further receives the low-frequency AC signal AC, and the output unit 30 of the final drive circuit 10-n receives the clock signal CLKN-7 to CLKN and synthetic signals ANN-7~ANN to output gate drive signals GN-7 to GN corresponding to the output terminals GPN-7 to GPN, wherein the synthetic signals ANN~ANN correspond to clock signals CLKN-7 to CLKN.

Furthermore, the present invention further utilizes the charging and discharging unit 20 corresponding to the last-level driving circuit 10-n to be coupled to the dummy circuit DUMMY and the cut-off signal VSTOP, so that some of the charging and discharging units 20 are coupled to the second dummy signal D2, and some The charging and discharging unit 20 shares the cutoff signal VSTOP, and the potential of the gate drive signals GN-7 to GN-5 corresponding to the output terminals GPN-7 to GPN-5 is controlled as the charging and discharging unit 20 pulls down to synthesize the signal ANN- according to the second virtual signal D2 The potential of 7 to ANN-5 pulls down the potential of the corresponding gate drive signal GN-7 to GN-5, and the potential of the gate drive signal GN-4 to GN corresponding to the output terminal GPN-4 to GPN is controlled to charge The discharge unit 20 pulls down the potentials of the synthesized signals ANN-4 to ANN according to the cut-off signal VSTOP, so that the corresponding gate drive signals GN-4 to GN are pulled down. For example, in this embodiment, the synthesized signals ANN-7 to ANN-5 are pulled down. The corresponding charging and discharging unit 20 is coupled to the second dummy signal D2, and the composite signal ANN-4 to ANN corresponding to the charging and discharging unit 20 is coupled to the cut-off signal VSTOP, and the potential of the composite signal ANN-7 to ANN is pulled down, so the final drive circuit 10-n can be directly controlled by the second virtual signal D2 to pull down the potential of the synthesized signals ANN-7 to ANN-5 corresponding to the gate drive signals GN-7 to GN-5, thus avoiding the gate drive signals GN-7 to GN -5 The corresponding synthetic signal ANN-7 to ANN-5 potential pull-down waiting time is too long, and receiving a single cut-off signal VSTOP can achieve the potential pull-down function of the synthetic signal ANN-4 to ANN, thus avoiding false output of the gate drive signal GN -7, while reducing the relevant circuit area of the cut-off signal VSTOP input to the last-stage drive circuit 10-n. In addition, the cut-off signal VSTOP supports the potential pull-down of the composite signal corresponding to up to 7 gate drive signals.

As shown in the first figure F, the dummy circuit DUMMY is similar to the driving circuit 10. The dummy circuit DUMMY includes a first charging and discharging unit 22, a second charging and discharging unit 24, a first dummy unit 32 and a second dummy unit 34 , The first charging and discharging unit 22 is respectively coupled to the first output unit 30 of the last-stage drive circuit 10-n (that is, the output unit 30 corresponding to the gate drive signal GN-7) to respectively generate the composite signal AND1, and the first output unit 30 The two charging and discharging units 24 are coupled to a fourth output unit of the last-stage drive circuit 10-n (that is, the output unit 30 corresponding to the gate drive signal GN-4) to respectively generate a composite signal AND2, the first dummy unit 32 is an eighth charging and discharging unit (that is, the charging and discharging unit 20 corresponding to the composite signal ANN-8) that couples the first charge and discharge unit 22 and the penultimate drive circuit 10-n-1, and receives the composite signal AND1 The charging and discharging unit 20 corresponding to the clock signal CLKN-7 to generate the first dummy signal D1 to the synthesized signal ANN-8. The second dummy unit 34 is coupled to the second charging and discharging unit 24 and the last-stage driving circuit 10-n The first to third charging and discharging units (that is, the charging and discharging units 20 corresponding to the composite signals ANN-7, ANN-6, and ANN-5), and receive the composite signal AND2 and the clock signal CLK-4 to generate the second The charging and discharging units 20 corresponding to the virtual signal D2 to the composite signals ANN-7, ANN-6, and ANN-5.

However, the dummy circuit DUMMY is not used to drive the display panel (not shown), but to output the first dummy signal D1 and the second dummy signal D2 to the penultimate stage driving circuit 10-n-1 and the last stage driving circuit 10-- n. The first virtual signal D1 is only used to pull down the composite signal ANN-8 corresponding to the gate drive signal GN-8, and the second virtual signal D2 is only used to pull down the one corresponding to the gate drive signals GN-7 to GN-5. The composite signals ANN-7~ANN-5 do not affect the display effect, that is, the first virtual signal D1 and the second virtual signal D2 are not output to the thin film transistors of the pixels of the display panel.

The control of the first dummy signal D1 output by the output terminal DP1 is that the first charging and discharging unit 22 controls the potential increase of the composite signal AND1 according to the gate driving signal GN-7 of the last-stage driving circuit 10-n, and the first dummy unit 32 According to the synthesized signal AND1 and the clock signal CLKN-6, the potential of the first dummy signal D1 of the first dummy unit 32 is driven to rise, and the corresponding first dummy signal D1 to the penultimate stage driving circuit 10-n- is generated. 1. It is used to control the charging and discharging unit 20 corresponding to the gate drive signal GN-8 to pull down the potential of the corresponding composite signal ANN-8, and the second virtual signal D2 output by the second virtual unit 34 is controlled to be the second The charging and discharging unit 24 controls the potential increase of the composite signal AND2 according to the gate drive signal GN-4 of the last-stage drive circuit 10-n, and the second dummy unit 34 drives one of the second dummy units 34 according to the composite signal AND2. The potential of the virtual signal D2 rises to generate the corresponding second virtual signal D2 to the last-stage drive circuit 10-n for controlling the charging and discharging units 20 corresponding to the gate drive signals GN-7, GN-6, and GN-5, so that the corresponding The combined signal ANN-7~ANN-5 has the potential to pull down.

The first dummy unit 32 and the second dummy unit 34 control the first dummy signal D1 and the second dummy signal D2 corresponding to the first dummy signal D1 and the second dummy signal D2 to pull down the potentials of the composite signals AND1 and AND2 according to the stop signal VSTOP, so as to drive the first dummy signal , The potentials of the first and second dummy signals D1 and D2 of the second dummy cells 32 and 34 are pulled down.

Therefore, in this creation, the first virtual signal D1 and the second virtual signal D2 output by the virtual circuit DUMMY are synthesized signals ANN-8~ANN-5 corresponding to the pull-down gate drive signals GN-8 to GN-5, thus avoiding sharing the cut-off signal VSTOP Too much leads to too long waiting time for the potential pull-down of the synthesized signals ANN-8~ANN-5 corresponding to the gate drive signals GN-8 to GN-5, and allows a single cut-off signal VSTOP to support the entire final drive circuit 10-n Part of the gate drive signals GN-4 to GN corresponding to the synthesized signals ANN-4~ANN are pulled down to reduce false output and reduce the relevant circuit area of the cut-off signal VSTOP input to the last-stage drive circuit 10-n. In addition, the dummy circuit DUMMY can also adjust the number of corresponding dummy signals according to the number of output terminals of the last-stage driving circuit 10-n, so that the last-stage driving circuit 10-n can be pulled down regardless of the amount of output signal.

To sum up, this creation has a virtual output gate drive circuit on the array, which is coupled to the penultimate level drive circuit and the last level drive circuit through the virtual circuit, so that the penultimate level drive circuit It corresponds to the timing of the potential pull-down and cut-off signal of the synthesized signal corresponding to the gate drive signal controlled by the virtual signal provided by the virtual circuit in the last stage of the drive circuit, so as to avoid sharing the cut-off signal VSTOP too much and cause the gate drive signal to correspond to The synthetic signal potential pull-down waiting time is too long to reduce false output, and by sharing the cut-off signal, the relevant circuit area from the input cut-off signal to the last-stage drive circuit is reduced.

Therefore, this creation is really novel, progressive, and available for industrial use. It should meet the patent application requirements of my country's patent law. Undoubtedly, I file a new patent application in accordance with the law. I pray that the Bureau will grant the patent as soon as possible.

However, the above are only the preferred embodiments of this creation, and are not used to limit the scope of implementation of this creation. For example, the equivalent changes and modifications of the shape, structure, characteristics and spirit described in the scope of the patent application for this creation are made. , Should be included in the scope of patent application for this creation.

1: Gate drive circuit on the array 10-1---10-n: drive circuit 10: Drive circuit 20: charge and discharge unit 22: The first charge and discharge unit 24: The second charge and discharge unit 30: output unit 32: The first virtual unit 34: The second virtual unit AC: low frequency AC signal AN: composite signal AN1~ANN: Synthetic signal AND: composite signal AND1: the first composite signal AND2: second composite signal AC: low frequency AC signal BUS: Signal Transmission Department D1: The first virtual signal D2: The second virtual signal DP1: output DP2: output DUMMY: virtual circuit CLK4~CLKN: clock signal G1~GN: Gate drive signal BUS: Signal Transmission Department GAP: Time segment GP: output terminal GP0: output terminal GP1: output terminal GP2: output terminal GP3: output terminal GP4: output terminal GP5: output terminal GP6: output terminal GP7: output terminal GPN-7: output GPN-6: output GPN-6: output GPN-5: output GPN-4: output GPN-3: output GPN-2: output GPN-1: output GPN: output NOISE: Noise VSTART: start signal VSTOP: Stop signal

Figure 1 A: It is a schematic diagram of the gate drive circuit on the array according to an embodiment of the creation; Fig. 1B: It is a schematic diagram of the first-level driving circuit of an embodiment of the creation; Figure 1 C: It is a schematic diagram of a single-stage drive circuit according to an embodiment of the creation; Figure 1 D: It is a schematic diagram of the penultimate stage driving circuit of an embodiment of the creation; The first E: it is a schematic diagram of the last-stage driving circuit of an embodiment of the creation; and Figure F: It is a schematic diagram of the virtual circuit of an embodiment of the creation.

1: Gate drive circuit

10-1---10-n: drive circuit

AN1---ANN: Synthetic signal

AND1: composite signal

AND2: composite signal

D1: The first virtual signal

D2: The second virtual signal

DUMMY: virtual circuit

G1---GN: Gate drive signal

VSTART: start signal

VSTOP: Stop signal

CLK4---CLKN: clock signal

Claims (6)

A gate drive circuit on an array with virtual output, which comprises: A plurality of driving circuits, one of the first-level driving circuits of the driving circuits is coupled to an external integrated circuit, a second-level driving circuit and a third-level driving circuit; the driving circuits are from the second-level The driving circuits are respectively coupled to an upper level driving circuit and a lower level driving circuit up to a penultimate level driving circuit; one of the driving circuits is coupled to the penultimate level driving circuit and Coupled to a final drive circuit and a virtual circuit; the final drive circuit of the drive circuits is coupled to the penultimate drive circuit and is coupled to the virtual circuit and the external integrated circuit; Wherein, the first-level driving circuit controls the potential rise of a plurality of composite signals corresponding to a plurality of first gate driving signals according to an initial signal of the external integrated circuit, and according to the plurality of second-level driving circuits of the second-level driving circuit. The two-gate drive signal and one of the third-level drive circuits control the potential pull-down of the composite signals corresponding to the first gate drive signals; the drive circuits are controlled from the first gate drive signals. The second-level driving circuit up to the penultimate third-level driving circuit is based on a plurality of upper-level gate driving signals of the upper-level driving circuit and a plurality of lower-level gate driving signals of the lower-level driving circuit and a lower-level gate driving Signal to control the plurality of driving circuits from the second-level driving circuit to the plurality of gate driving signals corresponding to the penultimate third-level driving circuit; Control a plurality of penultimate second stages according to the plurality of penultimate third gate drive signals of the penultimate third-stage drive circuit, the plurality of last-stage gate drive signals of the last-stage drive circuit, and a first virtual signal of the virtual circuit The potential of the plurality of composite signals corresponding to the gate drive signal rises or the potential falls; the last-stage drive circuit is based on the penultimate-stage gate drive signals of the penultimate-stage drive circuit, and one of the virtual circuits is second The virtual signal and one of the external integrated circuits turn off the signal, and the plurality of composite signals corresponding to the last-stage gate driving signals of the last-stage driving circuit are controlled to rise or pull down in potential. The gate driving circuit on the array according to claim 1, wherein the driving circuits respectively include a plurality of charging and discharging units and a plurality of output units, from the second-stage driving circuit to the penultimate third-stage driving circuit. A plurality of charge and discharge units are coupled to a plurality of upper-level output units of the upper-level driving circuit and are coupled to a plurality of lower-level output units of the lower-level driving circuit and a lower-next-level output unit to generate the corresponding composite signals To the corresponding output units to further generate the gate driving signals according to the corresponding plural clock signals. The gate driving circuit on the array according to claim 1, wherein the driving circuits are further coupled to a plurality of clock signals and a plurality of low-frequency AC signals, respectively. The gate drive circuit on the array according to claim 1, wherein the virtual circuit includes: A first charging and discharging unit coupled to a first output unit of the last-stage drive circuit and the cut-off signal to generate a first composite signal; A first dummy unit, coupled to the first charging and discharging unit, to generate the first dummy signal; A second charging and discharging unit coupled to a fourth output unit of the last-stage drive circuit and the cut-off signal to generate a second composite signal; and A second dummy unit, coupled to the second charging and discharging unit, to generate the second dummy signal; Wherein, the first charging and discharging unit controls the potential rise of the first composite signal according to the last-stage gate drive signal corresponding to the first output unit of the last-stage drive circuit to drive the potential of the first virtual signal to rise, The second charging and discharging unit controls the corresponding increase in the potential of the second composite signal according to the last-stage gate drive signal of the fourth output unit of the last-stage drive circuit to drive the potential of the second virtual signal to rise, the The first virtual unit and the second virtual unit control the pull-down of the potentials of the composite signals corresponding to the first virtual signal and the second virtual signal according to the cut-off signal to drive the first of the first and second virtual units , The potential of the second virtual signal is pulled down. The gate driving circuit on the array according to claim 4, wherein the last-stage driving circuit controls the potential pull-down of the composite signal corresponding to the last-stage gate driving signals according to the second virtual signal and the cut-off signal. The gate drive circuit on the array according to claim 1, wherein the cut-off signal supports the pull-down potential of the composite signal corresponding to a maximum of 7 gate drive signals.

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