TW202248979A - Circuit for gate drivers on arrays with dummy output signals - Google Patents

Abstract

The invention related to a circuit for gate drivers on arrays with dummy output signals, in which the final stage driving circuit of the gate drivers on arrays is further coupled to a plurality of last two stage output units of a last two stage driving circuit to receive a plurality of last two stage gate driving signals, and further coupled to at least one virtual circuit to receive at least one virtual signal, for controlling levels of An signals corresponding to the gate driving signals of the final stage driving circuit going up or going down. Thus, the error outputting and the VSTOP signals inputted to the final stage driving circuit are reduced.

Description

Array gate driver circuit with dummy output

The invention relates to a control circuit, in particular to an array gate drive circuit with reduced cut-off signal input.

Thin Film Transistor Liquid Crystal Displays (TFT-LCDs, Thin Film Transistor Liquid Crystal Displays) have become the mainstream of modern display technology products, especially for mobile phones, with the characteristics of lightness and portability. Compared with polysilicon thin film transistors (Poly-Si TFTs), displays made using amorphous silicon thin film transistors (a-Si TFTs) can reduce production costs and can be fabricated on large-area glass substrates at low temperatures , to increase the production rate.

As the concept of System-on-Glass (SOG, System-on-Glass) has been proposed, many products recently integrate the Gate driver or Scan driver in the display driver circuit on the glass, that is, GOA (Gate-Driver-on-Array) circuit, GOA circuit has many advantages. In addition to reducing the area of the display frame to achieve a thin frame, it can also reduce the use of gate scanning driver ICs, reduce the cost of purchasing ICs and avoid glass The problem of disconnection when bonding with IC is used to improve product yield. At present, it has been widely used in small and medium-sized displays such as mobile phones and notebook computers, and even products using GOA circuits for large displays have come out in recent years.

In response to changes in consumer habits, products are gradually evolving toward high reliability, wide-area operation, and narrow bezels. The traditional GOA circuit can be divided into a signal transmission part, an anti-noise part, and a gate pulse (Gate pulse) output part. The signal transmission part transmits the input signal required for the internal operation of the GOA circuit, which is related to the signal transmission of the GOA circuit. The anti-noise part is the circuit inside the GOA circuit to maintain the stability of the output signal, which is related to its reliability. The gate pulse output part is the output signal of the GOA circuit to the gate line. However, taking the single-stage eight-output GOA circuit as an example, the single-stage GOA circuit generates output signals eight times repeatedly, and the signal transmission part and anti-noise part occupy most of the area of the eight-output GOA circuit. If this can be reduced The layout area of the functional circuit can achieve the effect of a narrow border, but the final stage of the GOA circuit has the problem of false output due to too many shared cut-off signals.

Based on the above problems, the present invention provides a gate drive circuit on an array with a dummy output, which simplifies the connection relationship of the gate drive circuit on the array and avoids the combination signal clearing time being too long through the circuit design of the dummy circuit. Reduce the circuit area related to false output and cut-off signals.

The main purpose of the present invention is to provide a gate driver circuit on an array with a dummy output, which is coupled to at least one dummy circuit by the last-level drive circuit, so as to simplify the last-level drive circuit and avoid the synthesis signal clearing time being too long, thereby reducing The relevant circuit area of the wrong output and cut-off signal to the final drive circuit.

The present invention discloses an array gate drive circuit with virtual output, which has a plurality of drive circuits, wherein a first-level drive circuit is coupled to an external integrated circuit, a second-level drive circuit and a third-level drive circuit Driving circuits, these driving circuits are respectively coupled to an upper-level driving circuit and a lower-level driving circuit from the second-level driving circuit to a penultimate third-level driving circuit, so as to respectively receive a plurality of upper-level gate driving signals and The plurality of next-level gate drive signals and the lower-level gate drive signals of the next-level gate drive circuit, these drive circuits until the penultimate third level are respectively based on these upper-level gate drive signals, these The next-level gate drive signal and the next-level gate drive signals are used to control the potential rise or potential drop of the composite signal corresponding to the gate drive signals; the last-level drive circuit of these drive circuits further Coupling the penultimate second-level driving circuit and coupling at least one dummy circuit and the external integrated circuit to receive a plurality of penultimate second-level gate driving signals, at least one dummy signal of the dummy circuit and the external integrated circuit A cut-off signal is used to control the potential rise or fall of the composite signal corresponding to the plurality of last-stage gate drive signals of the last-stage drive circuits of the plurality of drive circuits. By coupling at least one dummy circuit with the above-mentioned last-level driving circuit, the related circuit area of false output and cut-off signal can be reduced.

In order to enable your review committee members to have a further understanding and understanding of the characteristics of the present invention and the achieved effects, the following examples and accompanying descriptions are hereby provided:

In view of the fact that the conventional signal transmission occupies part of the area of the GOA circuit, if the relevant circuit layout area of the cut-off signal can be reduced, the effect of narrow border can be achieved. Accordingly, the present invention proposes an array gate with reduced cut-off signal input Pole drive circuit to solve the problem of circuit area caused by conventional technology.

In the following, the present invention will further illustrate the characteristics and matching structure of an array gate drive circuit with virtual output:

First, please refer to Figures 1 A to 1 F, which are a schematic diagram of a gate drive circuit, a schematic diagram of a first-stage drive circuit, a schematic diagram of a single-stage drive circuit, a schematic diagram of a final-stage drive circuit, and a schematic diagram of a virtual circuit in an embodiment of the present invention. . As shown in the first figure A, the array gate drive circuit 1 with dummy output of the present invention includes a plurality of drive circuits 10-1 to 10-n and at least one dummy circuit DUMMY. The circuit DUMMY is used as an example, and the quantity can be adjusted according to the needs of use. Each driving circuit 10 is respectively coupled to a plurality of input signals, for example: the first-level driving circuit 10-1 is coupled to an external integrated circuit (not shown) to receive a start signal VSTART and a plurality of clock signals CLK4 to CLK11 , and the first-level drive circuit 10-1 is coupled to the next-level drive circuit and the next next-level drive circuit, that is, it is coupled to the second-level drive circuit 10-2 and the third-level drive circuit (not shown), thus receiving the first The gate drive signals G9 to G16 output by the secondary drive circuit 10-2, the gate drive signal G17 output by the third drive circuit, the first drive circuit 10-1 according to the start signal VSTART of the external integrated circuit These clock signals CLK4 to CLK11 sequentially control the potential rise of the synthesized signals AN1-AN8 corresponding to the plurality of gate drive signals G1-G8 of the first-stage drive circuit 10-1, and simultaneously pass through the second-stage The gate driving signals G10 to G16 output by the driving circuit 10-2 and the gate driving signal G17 output by the third-level driving circuit pull down the potentials of the synthesized signals AN1-AN8 corresponding to the gate driving signals G1-G8.

And starting from the second-level drive circuit 10-2, each level of drive circuit is coupled to the upper-level drive circuit and the next-level drive circuit and the next-level drive circuit until the penultimate third-level drive circuit (not shown), so the second-level The driving circuit 10-2 is coupled to the first-level driving circuit 10-1 and is coupled to the third-level driving circuit (not shown) and the fourth-level driving circuit (not shown), thus receiving the first-level driving circuit 10-1 The gate driving signals G1 to G8 are used to control the potential rise of the composite signals AN9 to AN16 corresponding to the gate driving signals G9 to G16 of the second-level driving circuit 10-2, and receive the gate driving signals of the third-level driving circuit G18 to G24 and the gate driving signal G25 of the fourth-level driving circuit are used to control the pull-down of the composite signals AN9 to AN16 corresponding to the gate driving signals G9 to G16 of the second-level driving circuit 10 - 2 . Until the penultimate third-level drive circuit (not shown in the figure) is still coupled to the upper-level drive circuit and the next-level drive circuit and the next-level drive circuit, that is, it is coupled to the penultimate fourth-level drive circuit (not shown) and the penultimate drive circuit. The detailed coupling method of the second-level driving circuit 10 - n - 1 and the last-level driving circuit 10 - n is the same as that of the second-level driving circuit, so it will not be repeated here. And, the penultimate second-level driving circuit 10-n-1 is coupled to the penultimate third-level driving circuit and coupled to the last-level driving circuit 10-n and a dummy circuit DUMMY, so as to receive the gate of the penultimate third-level driving circuit The driving signals GN-23 to GN-16 are used to control the potential rise of the synthesized potentials ANN-15 to ANN-8 corresponding to the gate driving signals GN-15 to GN-8 of the penultimate driving circuit 10-n-1, And receive the gate driving signals GN-6 to GN of the last-level driving circuit 10-n and a first dummy signal D1 provided by the dummy circuit DUMMY to control the gate of the penultimate second-level driving circuit 10-n-1 The combined potentials ANN-15 to ANN-8 corresponding to the driving signals GN-15 to GN-8 are pulled down.

Referring again to the first figure A, the final drive circuit 10n of the present invention is coupled to the external integrated circuit and the dummy circuit DUMMY, so as to receive a cut-off signal VSTOP of the external integrated circuit and a first one provided by the dummy circuit DUMMY. Two dummy signals D2, and the last-level drive circuit 10n is coupled to the penultimate second-level drive circuit 10-n-1 to receive the gate drive signals GN-15 to GN-8 of the penultimate second-level drive circuit 10-n-1 Therefore, the last-stage drive circuit 10-n controls the composite signals ANN-7 to ANN corresponding to the gate drive signals GN-7 to GN of the last-stage drive circuit 10-n according to the gate drive signals GN-15 to GN-8. The potential rises, and according to the second dummy signal D2 provided by the dummy circuit DUMMY, the synthesis signals ANN-7 to ANN-5 corresponding to the gate drive signals GN-7 to GN-5 of the last stage drive circuit 10-n are controlled. Pull down the potential, and further control the potential pull-down of the synthesized signals ANN-4 to ANN corresponding to the gate drive signals GN-4 to GN according to the cut-off signal VSTOP. In this embodiment, the gate drive is controlled by the cut-off signal VSTOP and the second dummy signal D2 The potential pull-down of the synthesized signals ANN-7 to ANN corresponding to the signals GN-7 to GN can be directly controlled by the second dummy signal D2 to control the synthesized signals ANN-7 to ANN- corresponding to the gate drive signals GN-7 to GN-5 The potential of 5 is pulled down, thus avoiding the long waiting time of the combined signal ANN-7 to ANN-5 corresponding to the gate drive signal GN-7 to GN-5, resulting in false output, and saving external power by sharing the cut-off signal VSTOP The circuit area of the input signal.

As shown in the first diagram A and the first diagram B, the first stage driving circuit 10 - 1 includes a plurality of charging and discharging units 20 and a plurality of output units 30 . The first-level drive circuit 10-1 is connected to the signal transmission part BUS to receive the start signal VSTART and a plurality of clock signals CLK4-CLK11 transmitted by the signal transmission part BUS, and the signal transmission part BUS can further transmit the low-frequency AC signal AC to The first stage driving circuit 10 - 1 is used to control the pre-charging of the combined signals AN1 to AN8 . Since the low frequency AC signal AC controls the combined signals AN1 to AN8 is a conventional technology, so it will not be described again. Wherein, this embodiment is an example of 8 charging and discharging units 20 and 8 output units 30, but the present invention is not limited to 8, and the output units 30 can be designed as 2, 4, 16 or even 32 outputs according to the usage requirements. The unit 30, or a plurality of output units 30 are shared. This embodiment is based on the current technology, and the signal response is better, and the circuit is relatively simplified. Therefore, in this embodiment, 8 charging and discharging units 20 and 8 The output unit 30 is shown as an example.

Continuing the above, since the first-level driving circuit 10-1 does not have an upper-level driving circuit, each charging and discharging unit 20 receives the start signal VSTART to generate corresponding composite signals AN1-AN8, and each output unit 30 That is to receive the synthesized signals AN1~AN8 corresponding to the clock signal CLK4-CLK11 and inside the circuit, wherein the synthesized signals AN1~AN8 correspond to the clock signal CLK4-CLK11, so that these output units 30 are respectively connected to a plurality of output terminals GP1~GP8 generate gate driving signals G1~G8, that is, the potentials of the synthesized signals AN1~AN8 correspond to the potentials of the gate driving signals G1~G8 of the output terminals GP1~GP8, and the first stage driving circuit 10-1 The first-level drive circuit is the second-level drive circuit 10-2, and the next next-level drive circuit is the third-level drive circuit (not shown), so the first-level drive circuit 10-1 further receives the second-level drive circuit 10-1. 2. The gate drive signals G10 to G16 output by the third-level drive circuit and the gate drive signal G17 output by the third-level drive circuit, that is, the charging and discharging units 20 receive the gate drive output by the second-level drive circuit 10-2 The signals G10 to G16 and the gate drive signal G17 output by the third-level drive circuit are used to pull down the potentials of the composite signals AN1~AN8 corresponding to the gate drive signals G1-G8, so that the composite signals form a sequential potential rise with potential pull-down.

Referring to the first figure A and the first figure C, the charging and discharging units 20 from the second-level driving circuit 10-2 to the penultimate third-level driving circuit are all coupled to the upper driving circuit. The output unit of the upper stage and the multiple next-stage output units of the next-stage drive circuit and the multiple next-stage output units of the next-stage drive circuit, so as shown in the first C figure, from the second-stage drive circuit 10-2 to Each drive circuit 10 of the penultimate third level receives a plurality of upper gate drive signals G-8 from the upper drive circuit (not shown) and the next drive circuit and the next next drive circuit (not shown) A plurality of next-level gate driving signals G+9, for example: for the gate driving signal G9, G-8 is G1 of the first-level driving circuit 10-1, and G+9 is the third-level driving circuit ( G18 of the figure not shown); for the gate driving signal G16, G-8 is G8 of the first-level driving circuit 10-1, and G+9 is the gate driving signal of the fourth-level driving circuit (not shown) G25, instead of receiving the start signal VSTART or the stop signal VSTOP, the output unit 30 receives the composite signal AN generated by the charging and discharging unit 20, and the charging and discharging unit 20 receives the upper-level gate drive signal G-8 and the lower-level gate drive signal G+9, to generate the corresponding composite signal AN, and the potential of the composite signal AN corresponding to the gate driving signal G is raised by the upper gate driving signal G-8, and by the lower secondary gate driving signal G +9 pulls down the potential of the composite signal AN corresponding to the gate driving signal G, therefore, the output unit 30 can generate the corresponding gate driving signal G at the signal output terminal GP according to the corresponding composite signal AN and the corresponding clock signal CLK respectively In this embodiment, a single-stage drive circuit 10 is provided with 8 output terminals GP, and correspondingly outputs 8 gate drive signals G for illustration. The synthesized signal AN inside the drive circuit 10 corresponds to the clock signal CLK, so the gate The driving signal G will correspond to the timing of the clock signal CLK.

Please refer to the first A diagram and the first D diagram together, the penultimate second stage drive circuit 10-n-1 of the present invention has a plurality of charge and discharge units 20 and a plurality of output units 30, and the charge and discharge units 20 are respectively coupled Connect to the penultimate third-level drive circuit to receive the corresponding gate drive signals GN-23 to GN-16, and the charging and discharging unit 20 is further coupled to the last-level drive circuit 10n and dummy circuit DUMMY, especially corresponding to the gate drive signal The charging and discharging unit 20 of GN-8 is coupled to the dummy circuit DUMMY, thus receiving the first dummy signal D1 of the dummy circuit DUMMY, and the remaining charging and discharging units 20 are coupled to the last-level drive circuit 10-n to receive the last-level drive circuit 10 -n gate drive signal GN-6 to GN. Wherein, the charging and discharging unit 20 respectively generates corresponding composite signals ANN-15 to ANN-8 for the output unit 30 to generate respectively according to the clock signals CLKN-15 to CLKN-8 and the corresponding composite signals ANN-15 to ANN-8 Corresponding gate drive signals GN-15 to GN-8.

Referring to the first A diagram and the first E diagram together, the last-level driving circuit 10-n of the present invention is respectively coupled to the penultimate second-level driving circuit 10-n-1, the dummy circuit DUMMY and the external integrated circuit, so The charging and discharging unit 20 of the last-level driving circuit 10-n receives the second dummy signal D2 and the gate driving signals GN-15 to GN-8 of the penultimate second-level driving circuit 10-n-1, and the last-level driving circuit 10- n further receives the clock signals CLKN-7 to CLKN provided by the external integrated circuit transmitted by the signal transmission part BUS, and further receives the low-frequency AC signal AC, and the output unit 30 of the last stage drive circuit 10-n receives the clock signal CLKN-7 to CLKN and synthesized signals ANN-7~ANN are used to output gate drive signals GN-7 to GN at corresponding output terminals GPN-7 to GPN, wherein these synthesized signals ANN~ANN are corresponding to clock signals CLKN-7 to CLKN.

Furthermore, in the present invention, the charging and discharging units 20 corresponding to the last-level driving circuit 10-n are further coupled to the dummy circuit DUMMY and the cut-off signal VSTOP, so that some charging and discharging units 20 are coupled to the second dummy signal D2, and some The charging and discharging unit 20 shares the stop signal VSTOP, and the potential control of the gate drive signals GN-7 to GN-5 corresponding to the output terminals GPN-7 to GPN-5 is controlled by the charging and discharging unit 20 according to the second dummy signal D2 to pull down the synthesized signal ANN- The potential of 7 to ANN-5 makes the potential of the corresponding gate drive signal GN-7 to GN-5 pull down, and the potential of the gate drive signal GN-4 to GN corresponding to the output terminal GPN-4 to GPN is controlled to charge The discharge unit 20 pulls down the potentials of the synthesized signals ANN-4 to ANN according to the cut-off signal VSTOP, so that the potentials of the corresponding gate drive signals GN-4 to GN are pulled down, for example: in this embodiment, the synthesized signals ANN-7 to ANN-5 The corresponding charging and discharging unit 20 is coupled to the second dummy signal D2, and the corresponding charging and discharging unit 20 of the synthesized signal ANN-4 to ANN is coupled to the cut-off signal VSTOP to pull down the potential of the synthesized signal ANN-7 to ANN, so the last stage of the driving circuit 10-n can directly control the potential pull-down of the synthesized signals ANN-7 to ANN-5 corresponding to the gate drive signals GN-7 to GN-5 by the second dummy signal D2, thus avoiding the gate drive signals GN-7 to GN -5 corresponds to the potential pull-down of composite signals ANN-7 to ANN-5. -7, and at the same time reduce the relevant circuit area of the cut-off signal VSTOP input to the last stage driving circuit 10-n. In addition, the stop signal VSTOP supports the potential pull-down of the synthesized signals corresponding to at most 7 gate driving signals.

As shown in the first figure F, the dummy circuit DUMMY is similar to the drive circuit 10, and the dummy circuit DUMMY includes a first charging and discharging unit 22, a second charging and discharging unit 24, a first dummy unit 32 and a second dummy unit 34 , the first charge and discharge unit 22 is respectively coupled to the first output unit 30 of the last-stage drive circuit 10-n (that is, the output unit 30 corresponding to the gate drive signal GN-7) to generate the composite signal AND1 respectively, and the first The second charge and discharge unit 24 is coupled to the fourth output unit of the last-level drive circuit 10-n (that is, the output unit 30 corresponding to the gate drive signal GN-4), so as to generate the composite signal AND2 respectively, and the first dummy unit 32 is the eighth charge-discharge unit (that is, the charge-discharge unit 20 corresponding to the composite signal ANN-8) coupled to the first charge-discharge unit 22 and the penultimate second-stage drive circuit 10-n-1, and receives the composite signal AND1 and the clock signal CLKN-7 to generate the charge and discharge unit 20 corresponding to the first dummy signal D1 to the composite signal ANN-8, and the second dummy unit 34 is coupled to the second charge and discharge unit 24 and the final drive circuit 10-n The first to third charging and discharging units (that is, the charging and discharging unit 20 corresponding to the composite signal ANN-7, ANN-6, and ANN-5) receive the composite signal AND2 and the clock signal CLK-4 to generate the second The dummy signal D2 is sent to the charging and discharging unit 20 corresponding to the combined signals ANN-7, ANN-6 and ANN-5.

However, the dummy circuit DUMMY is not used to drive the display panel (not shown), but outputs the first dummy signal D1 and the second dummy signal D2 to the penultimate second-level driving circuit 10-n-1 and the last-level driving circuit 10- n, the first dummy signal D1 is only used to pull down the synthesized signal ANN-8 corresponding to the gate drive signal GN-8, and the second dummy signal D2 is only used to pull down the composite signal corresponding to the gate drive signals GN-7 to GN-5 The synthesized signals ANN-7˜ANN-5 do not affect the display effect, that is, the first dummy signal D1 and the second dummy signal D2 are not output to the TFTs of the pixels of the display panel.

Among them, the control of the first dummy signal D1 output from the output terminal DP1 is that the first charging and discharging unit 22 controls the potential rise of the synthesized signal AND1 according to the gate driving signal GN-7 of the last-level driving circuit 10-n, and the first dummy unit 32 According to the synthesis signal AND1 and the clock signal CLKN-6, the potential of the first dummy signal D1 of the first dummy unit 32 is driven to rise, and the corresponding first dummy signal D1 is sent to the penultimate second-level driving circuit 10-n- 1. It is used to control the charging and discharging unit 20 corresponding to the gate drive signal GN-8, so that the potential of the corresponding composite signal ANN-8 is pulled down, and the potential of the second dummy signal D2 output by the second dummy unit 34 is controlled to be the second The charging and discharging unit 24 controls the potential rise of the composite signal AND2 according to the gate driving signal GN-4 of the last-level driving circuit 10-n, and the second dummy unit 34 drives the second dummy unit 34 according to the composite signal AND2. The potential of the dummy signal D2 rises to generate a corresponding second dummy signal D2 to the final drive circuit 10-n for controlling the charge and discharge unit 20 corresponding to the gate drive signals GN-7, GN-6, and GN-5, so that the corresponding The composite signal ANN-7~ANN-5 is pulled down.

The first dummy unit 32 and the second dummy unit 34 control the potential pull-down of the composite signals AND1 and AND2 corresponding to the first dummy signal D1 and the second dummy signal D2 according to the stop signal VSTOP, so as to drive the first , Pulling down the potentials of the first and second dummy signals D1 and D2 of the second dummy units 32 and 34 .

Therefore, the present invention uses the first dummy signal D1 and the second dummy signal D2 outputted by the dummy circuit DUMMY to pull down the synthesized signals ANN-8~ANN-5 corresponding to the gate drive signals GN-8 to GN-5, thereby avoiding sharing the cut-off signal VSTOP Too many lead to the pull-down waiting time of the composite signals ANN-8~ANN-5 corresponding to the gate drive signals GN-8 to GN-5 is too long, and allow a single cut-off signal VSTOP to support the entire last-level drive circuit 10-n Part of the gate driving signals GN- 4 to GN are pulled down for the synthetic signals ANN- 4 -ANN corresponding to the potentials, so as to reduce false output and reduce the related circuit area of the cut-off signal VSTOP input to the last-stage driving circuit 10 -n. In addition, the dummy circuit DUMMY can further adjust the number of corresponding dummy signals according to the number of output terminals of the last-stage driving circuit 10-n, so that the final-stage driving circuit 10-n can pull down regardless of the output signal.

Please refer to the second figure A, which is the waveform diagram of the synthesized signal corresponding to the output gate drive signal without using the dummy circuit. As shown in the figure, the composite signal corresponding to the gate drive signal output by the last stage drive circuit is coupled to a single cut-off signal (not shown in the figure), for example: the composite signal corresponding to the gate drive signal GN-8 waits for the pull-down potential The time is too long, so there will be additional warpage in the signal end area C of the composite signal ANN-8 corresponding to the gate drive signal GN-8, which will cause the corresponding gate drive signal GN-8 to output incorrectly, and the gate drive The pixel corresponding to the signal GN-8 is abnormally outputting the display signal, as shown in the second figure B, for the first virtual unit 32 or the second virtual unit 34, the synthesized signal AND and the virtual signal D are corresponding signal, the first dummy unit 32 or the second dummy unit 34 share the cut-off signal VSTOP, if the first dummy unit 32 has a wrong output due to the long waiting time of the node that synthesizes the signal AND, it forms an incorrect signal before the cut-off signal VSTOP The normal warped signal waveform will cause noise NOISE, and will cause the false output of the dummy signal D, for example, the wrong output of the first dummy signal D1, which will cause the wrong output of the corresponding gate driving signal GN-8.

Refer to Figure 3, which is a waveform diagram of a synthesized signal corresponding to the output gate drive signal of the present invention. As shown in the figure, the present invention utilizes the combined signals AND1 and AND2 corresponding to the first dummy signal D1 and the second dummy signal D2 of the dummy circuit DUMMY to cause the signal waveform to have a boundary in the end region C, which is shown in the third figure A The signal end area C of the second virtual signal D2 is vertically pulled down by the stop signal VSTOP, as shown in the third figure B, due to the signal boundary, the noise NOISE is reduced and the turn-on timing of the stop signal VSTOP is adjusted forward by a time zone The segment GAP, that is, the synthesized signal AND2 corresponding to the second dummy signal D2 is close to the stop signal VSTOP in timing, and does not warp abnormally as shown in the second figure B, thus avoiding the gate driving signals GN-7 to GN- 5. The pixels corresponding to the control are abnormally output display signals, thereby improving the reliability of wide-temperature operation.

In summary, the gate drive circuit on the array with dummy output of the present invention is coupled to the penultimate drive circuit and the last drive circuit through the dummy circuit, so that the penultimate drive circuit and the last drive circuit The circuit uses the virtual signal provided by the virtual circuit to control the potential pull-down of the composite signal corresponding to the gate drive signal and the corresponding timing of the cut-off signal, so as to avoid the potential pull-down of the composite signal corresponding to the gate drive signal due to too much common cut-off signal VSTOP The waiting time is too long to reduce false output, and by sharing the cut-off signal, the relevant circuit area of the input cut-off signal to the final drive circuit is reduced.

Therefore, the present invention is novel, progressive and can be used in industry. It should meet the patent application requirements of my country's patent law. I file an invention patent application in accordance with the law. I pray that the bureau will grant the patent as soon as possible. I sincerely pray.

However, the above-mentioned ones are only preferred embodiments of the present invention, and are not used to limit the scope of the present invention. For example, all equal changes and modifications are made according to the shape, structure, characteristics and spirit described in the scope of the patent application of the present invention. , should be included in the patent application scope of the present invention.

1: Gate drive circuit on the array 10-1---10-n: drive circuit 10: Drive circuit 20: Charge and discharge unit 22: The first charging and discharging unit 24: The second charging and discharging unit 30: output unit 32: The first virtual unit 34: Second virtual unit AC: low frequency alternating current signal AN: synthetic signal AN1~ANN: synthetic signal AND: Composite signal AND1: the first composite signal AND2: Second composite signal AC: low frequency alternating current signal BUS: Signal transmission department D1: the first virtual signal D2: Second virtual signal DP1: output port DP2: output port DUMMY: virtual circuit CLK4~CLKN: clock signal G1~GN: Gate drive signal BUS: Signal transmission department GAP: Time segment GP: output terminal GP0: output terminal GP1: output terminal GP2: output terminal GP3: output terminal GP4: output terminal GP5: output terminal GP6: output terminal GP7: output terminal GPN-7: output terminal GPN-6: output terminal GPN-6: output terminal GPN-5: output terminal GPN-4: output terminal GPN-3: output terminal GPN-2: output terminal GPN-1: output terminal GPN: output terminal NOISE: noise VSTART: start signal VSTOP: stop signal

The first figure A: It is a schematic diagram of the gate drive circuit on the array according to one embodiment of the present invention; The first B figure: it is a schematic diagram of the first stage drive circuit of one embodiment of the present invention; Figure 1 C: It is a schematic diagram of a single-stage drive circuit according to an embodiment of the present invention; Figure 1 D: It is a schematic diagram of the second-to-last drive circuit of an embodiment of the present invention; The first E figure: it is a schematic diagram of the last stage drive circuit of an embodiment of the present invention; The first F figure: it is a virtual circuit schematic diagram of an embodiment of the present invention; The second figure A: it is the waveform diagram of the output gate drive signal without dummy signal; The second figure B: it is a waveform diagram of a composite signal without boundaries and a virtual signal versus a cut-off signal; The third figure A: it is a waveform diagram of the output gate driving signal of the present invention; and Figure 3 B: It is a waveform diagram of the synthesized signal and the virtual signal versus the cut-off signal of the present invention.

1: Gate drive circuit

10-1---10-n: drive circuit

AN1---ANN: synthetic signal

AND1: synthetic signal

AND2: synthetic signal

D1: the first virtual signal

D2: Second virtual signal

DUMMY: virtual circuit

G1---GN: gate drive signal

VSTART: start signal

VSTOP: stop signal

CLK4---CLKN: clock signal

Claims (7)

A gate drive circuit on an array with dummy output, comprising: A plurality of driving circuits, wherein one of the first-level driving circuits of the driving circuits is coupled to an external integrated circuit, a second-level driving circuit, and a third-level driving circuit; the driving circuits are connected from the second level The driving circuits are respectively coupled to an upper-level driving circuit and to the lower-level driving circuit until a penultimate third-level driving circuit; one of the penultimate driving circuits of the driving circuits is coupled to the penultimate third-level driving circuit and coupling a last-level driving circuit and a dummy circuit; the last-level driving circuit of the plurality of driving circuits is coupled to the penultimate second-level driving circuit and coupled to the dummy circuit and the external integrated circuit; Wherein, the first-level driving circuit controls the potential rise of the plurality of composite signals corresponding to the plurality of first gate driving signals according to the initial signal of the external integrated circuit, and controls the potential rise of the plurality of composite signals corresponding to the plurality of first gate driving signals, and controls the potential rise of the plurality of first gate driving signals according to the second-level driving circuit. The second gate driving signal and the third gate driving signal of the third-level driving circuit control the potential pull-down of the composite signals corresponding to the first gate driving signals; The second-level drive circuit until the penultimate third-level drive circuit is based on a plurality of upper-level gate drive signals of the upper-level drive circuit and a plurality of lower-level gate drive signals of the lower-level drive circuit. signal to control the driving circuits from the second-level driving circuit to the multiple gate driving signals of the penultimate third-level driving circuit. Controlling the plurality of second-to-last stages based on the plurality of third-to-last gate drive signals of the penultimate third-stage drive circuit, the plurality of last-stage gate drive signals of the last-stage drive circuit, and the first dummy signal of the dummy circuit The potential rise or fall of the plurality of composite signals corresponding to the gate drive signal; The dummy signal and one cut-off signal of the external integrated circuit are used to control the potential rise or pull down of a plurality of composite signals corresponding to the final gate drive signals of the final drive circuit. The gate drive circuit on the array as described in Claim 1, wherein the drive circuits respectively include a plurality of charging and discharging units and a plurality of output units, from the second-level drive circuit to the penultimate third-level drive circuit. The charging and discharging units are coupled to a plurality of upper output units of the upper driving circuit and coupled to a plurality of lower output units and a lower output unit of the lower driving circuit, so as to generate corresponding synthesized signals to the corresponding output units, so as to further generate the gate drive signals according to the corresponding plurality of clock signals. The gate drive circuit on the array as described in Claim 1, wherein the drive circuits are further respectively coupled to a plurality of clock signals and a plurality of low-frequency AC signals. The gate drive circuit on the array as described in claim 1, wherein the dummy circuit includes: a first charging and discharging unit, coupled to a first output unit of the last-stage drive circuit and the cut-off signal to generate a first composite signal; a first dummy unit, coupled to the first charging and discharging unit, to generate the first dummy signal; a second charging and discharging unit, coupled to a fourth output unit of the last-stage drive circuit and the cut-off signal to generate a second composite signal; and a second dummy unit coupled to the second charging and discharging unit to generate the second dummy signal; Wherein, the first charge-discharge unit controls the potential rise of the first composite signal according to the last-stage gate drive signal corresponding to the first output unit of the last-stage drive circuit, so as to drive the potential rise of the first dummy signal, The second charge-discharge unit controls the potential increase of the corresponding second composite signal according to the last-level gate driving signal of the fourth output unit of the last-level driving circuit, so as to drive the potential of the second dummy signal to rise. The first dummy unit and the second dummy unit control the potential pull-down of the synthesized signals corresponding to the first dummy signal and the second dummy signal according to the cut-off signal, so as to drive the first dummy unit of the first and second dummy units , Pulling down the potential of the second dummy signal. The gate driving circuit on the array as described in claim 4, wherein the last-level driving circuit controls the potential pull-down of the composite signal corresponding to the last-level gate driving signals according to the second dummy signal and the cut-off signal. The gate drive circuit on the array as described in Claim 1, wherein the cut-off signal supports a pull-down potential of a synthesized signal corresponding to at most 7 gate drive signals. The gate drive circuit on the array as described in Claim 4, wherein the signal end area of the second dummy signal is vertically pulled down, so that the turn-on timing of the cut-off signal is advanced.

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