TWI497377B - Shift register for photo sensing touch panel - Google Patents

Description

Shift register for light sensing touch panel

The invention relates to a shift register, in particular to a shift register for a light-sensing touch panel.

At present, the design trend of the display panel is to integrate the shift register in the gate driving circuit on the display panel instead of the external driving chip, thereby reducing the manufacturing process, increasing the integration of the display panel, and reducing the manufacturing cost.

FIG. 1 is a schematic diagram of a shift register 100 and a pixel array 110 of a display panel. As shown in FIG. 1, the shift register 100 includes a multi-stage shift register, and only the N-1th shift register 102, the Nth shift register 104, and the N+1 stage shift register 106.

Since each stage shift register in the shift register 100 of FIG. 1 outputs only one gate signal to drive the pixel array 110, for example, the N-1th shift register 102 outputs only the N-th The first stage gate signal SG(n-1) to the pixel array 110, the Nth stage shift register 104 outputs only the Nth stage gate signal SG(n) to the pixel array 110, and the N+1th stage shift The bit buffer 106 outputs only the N+1th gate signal SG(n+1) to the pixel array 110. However, the optically-sensitive touch display panel formed after the display panel is added with the light-sensing touch function needs to receive the gate signal from the shift register 100, and needs to be connected. Another signal different from the gate signal is normally operated. If the external driver chip provides another signal to the light-sensing touch display panel, the advantages of the integrated shift register on the display panel cannot be extended to the light. Inductive touch display panel.

Embodiments of the present invention disclose an Nth stage shift register that can provide two different pulse width output signals for use in a light sensing touch panel. The shift register includes a drive circuit and a first pull-down circuit. The driving circuit is configured to provide the first gate signal and the sensing signal according to the first driving signal. The pulse widths of the first gate signal and the sensing signal are different.

The shift register in the integrated gate driving circuit of the invention is on the light sensing touch panel, and the Nth stage shift register can generate two different pulse width output signals for providing the light sensing touch display. The signal required by the panel does not require an external driver chip, thereby reducing the manufacturing process of the light-sensitive touch display panel and improving the integration, reducing the number of processes and reducing the manufacturing cost.

FIG. 2 is a schematic diagram of an Nth stage shift register 200 according to an embodiment of the present invention. As shown in FIG. 2, the Nth stage shift register 200 includes a driving circuit 202, a first pull-down circuit 204, a first pull-down control circuit 206, a main pull-down circuit 208, a pull-up circuit 210, and a second pull-down circuit. 212, a second pull-down control circuit 214 and a capacitor 216. The driving circuit 202 is configured to receive and according to the first driving signal Q(n) and the first high frequency clock signal HC1 For the first gate signal G(n) and the sensing signal S(n). The first pull-down control circuit 206 is configured to generate a first pull-down control signal K(n) according to the first driving signal Q(n) and the first low-frequency clock signal LC1. The first pull-down circuit 204 is coupled to the driving circuit 202 and the first pull-down control circuit 206 for pulling down the first driving signal Q(n) and the first gate signal G according to the first pull-down control signal K(n). (n) and the sensing signal S(n). The main pull-down circuit 208 is coupled to the driving circuit 202 for pulling down the first driving signal Q according to the second gate signal G(n+2) (which can be the gate signal from the N+2 stage shift register) (n) and the sensing signal S(n). The second pull-down control circuit 214 is configured to generate a second pull-down control signal P(n) according to the first driving signal Q(n) and the second low-frequency clock signal LC2. The second pull-down circuit 212 is coupled to the driving circuit 202 and the second pull-down control circuit 214 for pulling down the first driving signal Q(n) and the first gate signal G(n) according to the second pull-down control signal P(n). And the sensing signal S(n). The pull-up circuit 210 is coupled to the driving circuit 202 for providing the second driving signal Q(n+1) to another stage shift register according to the first driving signal Q(n) (which may be the N+1th shift) The drive circuit of the bit register).

The driving circuit 202 includes a first transistor T21, a second transistor T22, a third transistor T23, and a fourth transistor T24. The pull-up circuit 210 includes a fifth transistor T11. The main pull-down circuit 208 includes a sixth transistor T31 and a seventh transistor T41. The first pull-down circuit 204 includes an eighth transistor T35, a ninth transistor T33, and a tenth transistor T43. The first pull-down control circuit 206 includes an eleventh transistor T61, a twelfth transistor T62, a thirteenth transistor T63, and a fourteenth transistor T64. The second pull-down circuit 212 includes a fifteenth transistor T34, a sixteenth transistor T32, and a seventeenth transistor T42. The second pull-down control circuit 214 includes an eighteenth transistor T51, a nineteenth transistor T52, and a second Ten transistor T53 and twenty-first transistor T54.

The first transistor T21 has a control terminal for receiving the first driving signal Q(n) for receiving the first end of the first high frequency clock signal HC1, and for providing the first gate signal G(n) The second end. The second transistor T22 has a control end coupled to the control end of the first transistor T21, coupled to the first end of the first end of the first transistor T21, and the second end. The third transistor T23 has a control end coupled to the control end of the first transistor T21, coupled to the first end of the first end of the first transistor T21, and the second end. The fourth transistor T24 has a control end coupled to the second end of the second transistor T22, a first end coupled to the second end of the third transistor T23, and a second portion for providing the sensing signal S(n) Two ends. The fifth transistor T11 has a control end coupled to the second end of the second transistor T22, coupled to the first end of the second end of the first transistor T21, and configured to provide the second driving signal Q(n+1) The second end of the). The sixth transistor T31 has a control terminal for receiving the second gate signal G(n+2), a first terminal coupled to the second terminal of the fourth transistor T24, and a first low potential Sn_VSS. Second end. The seventh transistor T41 has a control end coupled to the control terminal of the sixth transistor T31, a first end coupled to the control terminal of the first transistor T21, and a second terminal for receiving the second low potential Gn_VSS. The eighth transistor T35 has a control terminal for receiving the first pull-down control signal K(n), a first end coupled to the second end of the fourth transistor T24, and a first terminal for receiving the first low potential Sn_VSS Two ends. The ninth transistor T33 has a control end coupled to the control terminal of the eighth transistor T35, a first end coupled to the second end of the first transistor T21, and a second end for receiving the second low potential Gn_VSS. The tenth transistor T43 has a control end coupled to the control end of the eighth transistor T35, and is coupled to the first end of the control end of the first transistor T21. The second end of the first transistor T21 or the second end of the ninth transistor T33. The eleventh transistor T61 has a control end for receiving the first low frequency clock signal LC1, a first end coupled to the control end of the eleventh transistor T61, and a second end. The twelfth transistor T62 has a control end for receiving the first driving signal Q(n), a first end coupled to the second end of the eleventh transistor T61, and a first end coupled to the ninth transistor T33. The second end of the two ends. The thirteenth transistor T63 has a control end coupled to the second end of the eleventh transistor T61, coupled to the first end of the control end of the eleventh transistor T61, and coupled to the control of the eighth transistor T35 The second end of the end. The fourteenth transistor T64 has a control end coupled to the control end of the twelfth transistor T62, coupled to the first end of the second end of the thirteenth transistor T63, and coupled to the ninth transistor T33 The second end of the two ends. The fifteenth transistor T34 has a control terminal for receiving the second pull-down control signal P(n), a first end coupled to the second end of the fourth transistor T24, and a first terminal for receiving the first low potential Sn_VSS Two ends. The sixteenth transistor T32 has a control end coupled to the control end of the fifteenth transistor T34, a first end coupled to the second end of the first transistor T21, and a second end for receiving the second low potential Gn_VSS end. The seventh transistor T42 has a control end coupled to the control end of the fifteenth transistor T34, and a first end coupled to the control end of the first transistor T21, and a second end coupled to the first The second end of the crystal T21 or the second end of the sixteenth transistor T32. The eighteenth transistor T51 has a control end for receiving the second low frequency clock signal LC2, a first end coupled to the control end of the eighteenth transistor T51, and a second end. The nineteenth transistor T52 has a control terminal for receiving the first driving signal Q(n), a first end coupled to the second end of the eighteenth transistor T51, and a coupling to the sixteenth transistor T32. The second end of the second end. The twentieth transistor T53 has a control end coupled to the second end of the eighteenth transistor T51, coupled The first end of the control end of the eighteenth transistor T51, and the second end of the control end of the fifteenth transistor T34. The twenty-first transistor T54 has a control end coupled to the control end of the nineteenth transistor T52, coupled to the first end of the second end of the twentieth transistor T53, and coupled to the sixteenth transistor T32. The second end of the second end. The capacitor 216 is coupled between the control end and the second end of the first transistor T21. The first low potential Sn_VSS may be higher than the second low potential Gn_VSS.

FIG. 3 is a schematic diagram showing the waveforms of the operation-related signals of the Nth stage shift register 200 of FIG. 2, wherein the horizontal axis t is the time axis. In the third figure, the signals from top to bottom are the first high frequency clock signal HC1, the second high frequency clock signal HC2, the third high frequency clock signal HC3, the fourth high frequency clock signal HC4, The third gate signal G(n-1) (which may be the gate signal from the N-1th stage shift register), the first gate signal G(n), the first driving signal Q(n), The sensing signal S(n) and the second gate signal G(n+2). The third gate signal G(n-1) is coupled to the Nth stage shift register 200 through the pull-up circuit T11 _{N-1 of} the N-1th stage shift register to provide the Nth stage shift The first drive signal Q(n) of the bit buffer 200. The frequencies of the first high frequency clock signal HC1, the second high frequency clock signal HC2, the third high frequency clock signal HC3, and the fourth high frequency clock signal HC4 are higher than the first low frequency clock signal LC1 and the second Low frequency clock signal LC2. The first high frequency clock signal HC1, the second high frequency clock signal HC2, the third high frequency clock signal HC3, and the fourth high frequency clock signal HC4 are cyclically applied to the shift register of each stage in sequence. Clock signal. For example, the N-1th shift register can receive the fourth high frequency clock signal HC4, and the Nth stage shift register can receive the first high frequency clock signal HC1, the N+1th shift The bit buffer can receive the second high frequency clock signal HC2, the N+2 stage shift register can receive the third high frequency clock signal HC3, and the N+3 stage shift register can receive the fourth The high frequency clock signal HC4, the N+5th stage shift register can receive the first high frequency clock signal HC1.

As shown in FIG. 3, during the T1 period, the third gate signal G(n-1) is switched from the low potential to the high potential, because the third gate signal G(n-1) is transmissive through the N-1th stage. The pull-up circuit T11 _{N-1 of the} register is coupled to the control terminal of the first transistor T21 of the Nth stage shift register 200, so the capacitor 216 is charged to raise the first driving signal Q(n) to the first a high potential VH1, and according to the first transistor T21, the second transistor T22 and the third transistor T23, and the nineteenth transistor T52, the twenty-first transistor T54, the twelfth transistor T62 And the fourteenth transistor T64, further pulling down the first pull-down control signal K(n) and the second pull-down control signal P(n) to the second low potential Gn_VSS to cut off the fifteenth transistor T34, the sixteenth transistor T32, seventeenth transistor T42, eighth transistor T35, ninth transistor T33, and tenth transistor T43.

Then, in the T2 period, the third gate signal G(n-1) is switched from the high potential to the low potential, so that the pull-up circuit T11 _{N-1 of the N-} 1th stage shift register can be turned off, so the third gate The low potential of the pole signal G(n-1) cannot change the first driving signal Q(n) via the pull-up circuit of the N-1th stage shift register. At this time, the first high frequency clock signal HC1 is switched from a low potential to a high potential, and the capacitive coupling of the capacitor 216 pulls the first driving signal Q(n) from the first high potential VH1 to the second high potential VH2, which will have The high-frequency first high-frequency clock signal HC1 is output as the first gate signal G(n), and the first high-frequency clock signal HC1 having a high potential is output to the second end of the second transistor T22 to be turned on. The fourth transistor T24 and the fifth transistor T11. The first gate signal G(n) can output the second driving signal Q(n+1) to the N+1th shift register through the fifth transistor T11. The high-frequency first high-frequency clock signal HC1 outputs a sensing signal S(n) having a third high potential VH3 through the third transistor T23 and the fourth transistor T24.

4 is a schematic diagram of the drive circuit 202 of the Nth stage shift register 200 of FIG. 2 including the parasitic capacitance Cds and the load capacitance CL of the fourth transistor T24. During the T3 period, the first high frequency clock signal HC1 is switched from a high potential to a low potential, and the first driving signal Q(n) is pulled down from the second high potential VH2 to the first high potential through the capacitive coupling of the transmission capacitor 216. VH1 causes the first gate signal G(n) and the second end of the second transistor T22 to fall to a low potential to turn off the third transistor T23 and the fourth transistor T24. The fourth transistor T24 after the cutoff isolates the low-frequency first high-frequency signal HC1 and the sensing signal S(n), so the sensing signal S(n) is in a floating state and transmits through the fourth transistor. The parasitic capacitance Cds of T24 and the load capacitance CL maintain S(n) at the fourth high potential VH4. In this way, the sensing signal S(n) does not decrease to a low potential with the change of the first high frequency clock signal HC1 during the T3 period, and can be maintained at the fourth high potential VH4, and the fourth high potential VH4 can be only slightly lower. The third high potential VH3.

Until the T4 period, when the third high frequency clock signal HC3 is switched from the low potential to the high potential, the second gate signal G(n+2) is switched from the low potential to the high potential, and the sixth transistor T31 and the seventh power When the crystal T41 is turned on, the first driving signal Q(n) and the sensing signal S(n) are pulled down. The first high frequency clock signal HC1, the second high frequency clock signal HC2, the third high frequency clock signal HC3, and the fourth high frequency clock signal HC4 have the same pulse width and can be sequentially applied to the first N-level shift register 200, N+1 shift temporary storage The high frequency clock signal of the N+2 stage shift register and the N+3 stage shift register. Therefore, in this embodiment, the time when the sensing signal S(n) is maintained at a high potential is longer than the time when the first gate signal G(n) is maintained at a high potential, and the time interval of the high-frequency clock signal is wide, but the present invention Without being limited thereto, it is within the scope of the invention to output two or more output signals having different pulse widths.

In the above embodiment, the time during which the sensing signal S(n) is maintained at a high potential is longer than the time at which the first gate signal G(n) is maintained at a high potential. Therefore, the driving circuit 202 of the Nth stage shift register integrated in the light sensing touch display panel can output two output signals with different pulse widths, that is, the sensing signals S(n) having different pulse widths and the first gate. The extreme signal G(n) is used to provide a light-sensitive touch display panel.

FIG. 5 is a schematic diagram of an Nth stage shift register 500 according to another embodiment of the present invention. In FIG. 5, only the layout position of the pull-up circuit 510 is different from that of FIG. 2, that is, the fifth transistor T11 of the pull-up circuit 510 has a control terminal for receiving the third gate signal G(n-1). The first end of the control end of the first transistor T21 is coupled to the second end of the control end of the first transistor T21. In this embodiment, the third gate signal G(n-1) is coupled to the first transistor T21 of the Nth stage shift register 200 through the pull-up circuit T11 of the Nth stage shift register. The control terminal is configured to provide a first driving signal Q(n) of the Nth stage shift register 200. The driving circuit 202 of the remaining Nth stage shift register 500, the first pull-down circuit 204, the first pull-down control circuit 206, the main pull-down circuit 208, the second pull-down circuit 212, the second pull-down control circuit 214, and the capacitor 216 The structure, working mode and signal output are similar to those described in Figures 2 to 4 and the previous embodiment. Said.

FIG. 6 is a schematic diagram of an Nth stage shift register 600 according to another embodiment of the present invention. The driving circuit 202 of the Nth stage shift register 600, the first pull-down circuit 204, the first pull-down control circuit 206, the main pull-down circuit 208, the second pull-down circuit 212, the second pull-down control circuit 214, and the capacitor 216 The structure and working principle are similar to those in Figure 2 and will not be described again. The pull-up circuit 610 of FIG. 6 is coupled to the driving circuit 202 for simultaneously providing the second driving signal Q(n+1) and the third driving signal Q(n-1) according to the first driving signal Q(n). The drive circuit of the other two-stage shift register (which may be the N+1th shift register and the N-1th shift register). The secondary pull-down circuit 618 of FIG. 6 is also coupled to the driving circuit 202 for pulling down according to the fourth gate signal G(n-2) (which can be the gate signal from the N-2 stage shift register) The first driving signal Q(n), the first gate signal G(n), and the sensing signal S(n).

The pull-up circuit 610 includes a fifth transistor T11 and a twenty-second transistor T13. The secondary pull-down circuit 618 includes a twenty-third transistor T36 and a twenty-fourth transistor T45. In this embodiment, the fifth transistor T11 has a control end coupled to the second end of the second transistor T22, coupled to the first end of the control end of the fifth transistor T11, and configured to provide a second driving signal ( The second end of Qn+1). The second transistor T13 has a control end coupled to the control end of the fifth transistor T11, coupled to the first end of the first end of the fifth transistor T11, and configured to provide a third driving signal Q(n) The second end of -1). The twenty-third transistor T36 has a control terminal for receiving the fourth gate signal G(n-2), a first end coupled to the second end of the fourth transistor T24, and a first low potential for receiving Second of Sn_VSS end. The twenty-fourth transistor T45 has a control end coupled to the control end of the thirteenth transistor T36, a first end coupled to the control end of the first transistor T22, and a second terminal for receiving the second low potential Gn_VSS Two ends.

The main pull-down circuit 208 and the second pull-down circuit 618 of FIG. 6 can pull down the first driving signal Q(n) according to the second gate signal G(n+2) and the fourth gate signal G(n-2), respectively. a gate signal G(n) and a sensing signal S(n), that is, the Nth stage shift register can be controlled by the gate signal of the N+2 stage or the N-2 stage shift register Signal output time. When the driving circuit 202 of FIG. 6 outputs the first high frequency clock signal HC1 having a high potential to the second end of the second transistor T22 to turn on the fifth transistor T11 and the twelfth transistor T13, The high potential of the high frequency clock signal HC1 can simultaneously output the second driving signal Q(n+1) to the N+1th shift register through the fifth transistor T11 and output through the twenty second transistor T13. The third driving signal Q(n-1) to the N-1th stage shift register, so the Nth stage shift register 600 of FIG. 6 can simultaneously drive the N-1th stage and the N+1th stage. Shift register. The Nth stage shift register 600 can control the shift register to transfer signals to the upper level or the lower level to achieve the bi-directionals function if the appropriate timing signal is matched. Moreover, since the driving circuit 202 of the Nth stage shift register 600 works similarly to FIG. 2, the Nth stage shift register 600 can simultaneously output two output signals having different pulse widths, that is, the pulse widths are different. The sensing signal S(n) and the first gate signal G(n) are applied to the light sensing touch display panel.

FIG. 7 is a schematic diagram of an Nth stage shift register 700 according to another embodiment of the present invention. The driving circuit 202 of the Nth stage shift register 700, the first pull-down circuit 204, and the first The structure and working principle of the pull-down control circuit 206, the main pull-down circuit 208, the second pull-down circuit 212, the second pull-down control circuit 214, the capacitor 216, and the secondary pull-down circuit 618 are similar to those of FIG. 6, and will not be described again. The pull-up circuit 710 of FIG. 7 is coupled to the driving circuit 202 for simultaneously providing the second driving signal Q(n+1) and the third driving signal Q(n-1) according to the first driving signal Q(n). The drive circuit of the other two-stage shift register (which may be the N+1th shift register and the N-1th shift register).

The pull-up circuit 710 includes a fifth transistor T11 and a twenty-second transistor T13. In this embodiment, the fifth transistor T11 has a control end coupled to the second end of the second transistor T22, coupled to the first end of the second end of the first transistor T21, and configured to provide the second driving signal. The second end of (Qn+1). The second transistor T13 has a control end coupled to the control end of the fifth transistor T11, coupled to the first end of the first end of the fifth transistor T11, and configured to provide a third driving signal Q(n) The second end of -1).

The main pull-down circuit 208 and the second pull-down circuit 618 of FIG. 7 can pull down the first driving signal Q(n) according to the second gate signal G(n+2) and the fourth gate signal G(n-2), respectively. a gate signal G(n) and a sensing signal S(n), that is, the Nth stage shift register can be controlled by the gate signal of the N+2 stage or the N-2 stage shift register Signal output time. When the driving circuit 202 of FIG. 7 outputs the first high frequency clock signal HC1 having a high potential as the first gate signal G(n), and outputs the first high frequency clock signal HC1 having a high potential to the first When the second end of the second transistor T22 turns on the fifth transistor T11 and the twelfth transistor T13, the first gate signal G(n) having a high potential can simultaneously output the second driver through the fifth transistor T11. Signal Q(n+1) to N+1th shift register and pass through The twelfth transistor T13 outputs the third driving signal Q(n-1) to the N-1th stage shift register, so the Nth stage shift register 700 of FIG. 7 can simultaneously drive the Nth- Level 1 and No. 1+1 shift register. The Nth stage shift register 700 can control the shift register to transfer the gate signal to the upper stage or the lower stage to achieve the bi-directions function if the appropriate timing signal is controlled. Moreover, since the driving principle of the driving circuit 202 of the Nth stage shift register 700 is similar to that of FIG. 2, the Nth stage shift register 700 can simultaneously output two output signals having different pulse widths, that is, the pulse widths are different. The sensing signal S(n) and the first gate signal G(n) are applied to the light sensing touch display panel.

The difference between the effect of using the pull-up circuit 610 of FIG. 6 and the pull-up circuit 710 of FIG. 7 is that when the second gate signal G(n+2) or the fourth gate signal G(n-2) pulls down the first driver When the signal Q(n) is used, the structure of the pull-up circuit 710 can reduce the coupling of the second driving signal Q(n+1) to the first driving signal Q(n), and reduce the influence on the waveform of the first driving signal Q(n). .

FIG. 8 is a schematic diagram of an Nth stage shift register 800 according to another embodiment of the present invention. The structure and working principle of the first pull-down circuit 204, the first pull-down control circuit 206, the second pull-down circuit 212, the second pull-down control circuit 214, and the capacitor 216 of the Nth stage shift register 800 are similar to those of FIG. ,No longer. The pull-up circuit 810 of FIG. 8 is coupled to the driving circuit 802 for providing the second driving signal Q(n+1) to the N+1th shift register according to the first driving signal Q(n). Drive circuit.

The driving circuit 802 of FIG. 8 is similar to the driving circuit 202 of FIG. 2, except that the driving circuit 802 does not include the fourth transistor T24 but the third transistor T23. The two ends output the sensing signal S(n), and the first end of the third transistor T23 is used to receive the DC high potential VGH. The main pull-down circuit 808 of FIG. 8 is coupled to the driving circuit 802. The main pull-down circuit 808 of FIG. 8 is different from the main pull-down circuit 208 of FIG. 2 in that the control terminal of the seventh transistor T41 of the main pull-down circuit 808 receives the second. The gate signal G(n+2), the control end of the sixth transistor T31 receives the fifth gate signal G(n+3) (which may be the gate signal from the N+3 stage), and according to the second The gate signal G(n+2) pulls down the first driving signal Q(n) and pulls down the sensing signal S(n) according to the fifth gate signal G(n+3). The pull-up circuit 810 includes a fifth transistor T11 in a similar manner to the pull-up circuit 202.

FIG. 9 is a schematic diagram of an Nth stage shift register 900 according to another embodiment of the present invention. The structure and working principle of the first pull-down circuit 204, the first pull-down control circuit 206, the second pull-down circuit 212, the second pull-down control circuit 214, the pull-up circuit 510 and the capacitor 216 of the Nth stage shift register 900 Similar to Figure 5, no longer repeat them.

The driving circuit 902 of FIG. 9 is similar to the driving circuit 202 of FIG. 5, except that the driving circuit 902 does not include the second transistor T22 and the fourth transistor T24, but is outputted by the second end of the third transistor T23. The signal signal S(n), and the first end of the third transistor T23 is used to receive the DC high potential VGH. The main pull-down circuit 908 of FIG. 9 differs from the main pull-down circuit 208 of FIG. 5 in that the control terminals of the sixth transistor T31 and the seventh transistor T41 of the main pull-down circuit 908 receive the fifth gate signal G(n+3). And pulling down the first driving signal Q(n) and the sensing signal S(n) according to the fifth gate signal G(n+3).

Figure 10 is a diagram showing the operation related signal waveform of the Nth stage shift register 800 of Fig. 8. schematic diagram. The principle of Fig. 10 is similar to that of Fig. 3, and only the differences are explained below. During the period T1, since the first end of the third transistor T23 is coupled to the relatively stable DC high potential VGH, when the first driving signal Q(n) rises to the first high potential VH1, the sensing signal S(n) ) can be pre-charged. Therefore, when the first driving signal Q(n) is pulled up from the first high potential VH1 to the second high potential VH2 in the T2 period, the sensing signal S(n) is ensured to be pulled up to the third high potential of FIG. VH3 is closer to the potential of the high DC high potential VGH, and the T3 period ends. When the first driving signal Q(n) is pulled down to the low potential, the sensing signal S(n) does not follow the first high frequency clock signal HC1. Variety. Moreover, since the sixth transistor T31 of the Nth stage shift register 800 pulls down the sensing signal S(n) according to the fifth gate signal G(n+3), the sensing signal S(n) of FIG. 10 After the end of the T4 period, the fifth gate signal G(n+3) rises to a high level before being pulled down, and has a longer pulse width than the sensing signal S(n) of FIG. The above can increase the driving capability of the sensing signal S(n) and can be applied to a large-sized panel.

In the embodiment of the invention, a shift register capable of transmitting one-way or two-way signals is integrated in a gate driving circuit of the light-sensitive touch panel, and the N-th shift register can generate two different pulse widths. The output signal is used to provide the signals required for the optically-sensitive touch display panel, and does not require an external drive chip, thereby reducing the manufacturing process of the light-sensitive touch display panel and improving the integration, reducing the number of processes and reducing the manufacturing cost.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Shift register

110‧‧‧ pixel array

102‧‧‧N-1 stage shift register

104, 200, 500, 600, 700, 800, 900‧‧‧Nth level shift register

106‧‧‧N+1 level shift register

202, 802, 902‧‧‧ drive circuit

204‧‧‧First pull-down circuit

206‧‧‧First pull-down control circuit

208, 808, 908‧‧‧ main pull-down circuit

618‧‧ ‧ pulldown circuit

210, 510, 610, 710, 810‧‧‧ pull-up circuits

212‧‧‧Second pull-down circuit

214‧‧‧Second pull-down control circuit

216‧‧‧ Capacitance

Q(n)‧‧‧First drive signal

Q(n+1)‧‧‧second drive signal

Q(n-1)‧‧‧third drive signal

G(n)‧‧‧ first gate signal

G(n+2)‧‧‧second gate signal

G(n-1)‧‧‧3rd gate signal

G(n-2)‧‧‧fourth gate signal

G(n+3)‧‧‧ fifth gate signal

S(n)‧‧‧Sense signal

SG(n-1)‧‧‧N-1 level gate signal

SG(n)‧‧‧Nth level gate signal

SG(n+1)‧‧‧N+1 level gate signal

K(n)‧‧‧First pulldown control signal

P(n)‧‧‧Second Pulldown Control

HC1‧‧‧ first high frequency clock signal

HC2‧‧‧Second high frequency clock signal

HC3‧‧‧ third high frequency clock signal

HC4‧‧‧ fourth high frequency clock signal

LC1‧‧‧ first low frequency clock signal

LC2‧‧‧ second low frequency clock signal

Sn_VSS‧‧‧ first low potential

Gn_VSS‧‧‧ second low potential

VH1‧‧‧ first high potential

VH2‧‧‧ second high potential

VH3‧‧‧ third high potential

VH4‧‧‧ fourth high potential

Cds‧‧‧ parasitic capacitance

CL‧‧‧ load capacitance

T‧‧‧ timeline

T1, T2, T3, T4‧‧‧

T11, T13, T21-T24, T31-T36, T41-T43, T45, T51-T54, T61-T64, T11 _N-1 ‧‧‧O crystal

Figure 1 is a schematic diagram of a shift register and a pixel array of a display panel.

FIG. 2 is a schematic diagram of an Nth stage shift register according to an embodiment of the present invention.

Figure 3 is a schematic diagram showing the waveforms of the operation related signals of the Nth stage shift register of Fig. 2.

Fig. 4 is a schematic diagram showing the driving circuit of the Nth stage shift register of Fig. 2 including the parasitic capacitance and the load capacitance of the fourth transistor.

FIG. 5 is a schematic diagram of an Nth stage shift register according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of an Nth stage shift register according to another embodiment of the present invention.

FIG. 7 is a schematic diagram of an Nth stage shift register according to another embodiment of the present invention.

FIG. 8 is a schematic diagram of an Nth stage shift register according to another embodiment of the present invention.

FIG. 9 is a schematic diagram of an Nth stage shift register according to another embodiment of the present invention.

Figure 10 is a schematic diagram showing the waveforms of the operation related signals of the Nth stage shift register of Fig. 8.

200‧‧‧N-level shift register

202‧‧‧ drive circuit

204‧‧‧First pull-down circuit

206‧‧‧First pull-down control circuit

208‧‧‧Main pull-down circuit

210‧‧‧ Pull-up circuit

212‧‧‧Second pull-down circuit

214‧‧‧Second pull-down control circuit

216‧‧‧ Capacitance

Q(n)‧‧‧First drive signal

Q(n+1)‧‧‧second drive signal

G(n)‧‧‧ first gate signal

G(n+2)‧‧‧second gate signal

G(n-1)‧‧‧3rd gate signal

S(n)‧‧‧Sense signal

K(n)‧‧‧First pulldown control signal

P(n)‧‧‧Second Pulldown Control

HC1‧‧‧ high frequency clock signal

LC1‧‧‧ first low frequency clock signal

LC2‧‧‧ second low frequency clock signal

Sn_VSS‧‧‧ first low potential

Gn_VSS‧‧‧ second low potential

T11, T21-T24, T31-T35, T41-T43, T51-T54, T61-T64, T11 _N-1 ‧‧‧O crystal

Claims (22)

An N-th stage shift register for providing an output signal of two different pulse widths for use in a light-sensitive touch panel includes: a driving circuit comprising: a first transistor having a first receiving transistor a control terminal of the first driving signal, a first end for receiving a high frequency clock signal, and a second end for providing a first gate signal; a second transistor having a coupling a control end of the control end of the first transistor, a first end coupled to the first end of the first transistor, and a second end; a third transistor having a first electrical coupling a control end of the control end of the crystal, a first end coupled to the first end of the first transistor, and a second end; and a fourth transistor having a first transistor coupled to the second transistor a second end of the control terminal, a first end coupled to the second end of the third transistor, and a second end for providing a sensing signal; and a first pull-down circuit coupled to the driving circuit For pulling down the first gate signal and the sensing signal; wherein N is a positive integer and the first gate signal and Pulse width sensing signal dissimilar. The Nth stage shift register according to claim 1, further comprising: a pull-up circuit coupled to the driving circuit; a main pull-down circuit coupled to the driving circuit; and a first pull-down control circuit coupled to the first pull-down circuit for generating a signal according to the first driving signal and a first low-frequency clock signal The first pull-down control signal controls the operation of the first pull-down circuit. The Nth stage shift register of claim 2, wherein the main pull-down circuit is coupled to the control end of the first transistor and the second end of the fourth transistor for The second gate signal is pulled down to the potential of the control terminal of the first transistor and the potential of the second terminal of the fourth transistor; and the first pull-down circuit is coupled to the control terminal of the first transistor, the first The second end of the crystal and the second end of the fourth transistor are configured to pull down the potential of the control end of the first transistor, the potential of the second end of the first transistor, and the first according to the first pull-down control signal The potential of the second end of the four transistors. The Nth stage shift register according to claim 3, wherein the pull-up circuit includes a fifth transistor having a control terminal for receiving a third gate signal, and a fifth coupled to the fifth a first end of the control end of the transistor, and a second end coupled to the control end of the first transistor. The Nth stage shift register according to claim 3, further comprising a capacitor coupled between the control end of the first transistor and the second end of the first transistor. The Nth stage shift register as claimed in claim 3, wherein the main pull-down circuit comprises: a sixth transistor having a control terminal for receiving the second gate signal, a first end coupled to the second end of the fourth transistor, and a first terminal for receiving a first low potential And a seventh transistor; and a seventh transistor having a control end coupled to the control end of the sixth transistor, a first end coupled to the control end of the first transistor, and a second end for receiving a second transistor a second end of the low potential; wherein the first low potential is higher than the second low potential. The Nth stage shift register according to claim 3, wherein the first pull-down circuit comprises: an eighth transistor having a control end for receiving the first pull-down control signal, and a coupling a first end of the second end of the fourth transistor, and a second end for receiving a first low potential; a ninth transistor having a control end coupled to the control end of the eighth transistor a first end coupled to the second end of the first transistor, and a second end for receiving a second low potential; and a tenth transistor having a first transistor coupled to the eighth transistor a control end of the control terminal, and a first end coupled to the control end of the first transistor; wherein the first low potential system is higher than the second low potential. The Nth stage shift register of claim 7, wherein the second end of the tenth transistor is coupled to the second end of the first transistor or the second end of the ninth transistor. The Nth stage shift register according to claim 7, wherein the first pull-down control circuit comprises: an eleventh transistor having a control end for receiving the first low frequency clock signal, a first end coupled to the control end of the eleventh transistor, and a second end; a twelfth transistor having a control end for receiving the first driving signal, and a coupling end a first end of the second end of the transistor, and a second end coupled to the second end of the ninth transistor; a thirteenth transistor having a second coupled to the eleventh transistor a control end coupled to the first end of the control end of the eleventh transistor, and a second end coupled to the control end of the eighth transistor; and a fourteenth transistor having a coupling The first end of the second end of the thirteenth transistor is coupled to the second end of the second end of the ninth transistor, and the second end of the second end of the ninth transistor. The Nth stage shift register according to claim 3, further comprising: a second pull-down circuit coupled to the control end of the first transistor, the second end of the first transistor, and the fourth a second end of the transistor, configured to pull down a potential of the control end of the first transistor, a potential of the second end of the first transistor, and a potential of the second end of the fourth transistor according to a second pull-down control signal; and a second pull-down control circuit is coupled to the second pull-down circuit for generating the second pull-down control according to the first driving signal and a second low-frequency clock signal Signal. The Nth stage shift register according to claim 10, wherein the second pull-down circuit comprises: a fifteenth transistor having a control end for receiving the second pull-down control signal, and a coupling a first end of the second end of the fourth transistor, and a second end for receiving a first low potential; a sixteenth transistor having a control coupled to the control end of the fifteenth transistor a first end coupled to the second end of the first transistor, and a second end for receiving a second low potential; and a seventeenth transistor having a coupling to the tenth a control terminal of the control terminal of the fifth transistor, and a first terminal coupled to the control terminal of the first transistor; wherein the first low potential system is higher than the second low potential. The Nth stage shift register of claim 11, wherein the second end of the seventeenth transistor is coupled to the second end of the first transistor or the second end of the sixteenth transistor end. The Nth stage shift register according to claim 11, wherein the second pull-down control circuit comprises: an eighteenth transistor having a control end for receiving the second low frequency clock signal, a coupling a first end connected to the control end of the eighteenth transistor, and a second end; a nineteenth transistor having a control terminal for receiving the first driving signal, a first end coupled to the second end of the eighteenth transistor, and a coupling to the sixteenth transistor a second end of the second end; a twentieth transistor having a control end coupled to the second end of the eighteenth transistor, and a first end coupled to the control end of the eighteenth transistor And a second end coupled to the control end of the fifteenth transistor; and a second eleven transistor having a control end coupled to the control end of the nineteenth transistor, coupled to the first a first end of the second end of the twenty-first transistor, and a second end coupled to the second end of the sixteenth transistor. The Nth stage shift register according to claim 3, wherein the pull-up circuit includes a fifth transistor having a control end coupled to the second end of the second transistor, and coupled to the a first end of the second end of the first transistor, and a second end for providing a second driving signal. The Nth stage shift register according to claim 14, wherein the pull-up circuit further comprises a second twelve transistor having a control end coupled to the control end of the fifth transistor, a coupling a first end of the first end of the fifth transistor, and a second end for providing a third driving signal. The Nth stage shift register of claim 15, wherein the first end of the fifth transistor is coupled to the control end of the fifth transistor. The Nth stage shift register according to claim 3, further comprising a pull-down circuit coupled to the control end of the first transistor and the second end of the fourth transistor for use according to a fourth The gate signal pulls down the potential of the control terminal of the first transistor and the potential of the second terminal of the fourth transistor. The Nth stage shift register according to claim 17, wherein the pull-down circuit comprises: a twenty-third transistor having a control terminal for receiving the fourth gate signal, and a coupling end a first end of the second end of the fourth transistor, and a second end for receiving a first low potential; and a second fourteen transistor having a second semiconductor transistor coupled thereto a control end of the control terminal, a first end coupled to the control end of the first transistor, and a second end configured to receive a second low potential; wherein the first low potential system is higher than the second low potential . An N-th stage shift register for providing an output signal of two different pulse widths for use in a light-sensitive touch panel includes: a driving circuit comprising: a first transistor having a first receiving transistor a control terminal of the first driving signal, a first end for receiving a high frequency clock signal, and a second end for providing a first gate signal; a second transistor having a coupling a control end of the control end of the first transistor, coupled to the first end of the first end of the first transistor, and a second end; and a third transistor having a control end coupled to the control end of the first transistor, coupled to the first end of the high current potential, and a signal for providing a sensing signal The second end of the first transistor; And a second terminal for providing a second driving signal; a main pull-down circuit coupled to the driving circuit; and a first pull-down circuit coupled to the driving circuit and the control of the first transistor The second end of the first transistor and the second end of the third transistor are configured to pull down the potential of the control end of the first transistor according to the first pull-down control signal, and the first transistor The potential of the two ends and the potential of the second end of the third transistor; wherein N is a positive integer and the pulse widths of the first gate signal and the sensing signal are different. The Nth stage shift register of claim 19, wherein the main pull-down circuit is coupled to the control end of the first transistor and the second end of the third transistor for The gate signal pulls down the potential of the control terminal of the first transistor and pulls down the potential of the second terminal of the third transistor according to a fifth gate signal. An N-th stage shift register capable of providing two different pulse width output signals for use in a light-sensitive touch panel, comprising: A driving circuit includes: a first transistor having a control terminal for receiving a first driving signal, a first terminal for receiving a high frequency clock signal, and a first gate for providing a first gate a second end of the pole signal; a third transistor having a control end coupled to the control end of the first transistor, a first end coupled to the high current potential, and a first sensing terminal a second end of the signal; a pull-up circuit comprising a fifth transistor having a control terminal for receiving a third gate signal, a first end coupled to the control terminal of the fifth transistor, and a second end connected to the control end of the first transistor; a main pull-down circuit coupled to the driving circuit; and a first pull-down circuit coupled to the driving circuit and the control end of the first transistor The second end of the first transistor and the second end of the third transistor are configured to pull down the potential of the control end of the first transistor, the second of the first transistor according to the first pull-down control signal a potential of the terminal and a potential of the second terminal of the third transistor; wherein N is a positive integer and the The pulse width of the first gate signal and the sensing signal are different. The Nth stage shift register of claim 21, wherein the main pull-down circuit is coupled to the control end of the first transistor and the second end of the third transistor for The gate signal pulls down the potential of the control terminal of the first transistor and the potential of the second terminal of the third transistor.