CN103680450A - Drive circuit capable of achieving two-way transmission of signals and shifting register thereof - Google Patents
Drive circuit capable of achieving two-way transmission of signals and shifting register thereof Download PDFInfo
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- CN103680450A CN103680450A CN201310697800.9A CN201310697800A CN103680450A CN 103680450 A CN103680450 A CN 103680450A CN 201310697800 A CN201310697800 A CN 201310697800A CN 103680450 A CN103680450 A CN 103680450A
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Abstract
The invention provides a drive circuit capable of achieving two-way transmission of signals and a shifting register thereof. The drive circuit comprises a first transistor, a second transistor and a third transistor, wherein the first end of the first transistor is electrically connected with the (n-2)th grid drive terminal, the control end of the first transistor is electrically connected with the (n-4)th control terminal, the first end of the second transistor is electrically connected with the second end of the first transistor to form a common node, the second end of the second transistor is electrically connected with the (n+2)th grid drive terminal, the control end of the second transistor is electrically connected with the (n+4)th control terminal, the first end of the third transistor receives a high frequency clock pulse signal, the second end of the third transistor is electrically connected with the nth grid drive terminal, and the control end of the third transistor is electrically coupled to the second end of the first transistor. Accordingly, the second transistor has charging and discharging functions at the same time by means of two-stage potential voltage of the common node, and therefore two-way transmission of signals is achieved. Compared with the prior art, the drive circuit is simple in structure and smaller in layout area.
Description
Technical field
The present invention relates to a kind of driving circuit, relate in particular to a kind of driving circuit of the signal the realized transmitted in both directions for the capable driving of array base palte (Gate driver On Array, GOA) panel and the shift register that comprises this driving circuit.
Background technology
At Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-LCD) in, each pixel has a thin film transistor (TFT) (Thin Film Transistor, TFT), the grid of this thin film transistor (TFT) is electrically connected to the sweep trace of horizontal direction, drain electrode is electrically connected to the data line of vertical direction, and source electrode is electrically connected to a pixel electrode.If a certain sweep trace in the horizontal direction applies enough positive voltages, can make all TFT on this sweep trace open, the pixel electrode that now this sweep trace is corresponding can be connected with the data line of vertical direction, thereby by the video signal voltage writing pixel of data line, and then the penetrability of controlling different liquid crystal is to reach the effect of controlling color.
Current, existing a lot of driving circuits are mainly for example, to be completed by the outer gluing integrated circuit (, grid drive IC or source drive IC) of liquid crystal panel.By contrast, the capable driving of array base palte (Gate driver On Array, GOA) technology is directly the gate driver circuit of thin film transistor (TFT) to be produced on array base palte, with the driving chip that replaces being made by external silicon.Because GOA circuit can directly be made in around liquid crystal panel, not only simplify making technology, but also can reduce cost of products, improve the integrated level of TFT-LCD panel, make panel trend towards slimming more.
In order to realize the signal transmitted in both directions in driving circuit, a solution of the prior art is to be, the gate driver circuit of GOA sees through symmetrical circuit framework makes the signal transmission in circuit possess two-way function.Although this circuit does not need extra signal just can reach the object of transmitted in both directions, circuit framework is comparatively complicated, makes circuit possess the extra fabric swatch area of transmitted in both directions function too much, this by significant adverse in the narrow typeization design of frame.In addition, the gate drive signal of this circuit output cannot be charged to expectancy wave at short notice smoothly, causes signal can not be sent to the afterbody of shift register at all undistortedly.
In view of this, how designing a kind of driving circuit of the GOA of being applicable to panel or existing driving circuit is improved, to improve or to eliminate above-mentioned defect and deficiency, is a person skilled problem urgently to be resolved hurrily in the industry.
Summary of the invention
For driving circuit existing above-mentioned defect when realizing signal transmitted in both directions of prior art, the invention provides the driving circuit of the signal the realized transmitted in both directions that a kind of circuit framework is simplified, circuit layout area is less and the shift register that comprises this driving circuit.
According to one aspect of the present invention, a kind of driving circuit of realizing signal transmitted in both directions is provided, be suitable for array basal plate row and drive panel, this driving circuit comprises:
One the first transistor, has control end, first end and the second end, and the first end of described the first transistor is electrically connected (n-2) individual grid drive terminal, and the control end of described the first transistor is electrically connected (n-4) individual control terminal;
One transistor seconds, there is control end, first end and the second end, the first end of described transistor seconds is electrically connected the second end of described the first transistor to form a common node, the second end of described transistor seconds is electrically connected (n+2) individual grid drive terminal, and the control end of described transistor seconds is electrically connected (n+4) individual control terminal; And
One the 3rd transistor, there is control end, first end and the second end, described the 3rd transistorized first end receives a high-frequency clock pulse signal, described the 3rd transistorized the second end is electrically connected n grid drive terminal, described the 3rd transistorized control end is electrically coupled to the second end of described the first transistor and the first end of described transistor seconds
Wherein, described driving circuit makes described the first transistor and described transistor seconds possess charge and discharge function by two stage potential voltages of described common node simultaneously, thereby realizes signal transmitted in both directions.
In an embodiment therein, this driving circuit also comprises an electric capacity, one end of described electric capacity is electrically connected to the second end of described the first transistor and the first end of described transistor seconds, and the other end of described electric capacity is electrically connected to described the 3rd transistorized the second end.
In an embodiment therein, when (n-4) individual control terminal is noble potential and (n+4) individual control terminal while being electronegative potential, described the first transistor conducting and described transistor seconds turn-off.Preferably, when (n-2) individual grid drive terminal is noble potential, the voltage of described common node is noble potential, thereby described the 3rd transistor turns is charged to described n grid drive terminal by the described high-frequency clock pulse signal of noble potential.
In an embodiment therein, when (n+4) individual control terminal is noble potential and (n-4) individual control terminal while being electronegative potential, described the first transistor turn-offs and described transistor seconds conducting.Preferably, when (n+2) individual grid drive terminal is noble potential, the voltage of described common node is noble potential, thereby described the 3rd transistor turns is discharged to described n grid drive terminal by the described high-frequency clock pulse signal of electronegative potential.
According to another aspect of the present invention, a kind of shift register is provided, be suitable for array basal plate row and drive panel, this shift register comprises:
One first drop-down unit, in order to receive one first low-frequency clock pulse signal and a n control terminal, and exports n grid drive terminal;
One second drop-down unit, in order to receive one second low-frequency clock pulse signal and a n control terminal, and exports n grid drive terminal, and the phase place of described the second low-frequency clock pulse signal is different from the phase place of described the first low-frequency clock pulse signal; And
One drive circuit, comprising:
One the first transistor, has control end, first end and the second end, and the first end of described the first transistor is electrically connected (n-2) individual grid drive terminal, and the control end of described the first transistor is electrically connected (n-4) individual control terminal;
One transistor seconds, there is control end, first end and the second end, the first end of described transistor seconds is electrically connected to the second end of described the first transistor to form a common node, the second end of described transistor seconds is electrically connected (n+2) individual grid drive terminal, and the control end of described transistor seconds is electrically connected (n+4) individual control terminal; And
One the 3rd transistor, there is control end, first end and the second end, described the 3rd transistorized first end receives a high-frequency clock pulse signal, described the 3rd transistorized the second end is electrically connected n grid drive terminal, described the 3rd transistorized control end is electrically coupled to the second end of described the first transistor and the first end of described transistor seconds, wherein, described driving circuit makes described the first transistor and transistor seconds possess charge and discharge function by two stage potential voltages of described common node simultaneously, thereby realizes signal transmitted in both directions.
In an embodiment therein, described the first drop-down unit and described the second drop-down unit include pull-down control circuit and the pull-down circuit of cascade, wherein, described pull-down control circuit receives low-frequency clock pulse signal and from the signal of described n control terminal, and described pull-down circuit is electrically connected extremely described n grid drive terminal of the output terminal of described pull-down control circuit and output drive signal.
In an embodiment therein, described pull-down control circuit comprises: one the 4th transistor, there is control end, first end and the second end, and described the 4th transistorized first end is connected with control end and in order to receive described low-frequency clock pulse signal; One the 5th transistor, there is control end, first end and the second end, described the 5th transistorized first end is electrically connected to described the 4th transistorized the second end, described the 5th transistorized control end is electrically connected described n control terminal, and described the 5th transistorized the second end is electrically connected to a threshold voltage; One the 6th transistor, has control end, first end and the second end, and described the 6th transistorized first end is electrically connected to described the 4th transistorized first end, and described the 6th transistorized control end is electrically connected to described the 4th transistorized the second end; And one the 7th transistor, there is control end, first end and the second end, described the 7th transistorized first end is electrically connected to described the 6th transistorized the second end, described the 7th transistorized control end is electrically connected described n control terminal, and described the 7th transistorized the second end is electrically connected to described threshold voltage; Described pull-down circuit comprises: one the 8th transistor, there is control end, first end and the second end, described the 8th transistorized first end is electrically connected to described common node, described the 8th transistorized control end is electrically connected to described the 6th transistorized the second end and described the 7th transistorized first end, and described the 8th transistorized the second end is electrically connected to n grid drive terminal; And one the 9th transistor, there is control end, first end and the second end, described the 9th transistorized first end is electrically connected to n grid drive terminal, described the 9th transistorized control end is electrically connected to described the 6th transistorized the second end and described the 7th transistorized first end, and described the 9th transistorized the second end is electrically connected to described threshold voltage.
According to another aspect of the present invention, a kind of shift register is provided, be suitable for array basal plate row and drive panel, this shift register comprises:
One drive circuit, comprising:
One the first transistor, has control end, first end and the second end, and the first end of described the first transistor is electrically connected (n-2) individual grid drive terminal, and the control end of described the first transistor is electrically connected (n-4) individual control terminal;
One transistor seconds, there is control end, first end and the second end, the first end of described transistor seconds is electrically connected to the second end of described the first transistor to form a common node, the second end of described transistor seconds is electrically connected (n+2) individual grid drive terminal, and the control end of described transistor seconds is electrically connected (n+4) individual control terminal; And
One the 3rd transistor, there is control end, first end and the second end, described the 3rd transistorized first end receives a high-frequency clock pulse signal, described the 3rd transistorized the second end is electrically connected n grid drive terminal, described the 3rd transistorized control end is electrically coupled to the second end of described the first transistor and the first end of described transistor seconds, wherein, described driving circuit makes described the first transistor and transistor seconds possess charge and discharge function by two stage potential voltages of described common node simultaneously, thereby realizes signal transmitted in both directions; And
One drop-down unit, comprising:
One the 4th transistor, there is control end, first end and the second end, described the 4th transistorized control end is electrically connected n control terminal, described the 4th transistorized first end is connected to described high-frequency clock pulse signal by an electric capacity, and described the 4th transistorized the second end is electrically connected to a threshold voltage;
One the 5th transistor, there is control end, first end and the second end, described the 5th transistorized control end is electrically connected to described the 4th transistorized first end, described the 5th transistorized first end is electrically connected to described common node, and described the 5th transistorized the second end is electrically connected to described threshold voltage;
One the 6th transistor, there is control end, first end and the second end, described the 6th transistorized first end is electrically connected to described the 3rd transistorized the second end, described the 6th transistorized control end is electrically connected to described the 4th transistorized first end, and described the 6th transistorized the second end is electrically connected to described threshold voltage; And
One the 7th transistor, there is control end, first end and the second end, described the 7th transistorized first end is electrically connected to described the 3rd transistorized the second end, described the 7th transistorized the second end is electrically connected to described threshold voltage, and described the 7th transistorized control end is in order to receive another high-frequency clock pulse signal.
Adopt driving circuit and the shift register thereof of realizing signal transmitted in both directions of the present invention, the first end of the first transistor is electrically connected (n-2) individual grid drive terminal and control end is electrically connected (n-4) individual control terminal, the first end of transistor seconds is electrically connected the second end of the first transistor to form a common node, the second end of transistor seconds is electrically connected (n+2) individual grid drive terminal, the control end of transistor seconds is electrically connected (n+4) individual control terminal, the two stage potential voltages by this common node make the first transistor and transistor seconds possess charge and discharge function simultaneously, thereby realize signal transmitted in both directions.Than prior art, GOA circuit framework of the present invention does not need extra signal just can reach the function of signal bi-directional, and the balancing waveform that this driving circuit can see through common node potential voltage utilizes the 3rd transistor to increase the discharge capacity of gate drive signal, not only circuit framework is simple, and circuit layout area still less.
Accompanying drawing explanation
Reader, after having read the specific embodiment of the present invention with reference to accompanying drawing, will become apparent various aspects of the present invention.Wherein,
Fig. 1 illustrates a kind of circuit structure diagram of realizing the driving circuit of signal transmitted in both directions of the prior art;
Fig. 2 illustrates the circuit structure diagram according to the driving circuit of the signal the realized transmitted in both directions of an embodiment of the present invention;
Fig. 3 illustrates the specific embodiment of circuit framework of the drop-down unit with pull-down control circuit and pull-down circuit of Fig. 2;
Fig. 4 illustrates the timing waveform schematic diagram of the key signal in the driving circuit of the signal realized transmitted in both directions of Fig. 2; And
Fig. 5 illustrates the circuit structure diagram according to the driving circuit of the signal the realized transmitted in both directions of another embodiment of the present invention.
Embodiment
For the technology contents that the application is disclosed is more detailed and complete, can be with reference to accompanying drawing and following various specific embodiments of the present invention, in accompanying drawing, identical mark represents same or analogous assembly.Yet those of ordinary skill in the art should be appreciated that the embodiment that hereinafter provided is not used for limiting the scope that the present invention is contained.In addition, accompanying drawing, only for being schematically illustrated, is not drawn according to its life size.
With reference to the accompanying drawings, the embodiment of various aspects of the present invention is described in further detail.
Fig. 1 illustrates a kind of circuit structure diagram of realizing the driving circuit of signal transmitted in both directions of the prior art.
With reference to Fig. 1, traditional driving circuit comprises that a first transistor T11, a transistor seconds T12, one the 3rd transistor T 13, one the 4th transistor T 14(are as shown in dotted line frame).For example, the first transistor T11 to the four transistor Ts 14 are thin film transistor (TFT) (Thin Film Transistor, TFT), the grid of the corresponding thin film transistor (TFT) of transistorized control end, the drain electrode of the corresponding thin film transistor (TFT) of transistorized first end, the source electrode of the corresponding thin film transistor (TFT) of transistorized the second end.
The first transistor T11 has control end, first end and the second end.The first end of the first transistor T11 and control end all receive (n+2) individual control signal ST (n+2).In addition, between the second end of the first transistor T11 and the second end of transistor T 16, also comprise a capacitor C.Transistor seconds T12 has control end, first end and the second end.The first end of transistor seconds T12 and control end all receive (n+1) individual gate drive signal G(n+1).The second end of transistor seconds T12 is electrically connected to the second end of the first transistor T11, as shown in Figure 1, the second end of transistor seconds T12 is, the second end formation one common node Q(n connected with each other of the second end of the second end of the first transistor T11, the 3rd transistor T 13 and the 4th transistor T 14).
Similarly, the 3rd transistor T 13 has control end, first end and the second end.The first end of the 3rd transistor T 13 and control end all receive (n-2) individual control signal ST(n-2).The 4th transistor T 14 has control end, first end and the second end.The first end of the 4th transistor T 14 and control end all receive (n-1) individual gate drive signal G(n-1).
Hence one can see that, and the first transistor T11 and transistor seconds T12 are set up and the 3rd transistor T 13 and the 4th transistor T 14 symmetries.For example, the first end of the first transistor T11 and control end receive (n+2) individual control signal ST (n+2), and the first end of the 3rd transistor T 13 and control end receive (n-2) individual control signal ST (n-2).And for example, the first end of transistor seconds T12 and control end receive (n+1) individual gate drive signal G(n+1), and the first end of the 4th transistor T 14 and control end receive (n-1) individual gate drive signal G(n-1).As shown in Figure 1, when forward scan, by the 3rd transistor and the 4th transistor to common node Q(n) charging, and see through (n+4) individual gate drive signal G(n+4) to common node Q(n) electric discharge; When negative sense scans, by the first transistor and transistor seconds to common node Q(n) charging, and see through (n-4) individual gate drive signal G(n-4) to common node Q(n) electric discharge.Thus, this driving circuit can make the signal transmission in circuit possess two-way function through above-mentioned symmetrical architecture.But this symmetrical architecture is comparatively complicated, extra fabric swatch area is too much, and significant adverse is in the narrow typeization design of frame.
In order to address the aforementioned drawbacks or deficiency, Fig. 2 illustrates the circuit structure diagram according to the driving circuit of the signal the realized transmitted in both directions of an embodiment of the present invention.Fig. 3 illustrates the specific embodiment of circuit framework of the drop-down unit with pull-down control circuit and pull-down circuit of Fig. 2, and Fig. 4 illustrates the timing waveform schematic diagram of the key signal in the driving circuit of the signal realized transmitted in both directions of Fig. 2.
With reference to Fig. 2, the driving circuit of realizing signal transmitted in both directions of the present invention is suitable for array basal plate row and drives (Gate driver On Array, GOA) panel.This driving circuit 20 comprises a first transistor T21, a transistor seconds T22 and one the 3rd transistor T 23.
Particularly, the first transistor T21 has control end, first end and the second end.The first end of the first transistor T21 is electrically connected (n-2) individual grid drive terminal G(n-2).The control end of the first transistor T21 is electrically connected (n-4) individual control terminal Q(n-4).Transistor seconds T22 has control end, first end and the second end.The first end of transistor seconds T22 is electrically connected the second end of the first transistor T21 to form a common node Q(n).The second end of transistor seconds T22 is electrically connected (n+2) individual grid drive terminal G(n+2).The control end of transistor seconds T22 is electrically connected (n+4) individual control terminal Q(n+4).The 3rd transistor T 23 has control end, first end and the second end.The first end of the 3rd transistor T 23 receives a high-frequency clock pulse signal HC1.The second end of the 3rd transistor T 23 is electrically connected n grid drive terminal G(n).The control end of the 3rd transistor T 23 is electrically coupled to the second end of the first transistor T21 and the first end of transistor seconds T22.It needs to be noted, this driving circuit 20 is by common node Q(n) two stage potential voltages (as shown in the timing waveform of Fig. 4) make the first transistor T21 and transistor seconds T22 possess charge and discharge function simultaneously, thereby realize signal transmitted in both directions.
In one embodiment, this driving circuit also comprises a capacitor C 1.One end of capacitor C 1 is electrically connected to the second end of the first transistor T21 and the first end of transistor seconds T22, and the other end of capacitor C 1 is electrically connected to the second end of the 3rd transistor T 23.
It will be understood by those of skill in the art that Fig. 2 not only can schematically describe the driving circuit of realizing signal transmitted in both directions of the present invention, but also the shift register structure that contains this driving circuit of the present invention can be described.
Referring again to Fig. 2, this shift register comprises one first drop-down unit, one second drop-down unit and one drive circuit 20.The circuit framework that it is pointed out that driving circuit 20 is at length explained hereinbefore, for convenience of description for the purpose of, repeat no more herein.
The first drop-down unit is in order to receive one first low-frequency clock pulse signal LC1 and a n control terminal Q(n), and export n grid drive terminal G(n).The second drop-down unit is in order to receive one second low-frequency clock pulse signal LC2 and a n control terminal Q(n), and export n grid drive terminal G(n), the phase place of the second low-frequency clock pulse signal LC2 is different from the phase place of the first low-frequency clock pulse signal LC1.
In one embodiment, as shown in Figure 3, the first drop-down unit and the second drop-down unit include pull-down control circuit and the pull-down circuit of cascade.For example, the first drop-down unit comprises the first pull-down control circuit 202 and the first pull-down circuit 204.The second drop-down unit comprises the second pull-down control circuit 206 and the second pull-down circuit 208.Each pull-down control circuit receive low-frequency clock pulse signal and from the signal Q(n of n control terminal).Pull-down circuit is electrically connected output terminal and output drive signal to the n the grid drive terminal G(n of pull-down control circuit).
Further, each pull-down control circuit comprises one the 4th transistor (T51 or T61), one the 5th transistor (T52 or T62), one the 6th transistor (T53 or T63) and one the 7th transistor (T54 or T64).Each pull-down circuit comprises one the 8th transistor (T41 or T42) and one the 9th transistor (T31 or T32).Below take pull-down control circuit in the first drop-down unit and pull-down circuit describes as example.
In pull-down control circuit, the 4th transistor T 51 has control end, first end and the second end.The first end of the 4th transistor T 51 is connected with control end and in order to receive low-frequency clock pulse signal LC1.The 5th transistor T 52 has control end, first end and the second end.The first end of the 5th transistor T 52 is electrically connected to the second end of the 4th transistor T 51, and the control end of the 5th transistor T 52 is electrically connected n control terminal Q(n), the second end of the 5th transistor T 52 is electrically connected to a threshold voltage VSS.The 6th transistor T 53 has control end, first end and the second end.The first end of the 6th transistor T 53 is electrically connected to the first end of the 4th transistor T 51, and the control end of the 6th transistor T 53 is electrically connected to the second end of the 4th transistor T 51.The 7th transistor T 54 has control end, first end and the second end.The first end of the 7th transistor T 54 is electrically connected to the second end of the 6th transistor T 53.The control end of the 7th transistor T 54 is electrically connected n control terminal Q(n).The second end of the 7th transistor T 54 is electrically connected to threshold voltage VSS.
In pull-down circuit, the 8th transistor T 41 has control end, first end and the second end.The first end of the 8th transistor T 41 is electrically connected to common node Q(n).The control end of the 8th transistor T 41 is electrically connected to the second end of the 6th transistor T 53 and the first end of the 7th transistor T 54.The second end of the 8th transistor T 41 is electrically connected to n grid drive terminal G(n).The 9th transistor T 31 has control end, first end and the second end.The first end of the 9th transistor T 31 is electrically connected to n grid drive terminal G(n), the control end of the 9th transistor T 31 is electrically connected to the second end of the 6th transistor T 53 and the first end of the 7th transistor T 54, and the second end of the 9th transistor T 31 is electrically connected to threshold voltage VSS.
In one embodiment, as (n-4) individual control terminal Q(n-4) be noble potential and (n+4) individual control terminal Q(n+4) during for electronegative potential, the first transistor T21 conducting and transistor seconds T22 turn-off.In addition, as (n-2) individual grid drive terminal G(n-2) while being noble potential, common node Q(n) voltage is noble potential, thereby the 3rd transistor T 23 conductings by the high-frequency clock pulse signal HC1 of noble potential to n grid drive terminal G(n) charge, as shown in time durations t2.
In one embodiment, as (n+4) individual control terminal Q(n+4) be noble potential and (n-4) individual control terminal Q(n-4) during for electronegative potential, the first transistor T21 turn-offs and transistor seconds T22 conducting.In addition, as (n+2) individual grid drive terminal G(n+2) while being noble potential, common node Q(n) voltage is noble potential, thus the 3rd transistor T 23 conductings by the high-frequency clock pulse signal HC1 of electronegative potential to n grid drive terminal G(n) discharge.Afterwards, (n+2) individual grid drive terminal G(n+2) voltage be electronegative potential, common node Q(n) is also transformed to electronegative potential thereupon, as shown in time durations t5.
Fig. 5 illustrates the circuit structure diagram according to the driving circuit of the signal the realized transmitted in both directions of another embodiment of the present invention.
Fig. 5 and Fig. 3 are compared, and the driving circuit of Fig. 5 is substantially similar to the driving circuit of Fig. 3, for convenience of description for the purpose of, do not repeat them here.The key distinction of Fig. 5 and Fig. 3 is that the circuit framework that is drop-down unit is simplified more.
Particularly, this drop-down unit comprises the 4th transistor T 51, the 5th transistor T 42, the 6th transistor T 32 and the 7th transistor T 31.The control end of the 4th transistor T 51 is electrically connected n control terminal Q(n).The first end of the 4th transistor T 51 is connected to high-frequency clock pulse signal HC1 by a capacitor C 2.The second end of the 4th transistor T 51 is electrically connected to a threshold voltage VSS.The control end of the 5th transistor T 42 is electrically connected to the first end of the 4th transistor T 51.The first end of the 5th transistor T 42 is electrically connected to common node Q(n).The second end of the 5th transistor T 42 is electrically connected to threshold voltage VSS.
The first end of the 6th transistor T 32 is electrically connected to the second end of the 3rd transistor T 23.The control end of the 6th transistor T 32 is electrically connected to the first end of the 4th transistor T 51.The second end of the 6th transistor T 32 is electrically connected to threshold voltage VSS.The first end of the 7th transistor T 31 is electrically connected to the second end of the 3rd transistor T 23.The second end of the 7th transistor T 31 is electrically connected to threshold voltage VSS.The control end of the 7th transistor T 31 is in order to receive another high-frequency clock pulse signal HC5.
Adopt driving circuit and the shift register thereof of realizing signal transmitted in both directions of the present invention, the first end of the first transistor is electrically connected (n-2) individual grid drive terminal and control end is electrically connected (n-4) individual control terminal, the first end of transistor seconds is electrically connected the second end of the first transistor to form a common node, the second end of transistor seconds is electrically connected (n+2) individual grid drive terminal, the control end of transistor seconds is electrically connected (n+4) individual control terminal, the two stage potential voltages by this common node make the first transistor and transistor seconds possess charge and discharge function simultaneously, thereby realize signal transmitted in both directions.Than prior art, GOA circuit framework of the present invention does not need extra signal just can reach the function of signal bi-directional, and the balancing waveform that this driving circuit can see through common node potential voltage utilizes the 3rd transistor to increase the discharge capacity of gate drive signal, not only circuit framework is simple, and circuit layout area still less.
Above, describe the specific embodiment of the present invention with reference to the accompanying drawings.But those skilled in the art can understand, without departing from the spirit and scope of the present invention in the situation that, can also do various changes and replacement to the specific embodiment of the present invention.These changes and replacement all drop in the claims in the present invention book limited range.
Claims (10)
1. can realize a driving circuit for signal transmitted in both directions, be suitable for array basal plate row and drive (Gate driver On Array, GOA) panel, it is characterized in that, described driving circuit comprises:
One the first transistor, has control end, first end and the second end, and the first end of described the first transistor is electrically connected (n-2) individual grid drive terminal, and the control end of described the first transistor is electrically connected (n-4) individual control terminal;
One transistor seconds, there is control end, first end and the second end, the first end of described transistor seconds is electrically connected the second end of described the first transistor to form a common node, the second end of described transistor seconds is electrically connected (n+2) individual grid drive terminal, and the control end of described transistor seconds is electrically connected (n+4) individual control terminal; And
One the 3rd transistor, there is control end, first end and the second end, described the 3rd transistorized first end receives a high-frequency clock pulse signal, described the 3rd transistorized the second end is electrically connected n grid drive terminal, described the 3rd transistorized control end is electrically coupled to the second end of described the first transistor and the first end of described transistor seconds
Wherein, described driving circuit makes described the first transistor and described transistor seconds possess charge and discharge function by two stage potential voltages of described common node simultaneously, thereby realizes signal transmitted in both directions.
2. driving circuit according to claim 1, it is characterized in that, described driving circuit also comprises an electric capacity, one end of described electric capacity is electrically connected to the second end of described the first transistor and the first end of described transistor seconds, and the other end of described electric capacity is electrically connected to described the 3rd transistorized the second end.
3. driving circuit according to claim 1, is characterized in that, when (n-4) individual control terminal is noble potential and (n+4) individual control terminal while being electronegative potential, described the first transistor conducting and described transistor seconds turn-off.
4. driving circuit according to claim 3, it is characterized in that, when (n-2) individual grid drive terminal is noble potential, the voltage of described common node is noble potential, thereby described the 3rd transistor turns is charged to described n grid drive terminal by the described high-frequency clock pulse signal of noble potential.
5. driving circuit according to claim 1, is characterized in that, when (n+4) individual control terminal is noble potential and (n-4) individual control terminal while being electronegative potential, described the first transistor turn-offs and described transistor seconds conducting.
6. driving circuit according to claim 5, it is characterized in that, when (n+2) individual grid drive terminal is noble potential, the voltage of described common node is noble potential, thereby described the 3rd transistor turns is discharged to described n grid drive terminal by the described high-frequency clock pulse signal of electronegative potential.
7. a shift register, is suitable for array basal plate row and drives (Gate driver On Array, GOA) panel, it is characterized in that, described shift register comprises:
One first drop-down unit, in order to receive one first low-frequency clock pulse signal and a n control terminal, and exports n grid drive terminal;
One second drop-down unit, in order to receive one second low-frequency clock pulse signal and a n control terminal, and exports n grid drive terminal, and the phase place of described the second low-frequency clock pulse signal is different from the phase place of described the first low-frequency clock pulse signal; And
One drive circuit, comprising:
One the first transistor, has control end, first end and the second end, and the first end of described the first transistor is electrically connected (n-2) individual grid drive terminal, and the control end of described the first transistor is electrically connected (n-4) individual control terminal;
One transistor seconds, there is control end, first end and the second end, the first end of described transistor seconds is electrically connected to the second end of described the first transistor to form a common node, the second end of described transistor seconds is electrically connected (n+2) individual grid drive terminal, and the control end of described transistor seconds is electrically connected (n+4) individual control terminal; And
One the 3rd transistor, there is control end, first end and the second end, described the 3rd transistorized first end receives a high-frequency clock pulse signal, described the 3rd transistorized the second end is electrically connected n grid drive terminal, described the 3rd transistorized control end is electrically coupled to the second end of described the first transistor and the first end of described transistor seconds, wherein, described driving circuit makes described the first transistor and transistor seconds possess charge and discharge function by two stage potential voltages of described common node simultaneously, thereby realizes signal transmitted in both directions.
8. shift register according to claim 7, it is characterized in that, described the first drop-down unit and described the second drop-down unit include pull-down control circuit and the pull-down circuit of cascade, wherein, described pull-down control circuit receives low-frequency clock pulse signal and from the signal of described n control terminal, and described pull-down circuit is electrically connected extremely described n grid drive terminal of the output terminal of described pull-down control circuit and output drive signal.
9. shift register according to claim 8, is characterized in that, described pull-down control circuit comprises:
One the 4th transistor, has control end, first end and the second end, and described the 4th transistorized first end is connected with control end and in order to receive described low-frequency clock pulse signal;
One the 5th transistor, there is control end, first end and the second end, described the 5th transistorized first end is electrically connected to described the 4th transistorized the second end, described the 5th transistorized control end is electrically connected described n control terminal, and described the 5th transistorized the second end is electrically connected to a threshold voltage;
One the 6th transistor, has control end, first end and the second end, and described the 6th transistorized first end is electrically connected to described the 4th transistorized first end, and described the 6th transistorized control end is electrically connected to described the 4th transistorized the second end; And
One the 7th transistor, there is control end, first end and the second end, described the 7th transistorized first end is electrically connected to described the 6th transistorized the second end, described the 7th transistorized control end is electrically connected described n control terminal, and described the 7th transistorized the second end is electrically connected to described threshold voltage;
Described pull-down circuit comprises:
One the 8th transistor, there is control end, first end and the second end, described the 8th transistorized first end is electrically connected to described common node, described the 8th transistorized control end is electrically connected to described the 6th transistorized the second end and described the 7th transistorized first end, and described the 8th transistorized the second end is electrically connected to n grid drive terminal; And
One the 9th transistor, there is control end, first end and the second end, described the 9th transistorized first end is electrically connected to n grid drive terminal, described the 9th transistorized control end is electrically connected to described the 6th transistorized the second end and described the 7th transistorized first end, and described the 9th transistorized the second end is electrically connected to described threshold voltage.
10. a shift register, is suitable for array basal plate row and drives (Gate driver On Array, GOA) panel, it is characterized in that, described shift register comprises:
One drive circuit, comprising:
One the first transistor, has control end, first end and the second end, and the first end of described the first transistor is electrically connected (n-2) individual grid drive terminal, and the control end of described the first transistor is electrically connected (n-4) individual control terminal;
One transistor seconds, there is control end, first end and the second end, the first end of described transistor seconds is electrically connected to the second end of described the first transistor to form a common node, the second end of described transistor seconds is electrically connected (n+2) individual grid drive terminal, and the control end of described transistor seconds is electrically connected (n+4) individual control terminal; And
One the 3rd transistor, there is control end, first end and the second end, described the 3rd transistorized first end receives a high-frequency clock pulse signal, described the 3rd transistorized the second end is electrically connected n grid drive terminal, described the 3rd transistorized control end is electrically coupled to the second end of described the first transistor and the first end of described transistor seconds, wherein, described driving circuit makes described the first transistor and transistor seconds possess charge and discharge function by two stage potential voltages of described common node simultaneously, thereby realizes signal transmitted in both directions; And
One drop-down unit, comprising:
One the 4th transistor, there is control end, first end and the second end, described the 4th transistorized control end is electrically connected n control terminal, described the 4th transistorized first end is connected to described high-frequency clock pulse signal by an electric capacity, and described the 4th transistorized the second end is electrically connected to a threshold voltage;
One the 5th transistor, there is control end, first end and the second end, described the 5th transistorized control end is electrically connected to described the 4th transistorized first end, described the 5th transistorized first end is electrically connected to described common node, and described the 5th transistorized the second end is electrically connected to described threshold voltage;
One the 6th transistor, there is control end, first end and the second end, described the 6th transistorized first end is electrically connected to described the 3rd transistorized the second end, described the 6th transistorized control end is electrically connected to described the 4th transistorized first end, and described the 6th transistorized the second end is electrically connected to described threshold voltage; And
One the 7th transistor, there is control end, first end and the second end, described the 7th transistorized first end is electrically connected to described the 3rd transistorized the second end, described the 7th transistorized the second end is electrically connected to described threshold voltage, and described the 7th transistorized control end is in order to receive another high-frequency clock pulse signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310697800.9A CN103680450A (en) | 2013-12-18 | 2013-12-18 | Drive circuit capable of achieving two-way transmission of signals and shifting register thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310697800.9A CN103680450A (en) | 2013-12-18 | 2013-12-18 | Drive circuit capable of achieving two-way transmission of signals and shifting register thereof |
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| CN201310697800.9A Pending CN103680450A (en) | 2013-12-18 | 2013-12-18 | Drive circuit capable of achieving two-way transmission of signals and shifting register thereof |
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Application publication date: 20140326 |