CN108986732B - Shift register circuit and display device - Google Patents
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention discloses a shift register circuit and a display device. The shift temporary storage circuit comprises a plurality of stages of shift temporary storage units which are arranged in a cascade manner, each shift temporary storage unit comprises a charging module, an output module, a reset module and a voltage stabilizing module, each voltage stabilizing module comprises a first voltage stabilizing sub-module and a second voltage stabilizing sub-module, first ends of the first voltage stabilizing sub-module and the second voltage stabilizing sub-module are respectively and electrically connected with a low-frequency voltage stabilizing signal source and a high-frequency voltage stabilizing signal source, second ends of the first voltage stabilizing sub-module and the second voltage stabilizing sub-module are respectively and electrically connected with a scanning signal output end of the shift temporary storage unit of the current stage, third ends of the first voltage stabilizing sub-module and the second voltage stabilizing sub-module are respectively and electrically connected with pull-up points of the shift temporary storage unit of the current stage, fourth ends of the first voltage stabilizing sub-module and the second voltage stabilizing sub-module are respectively and electrically connected with a low-level signal source, and when the low-frequency voltage stabilizing signal is at a high level, the first voltage stabilizing submodule is communicated with a pull-up point, a scanning signal output end and a low level signal source, and the second voltage stabilizing submodule is communicated with the pull-up point, the scanning signal output end and the low level signal source when the high-frequency voltage stabilizing signal is at a high level. The technical scheme of the invention can eliminate timing noise.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register circuit and a display device.
Background
In a conventional display device, a line scan signal is implemented by an external integrated circuit, and with the development of light weight, thin frame, and low cost of the display device, the line scan signal is generally output by Gate Drive on Array (GOA) on an Array substrate, and specifically, by integrating a shift register circuit on the Array substrate of the display device. However, in the multi-clock shift register circuit, the clock signal is a periodic signal, and the same clock signal often controls a plurality of shift register units in the shift register circuit, which results in the generation of timing noise, thereby causing adverse effects on the display effect of the display device.
Disclosure of Invention
The present invention is directed to a shift register circuit, which solves the technical problem of timing noise in the display device and improves the display effect of the display device.
In order to achieve the above object, the shift register circuit provided by the present invention includes a plurality of cascaded shift register units, each of the cascaded shift register units includes a charging module, an output module, a reset module and a voltage stabilizing module, wherein the voltage stabilizing module includes a first voltage stabilizing sub-module and a second voltage stabilizing sub-module, a first end of the first voltage stabilizing sub-module is electrically connected to a low-frequency voltage stabilizing signal source, a second end of the first voltage stabilizing sub-module is electrically connected to a scan signal output end of the shift register unit of the current stage, a third end of the first voltage stabilizing sub-module is electrically connected to a pull-up point of the shift register unit of the current stage, a fourth end of the first voltage stabilizing sub-module is electrically connected to a low-level signal source, and when a low-frequency voltage stabilizing signal generated by the low-frequency voltage signal source is at a high level, the first voltage stabilizing sub-module communicates the pull-up point, the scan signal output end and the low-level signal source, to eliminate the timing noise of the pull-up point and the scan signal output end; the first end of the second voltage stabilizing sub-module is electrically connected with a high-frequency voltage stabilizing signal source, the second end of the second voltage stabilizing sub-module is electrically connected with the scanning signal output end of the shift temporary storage unit at the current stage, the third end of the second voltage stabilizing sub-module is electrically connected with the pull-up point of the shift temporary storage unit at the current stage, the fourth end of the second voltage stabilizing sub-module is electrically connected with the low-level signal source, and when the high-frequency voltage stabilizing signal generated by the high-frequency voltage stabilizing signal source is at a high level, the second voltage stabilizing sub-module is communicated with the pull-up point, the scanning signal output end and the low-level signal source so as to eliminate timing noise of the pull-up point and the scanning signal output end.
Optionally, the first voltage stabilizing sub-module includes a first switching device and a second switching device, a gate of the first switching device is electrically connected to the low-frequency voltage stabilizing signal source, a drain of the first switching device is electrically connected to a scan signal output end of the shift register unit of the current stage, and a source of the first switching device is electrically connected to the low-level signal source; the grid electrode of the second switching device is electrically connected with the low-frequency voltage-stabilizing signal source, the drain electrode of the second switching device is electrically connected with the pull-up point of the shift temporary storage unit at the current stage, and the source electrode of the second switching device is electrically connected with the low-level signal source.
Optionally, the high-frequency voltage-stabilizing signal source is a previous-stage clock signal source; the second voltage stabilizing sub-module comprises a third switching device and a fourth switching device, the grid electrode of the third switching device is electrically connected with the previous-stage clock signal source, the drain electrode of the third switching device is electrically connected with the scanning signal output end of the current-stage shift temporary storage unit, and the source electrode of the third switching device is electrically connected with the low-level signal source; the grid electrode of the fourth switching device is electrically connected with the previous stage clock signal source, the drain electrode of the fourth switching device is electrically connected with the pull-up point of the current stage shift temporary storage unit, and the source electrode of the fourth switching device is electrically connected with the low level signal source.
Optionally, the shift register unit further includes a fifth switching device, a gate of the fifth switching device is electrically connected to the pull-up point of the shift register unit of the current stage, a drain of the fifth switching device is electrically connected to the high-frequency voltage-stabilizing signal source, and a source of the fifth switching device is electrically connected to the low-level signal source.
Optionally, the low-frequency voltage-stabilizing signal source includes a sixth switching device, a seventh switching device, an eighth switching device, a ninth switching device, a tenth switching device, and an eleventh switching device, and a gate and a drain of the sixth switching device are electrically connected to the low-frequency clock signal source; a grid electrode of the seventh switching device is electrically connected with a source electrode of the sixth switching device, a drain electrode of the seventh switching device is electrically connected with a drain electrode of the sixth switching device, and a source electrode of the seventh switching device is electrically connected with the first end of the first voltage stabilizing sub-module; a grid electrode of the eighth switching device is electrically connected with a pull-up point of a previous-stage shift temporary storage unit, a drain electrode of the eighth switching device is electrically connected with a source electrode of the seventh switching device, and the source electrode of the eighth switching device is electrically connected with the low-level signal source; a grid electrode of the ninth switching device is electrically connected with a pull-up point of a previous-stage shift temporary storage unit, a drain electrode of the ninth switching device is electrically connected with a grid electrode of the seventh switching device, and a source electrode of the ninth switching device is electrically connected with the low-level signal source; a grid electrode of the tenth switching device is electrically connected with a pull-up point of the shift temporary storage unit at the current stage, a drain electrode of the tenth switching device is electrically connected with a source electrode of the seventh switching device, and the source electrode of the tenth switching device is electrically connected with the low level signal source; the grid electrode of the eleventh switching device is electrically connected with the pull-up point of the shift temporary storage unit at the current stage, the drain electrode of the eleventh switching device is electrically connected with the grid electrode of the seventh switching device, and the source electrode of the eleventh switching device is electrically connected with the low-level signal source.
Optionally, the charging module includes a twelfth switching device, a gate of the twelfth switching device is electrically connected to the feedback signal output end of the preceding stage shift temporary storage unit, a drain of the twelfth switching device is electrically connected to the gate of the twelfth switching device or a high level signal source, and a source of the twelfth switching device is electrically connected to a pull-up point of the present stage shift temporary storage unit.
Optionally, the output module includes a tenth three-switch device, a gate of the tenth three-switch device is electrically connected to a pull-up point of the shift temporary storage unit of the current stage, a drain of the tenth three-switch device is electrically connected to the clock signal source of the current stage, and a source of the tenth three-switch device is electrically connected to the scan signal output terminal of the shift temporary storage unit of the current stage.
Optionally, the output module further includes a fourteenth switching device, a gate of the fourteenth switching device is electrically connected to the pull-up point of the current-stage shift register unit, a drain of the fourteenth switching device is electrically connected to the current-stage clock signal source, and a source of the fourteenth switching device is electrically connected to the feedback signal output end of the current-stage shift register unit.
Optionally, the reset module includes a fifteenth switching device and a sixteenth switching device, a gate of the fifteenth switching device is electrically connected to a pull-down point of the shift register unit of the current stage, a drain of the fifteenth switching device is electrically connected to a scan signal output end of the shift register unit of the current stage, and a source of the fifteenth switching device is electrically connected to the low-level signal source; a grid electrode of the sixteenth switching device is electrically connected with a pull-down point of the current-stage shift temporary storage unit, a drain electrode of the sixteenth switching device is electrically connected with a pull-up point of the current-stage shift temporary storage unit, and a source electrode of the sixteenth switching device is electrically connected with the low-level signal source; the pull-down point of the shift temporary storage unit at the current stage is electrically connected with the feedback signal output end of the shift temporary storage unit at the later stage.
In order to achieve the above object, the present invention further provides a display device, where the display device includes a display panel and a driving unit, the driving unit includes a shift register circuit, the shift register circuit includes multiple stages of shift register units arranged in a cascade, the shift register unit includes a charging module, an output module, a reset module and a voltage stabilizing module, where the voltage stabilizing module includes a first voltage stabilizing module and a second voltage stabilizing module, a first end of the first voltage stabilizing module is electrically connected to a low-frequency voltage stabilizing signal source, a second end of the first voltage stabilizing module is electrically connected to a scanning signal output end of the shift register unit, a third end of the first voltage stabilizing module is electrically connected to a pull-up point of the shift register unit, a fourth end of the first voltage stabilizing module is electrically connected to a low-level signal source, and a low-frequency voltage stabilizing signal generated by the low-frequency voltage stabilizing signal source is at a high level, the first voltage stabilizing sub-module is communicated with the pull-up point, the scanning signal output end and the low level signal source so as to eliminate timing noise of the pull-up point and the scanning signal output end; the first end of the second voltage stabilizing sub-module is electrically connected with a high-frequency voltage stabilizing signal source, the second end of the second voltage stabilizing sub-module is electrically connected with the scanning signal output end of the current-stage shift temporary storage unit, the third end of the second voltage stabilizing sub-module is electrically connected with the pull-up point of the current-stage shift temporary storage unit, the fourth end of the second voltage stabilizing sub-module is electrically connected with the low-level signal source, when a high-frequency voltage stabilizing signal generated by the high-frequency voltage stabilizing signal source is at a high level, the second voltage stabilizing sub-module is communicated with the pull-up point, the scanning signal output end and the low-level signal source so as to eliminate timing noises of the pull-up point and the scanning signal output end, and the shift temporary storage circuit is an array substrate gate drive integrated circuit.
In the technical scheme of the invention, the shift register circuit comprises a plurality of stages of shift register units which are arranged in a cascade way, each shift register unit comprises a charging module, an output module, a reset module and a voltage stabilizing module, wherein, the voltage stabilizing module comprises a first voltage stabilizing sub-module and a second voltage stabilizing sub-module, the first end of the first voltage stabilizing sub-module is electrically connected with the low-frequency voltage stabilizing signal source, the second end of the first voltage stabilizing sub-module is electrically connected with the scanning signal output end of the current stage shift temporary storage unit, the third end of the first voltage stabilizing sub-module is electrically connected with the pull-up point of the current stage shift temporary storage unit, the fourth end of the first voltage stabilizing sub-module is electrically connected with the low-level signal source, when the low-frequency voltage stabilizing signal generated by the low-frequency voltage stabilizing signal source is at high level, the first voltage stabilizing sub-module is communicated with a pull-up point, a scanning signal output end and a low level signal source so as to eliminate timing noise of the pull-up point and the scanning signal output end; the first end of the second voltage stabilizing sub-module is electrically connected with the high-frequency voltage stabilizing signal source, the second end of the second voltage stabilizing sub-module is electrically connected with the scanning signal output end of the current-stage shifting temporary storage unit, the third end of the second voltage stabilizing sub-module is electrically connected with the pull-up point of the current-stage shifting temporary storage unit, the fourth end of the second voltage stabilizing sub-module is electrically connected with the low-level signal source, when the high-frequency voltage stabilizing signal generated by the high-frequency voltage stabilizing signal source is at a high level, the second voltage stabilizing sub-module is communicated with the pull-up point, the scanning signal output end and the low-level signal source, and therefore timing noise of the pull-up point and the scanning signal output end is eliminated. Through setting up first voltage stabilizing submodule piece and second voltage stabilizing submodule piece simultaneously, under the effect of low frequency steady voltage signal and high frequency steady voltage signal respectively, make pull-up point, scanning signal output terminal and the low level signal source of aversion temporary storage unit communicate, increased the discharge channel of pull-up point and scanning signal output terminal of aversion temporary storage unit to make it keep in the low level state at predetermineeing constantly, with the timing noise that probably exists in the effective elimination display device, thereby improved display device's display effect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a circuit diagram illustrating an exemplary nth shift register unit of a shift register circuit;
FIG. 2 is a timing diagram of an exemplary 8CK shift register circuit;
FIG. 3 is a schematic structural diagram of a display device according to an embodiment of the present invention;
FIG. 4 is a block diagram of an nth shift register unit according to an embodiment of the shift register circuit of the present invention;
FIG. 5 is a schematic circuit diagram of an nth shift register unit according to another embodiment of the shift register circuit of the present invention;
FIG. 6 is a timing diagram of an 8CK shift register circuit according to another embodiment of the shift register circuit of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Fig. 1 is a circuit diagram illustrating an exemplary nth stage shift register unit of a shift register circuit, wherein a pull-up point of the nth stage is pre-charged by an nth stage pre-charge signal ST '(n), where the pull-up signal corresponding to the nth stage pull-up point is PU' (n). Meanwhile, due to the coupling capacitance C ' gd between the gate and the drain of the switching device T13 ', the nth stage clock signal CK ' (n) is coupled to the pull-up point of the present stage shift register unit, and when the nth stage clock signal CK ' (n) is at a high level, the switching device T13 ' is turned on, and the nth stage clock signal is transmitted to the source of the switching device T13 ', generating a high level in the nth stage scan signal G ' (n). The gates of the switching device T15 ' and the switching device T16 ' are electrically connected to the pull-down signal source of the shift register unit of the current stage, the source is electrically connected to the low-level signal source, the drain of the switching device T15 ' is electrically connected to the scan signal output terminal, and the drain of the switching device T16 ' is electrically connected to the pull-up point, so that the reset of the nth scan signal G ' (n) is realized. The gate and drain of the switching device T14 ' shown in fig. 1 are connected to the gate and drain of the switching device T13 ', and the switching device T14 ' is configured to output the nth-stage feedback signal F ' (n), which corresponds to the nth-stage scan signal G ' (n). Of course, the switching device T14 ' may be omitted, and the nth stage feedback signal F ' (n) may be directly output from the source of the switching device T13 '. Fig. 2 is a timing diagram of the shift register circuit corresponding to fig. 1, taking an eight clock (CK8) shift register circuit as an example, since the clock signal is a periodic signal and the same clock signal usually controls a plurality of shift register units, for example, the 4 th clock signal CK' (4) will control the 4 th +8 th shift register units, where m is an integer greater than or equal to zero. Meanwhile, when the clock signal is at a high level, it is coupled to each shift register unit controlled by the shift register unit, which results in the false turn-on of the switching devices T13 'and/or T14', and thus the generation of timing noise as shown in the dashed oval frame in fig. 2. In an example, the timing noise can be eliminated by providing the voltage stabilizing module 111'. Specifically, the voltage stabilizing module 111' includes a pull-down sub-module and a pull-down control sub-module, the pull-down sub-module is configured to maintain a pull-up point of the shift register unit at a low level at a preset time, so as to eliminate timing noise, and the pull-down control sub-module is configured to control operation of the pull-down sub-module. The regulation module 111' in the example as a whole may operate under the control of the low frequency regulation signal.
The present invention provides a shift register circuit to eliminate the timing noise in the display device. In an embodiment of the present invention, as shown in fig. 3 and 4, the shift register circuit includes a plurality of stages of shift register units arranged in a cascade, each of the shift register units includes a charging module 112, an output module 113, a reset module 114 and a voltage stabilizing module 111, wherein the voltage stabilizing module 111 includes a first voltage stabilizing sub-module 111a and a second voltage stabilizing sub-module 111b, a first end L1 of the first voltage stabilizing sub-module 111a is electrically connected to the low-frequency voltage signal source, a second end L2 of the first voltage stabilizing sub-module 111a is electrically connected to the scan signal output end of the shift register unit of the present stage, a third end L3 of the first voltage stabilizing sub-module 111a is electrically connected to the pull-up point of the temporary shift register unit of the present stage, a fourth end L4 of the first voltage stabilizing sub-module 111a is electrically connected to the low-level signal source, and a low-frequency voltage signal P1(n) generated by the low-frequency voltage signal source is at a high level, the first voltage sub-module 111a connects the pull-up point, Scanning the signal output end and the low level signal source to eliminate the timing noise of the pull-up point and the scanning signal output end; the first end H1 of the second voltage-stabilizing sub-module 111b is electrically connected to the high-frequency voltage-stabilizing signal source, the second end H2 of the second voltage-stabilizing sub-module 111b is electrically connected to the scan signal output end of the current-stage shift register unit, the third end H3 of the second voltage-stabilizing sub-module 111b is electrically connected to the pull-up point of the current-stage shift register unit, the fourth end H4 of the second voltage-stabilizing sub-module 111b is electrically connected to the low-level signal source, and when the high-frequency voltage-stabilizing signal P2(n) generated by the high-frequency voltage-stabilizing signal source is at a high level, the second voltage-stabilizing sub-module 111b is communicated with the pull-up point, the scan signal output end and the low.
Hereinafter, a liquid crystal display device will be taken as an example to describe the embodiments of the present invention in detail. As shown in fig. 3, the display device includes a display panel including an array substrate 100, a color filter substrate 200, and liquid crystal (not shown) filled between the array substrate 100 and the color filter substrate 200. The display panel is provided with a plurality of pixels arranged in a rectangular array, each pixel generally includes a plurality of sub-pixels, the array substrate 100 is provided with a switching device corresponding to each sub-pixel, and the color filter substrate 200 is provided with a color filter block corresponding to each sub-pixel. Under the control of the switching device on the array substrate 100, the liquid crystal in the region corresponding to each sub-pixel is deflected at a certain angle to realize the display of a specific image. In the display device with the GOA architecture, a shift register circuit 110 is further disposed on the array substrate 100 for driving each row of sub-pixels. The shift register circuit 110 is directly integrated on the array substrate 100 through a micro-processing process, so that an external shift register circuit is omitted, the material cost and the process cost of the display device are reduced, and the light, thin and narrow frame design of the display device is facilitated.
The shift register circuit 110 is developed based on the thompson circuit, and includes multiple stages of shift register units arranged in a cascade manner, where a feedback signal F (n-i) output by a preceding stage of shift register unit can be used as a pre-charge signal st (n) of the shift register unit of the current stage, and a feedback signal F (n + j) output by a subsequent stage of shift register unit can be used as a pull-down signal pd (n) of the shift register unit of the current stage, where i and j are positive integers respectively, and specific values thereof are related to a time sequence in the shift register circuit, and are not described herein again. The scanning signal and the feedback signal of the same-stage shift temporary storage unit are generally consistent, the first-stage shift temporary storage unit can take an independently provided initial signal as a pre-charging signal, and the last-stage shift temporary storage unit can be provided with a redundant shift temporary storage unit to provide a pull-down signal for the last-stage shift temporary storage unit.
In each stage of shift register unit, as shown in fig. 4, a first end of the charging module 112 receives the precharge signal st (n), a second end of the charging module 112 is connected to a first end of the output module 113, and a pull-up point of the shift register unit is located between the charging module 112 and the output module 113, where a pull-up signal corresponding to the pull-up point is denoted by pu (n). The second end of the output module 113 receives the clock signal ck (n), and it should be noted that in the shift register circuit, the same clock signal is often used to control multiple stages of shift register units, for example, for a TCK shift register circuit, the T-th stage clock signal will control the T + Tm stage of shift register units, where m is an integer greater than or equal to zero, and T is the total number of clock signal sources. The output module 113 outputs a scan signal g (n) at a third end and outputs a feedback signal f (n) at a fourth end, wherein the scan signal g (n) is used to drive the corresponding sub-pixel row, and the feedback signal f (n) is usually completely consistent with the scan signal g (n) and is used as a pull-down signal of the preceding stage shift register unit. The first end of the reset module 114 is connected to the pull-up point of the current stage of the shift register unit, the second end of the reset module 114 is connected to the third end of the output module 113, the third end of the reset module 114 is connected to the low level signal source, and the fourth end of the reset module 114 receives the pull-down signal pd (n) of the current stage of the shift register unit. Under the control of the pull-down signal pd (n), the reset module 114 pulls down the pull-up point and the scan signal output terminal to a low level to maintain the normal operation of the shift register circuit, thereby implementing the progressive scan driving.
In order to better eliminate the timing noise possibly existing in the shift register circuit, the shift register unit further includes a voltage stabilizing module 111. As shown in fig. 4, the voltage regulation module 111 includes a first voltage regulation sub-module 111a and a second voltage regulation sub-module 111 b. The first end L1 of the first voltage regulation submodule 111a is electrically connected to the low frequency voltage regulation signal source to receive the low frequency voltage regulation signal P1 (n); the second end L2 of the first voltage-stabilizing sub-module 111a is electrically connected to the scan signal output end of the shift register unit of the current stage, and pulls the scan signal output end to a low level; the third terminal L3 of the first voltage-stabilizing sub-module 111a is electrically connected to the pull-up point of the shift register unit of the current stage, so as to pull down the pull-up point to a low level; the fourth terminal L4 of the first voltage regulation sub-module 111a is electrically connected to the low-level signal source to receive the low-level signal VSS. When the low-frequency regulated signal P1(n) generated by the low-frequency regulated signal source is at a high level, the first regulated sub-module 111a communicates the pull-up point, the scan signal output terminal and the low-level signal source to eliminate timing noise at the pull-up point and the scan signal output terminal. Similarly, the first end H1 of the second regulator submodule 111b is electrically connected to the high-frequency regulator signal source to receive the high-frequency regulator signal P2 (n); a second end H2 of the second voltage stabilizing submodule 111b is electrically connected with the scanning signal output end of the current stage shift register unit, and pulls the scanning signal output end to a low level; the third terminal H3 of the second voltage-stabilizing submodule 111b is electrically connected to the pull-up point of the shift register unit of the current stage, so as to pull down the pull-up point to a low level; the fourth terminal H4 of the second voltage regulation submodule 111b is electrically connected to the low level signal source to receive the low level signal VSS. When a high-frequency voltage-stabilizing signal P2(n) generated by the high-frequency voltage-stabilizing signal source is at a high level, the second voltage-stabilizing submodule is communicated with the pull-up point, the scanning signal output end and the low-level signal source so as to eliminate timing noise of the pull-up point and the scanning signal output end. By designing the corresponding time sequences of the low-frequency voltage-stabilizing signal P1(n) and the high-frequency voltage-stabilizing signal P2(n), the low-frequency voltage-stabilizing signal P1(n) and the high-frequency voltage-stabilizing signal P2(n) are both in a high level state at the moment when timing noise possibly occurs in the shift register unit, so that the scanning signal output end and the pull-up point are pulled down to a low level state, rapid discharge of the scanning signal output end and the pull-up point is realized, the timing noise is thoroughly eliminated, and the normal operation of the display device is guaranteed. There are many arrangements of specific circuits of the charging module 112, the output module 113, the reset module 114 and the voltage stabilizing module 111, and one of them will be described in detail later.
In this embodiment, the shift register circuit includes a plurality of stages of shift register units arranged in cascade, each shift register unit includes a charging module 112, an output module 113, a reset module 114 and a voltage stabilizing module 111, wherein the voltage stabilizing module 111 includes a first voltage stabilizing sub-module 111a and a second voltage stabilizing sub-module 111b, a first end L1 of the first voltage stabilizing sub-module 111a is electrically connected to a low-frequency voltage stabilizing signal source, a second end L2 of the first voltage stabilizing sub-module 111a is electrically connected to a scan signal output end of the shift register unit of the current stage, a third end L3 of the first voltage stabilizing sub-module 111a is electrically connected to a pull-up point of the shift register unit of the current stage, a fourth end L4 of the first voltage stabilizing sub-module 111a is electrically connected to a low-level signal source, when a low-frequency voltage stabilizing signal P1(n) generated by the low-frequency voltage stabilizing signal source is at a high level, the first voltage stabilizing sub-module 111a communicates the pull-up point, the scan signal output end and the low-level signal source, to eliminate the timing noise at the pull-up point and the output end of the scanning signal; the first end H1 of the second voltage-stabilizing sub-module 111b is electrically connected to the high-frequency voltage-stabilizing signal source, the second end H2 of the second voltage-stabilizing sub-module 111b is electrically connected to the scan signal output end of the current-stage shift register unit, the third end H3 of the second voltage-stabilizing sub-module 111b is electrically connected to the pull-up point of the current-stage shift register unit, the fourth end H4 of the second voltage-stabilizing sub-module 111b is electrically connected to the low-level signal source, and when the high-frequency voltage-stabilizing signal P2(n) generated by the high-frequency voltage-stabilizing signal source is at a high level, the second voltage-stabilizing sub-module 111b is communicated with the pull-up point, the scan signal output end and the low-level signal source to eliminate the timing noise of the pull-up point and the scan signal output end. By arranging the first voltage stabilizing sub-module 111a and the second voltage stabilizing sub-module 111b at the same time, the pull-up point, the scanning signal output end and the low level signal source of the shift register unit are communicated under the action of the low-frequency voltage stabilizing signal P1(n) and the high-frequency voltage stabilizing signal P2(n), and the discharge channels of the pull-up point and the scanning signal output end of the shift register unit are increased, so that the shift register unit is kept in a low level state at a preset moment, timing noise possibly existing in the display device is effectively eliminated, the problem of incomplete timing noise elimination is avoided, and the display effect of the display device is improved.
In another embodiment of the present invention, as shown in fig. 5, the first voltage regulation submodule 111a includes a first switching device T1 and a second switching device T2, a gate of the first switching device T1 is electrically connected to the low frequency voltage regulation signal source to receive the low frequency voltage regulation signal P1(n), a drain of the first switching device T1 is electrically connected to the scan signal output terminal of the present stage shift register unit, and a source of the first switching device T1 is electrically connected to the low level signal source; the gate of the second switching device T2 is electrically connected to the low-frequency regulated signal source to receive the low-frequency regulated signal P1(n), the drain of the second switching device T2 is electrically connected to the pull-up point of the present stage shift register unit, and the source of the second switching device T2 is electrically connected to the low-level signal source. When the low-frequency voltage-stabilizing signal is in a high level state, the first switch device T1 and the second switch device T2 are both in a conducting state, so that the pull-up point and the scan signal output end are respectively pulled down to a low level state under the action of the low level signal VSS, thereby eliminating the influence of timing noise. It should be noted that, in the following description, a specific description will be given of a scheme in which the switching device in the shift register circuit is an n-type thin film transistor.
As shown in fig. 5, the high-frequency regulated signal source is a previous-stage clock signal source, the second regulator submodule 111b includes a third switching device T3 and a fourth switching device T4, a gate of the third switching device T3 is electrically connected to the previous-stage clock signal source to receive a previous-stage clock signal CK (n-1), a drain of the third switching device is electrically connected to the scan signal output terminal of the shift register unit of the present stage, and a source of the third switching device is electrically connected to the low-level signal source; the grid electrode of the fourth switching device T4 is electrically connected with the previous-stage clock signal source to receive the previous-stage clock signal CK (n-1), the drain electrode of the fourth switching device is electrically connected with the pull-up point of the current-stage shift temporary storage unit, and the source electrode of the fourth switching device is electrically connected with the low-level signal source. When the previous stage clock signal CK (n-1) is in a high level state, the third switching device T3 and the fourth switching device T4 are both in a conducting state, so that under the action of the low level signal VSS, the pull-up point and the scan signal output end are respectively pulled down to a low level state, thereby eliminating the influence of timing noise. It should be noted that the second regulator submodule 111b further includes a corresponding switching device (not shown in the figure) for converting the previous stage clock signal CK (n-1) into the high frequency regulator signal P2(n) to eliminate an unnecessary high level in the previous stage clock signal CK (n-1), and only the required high level is reserved to generate the high frequency regulator signal P2(n), so as to avoid interference with the function of the shift register unit.
As shown in fig. 5, the shift register unit further includes a fifth switching device T5, a gate of the fifth switching device T5 is electrically connected to the pull-up point of the shift register unit of the current stage, a drain of the fifth switching device T5 is electrically connected to the high-frequency regulated signal source, and a source of the fifth switching device T5 is electrically connected to the low-level signal source. When the pull-up signal pu (n) corresponding to the pull-up point of the shift register unit of the current stage is in a high level state, it indicates that the shift register unit of the current stage is going to generate a high level of the scan signal g (n), at this time, the fifth switching device T5 is in a conducting state, under the action of the low level signal VSS, the first terminal H1 of the second voltage-stabilizing submodule 111b is pulled down to a low level state, and the second voltage-stabilizing submodule 111b controls the pull-up point and the scan signal output terminal to be disconnected from the low level signal source, so as to avoid interference caused by clamping the pull-up point and the scan signal output terminal in the low level state to the high level of the scan signal g (n).
As shown in fig. 5, the low frequency regulated signal source includes a sixth switching device T6, a seventh switching device T7, an eighth switching device T8, a ninth switching device T9, a tenth switching device T10 and an eleventh switching device T11, wherein a gate and a drain of the sixth switching device T6 are electrically connected to the low frequency clock signal source; a gate of the seventh switching device T7 is electrically connected to a source of the sixth switching device T6, a drain of the seventh switching device T7 is electrically connected to a drain of the sixth switching device T6, and a source of the seventh switching device T7 is electrically connected to the first end of the first voltage regulator sub-module; the grid electrode of the eighth switching device T8 is electrically connected with the pull-up point of the previous stage shift temporary storage unit, the drain electrode of the eighth switching device T8 is electrically connected with the source electrode of the seventh switching device T7, and the source electrode of the eighth switching device T8 is electrically connected with a low level signal source; a grid electrode of the ninth switching device T9 is electrically connected with a pull-up point of the previous stage of shift temporary storage unit, a drain electrode of the ninth switching device T9 is electrically connected with a grid electrode of the seventh switching device T7, and a source electrode of the ninth switching device T9 is electrically connected with a low level signal source; a gate of the tenth switching device T10 is electrically connected to the pull-up point of the shift register unit of the current stage, a drain of the tenth switching device T10 is electrically connected to a source of the seventh switching device T7, and a source of the tenth switching device T10 is electrically connected to the low level signal source; the gate of the eleventh switching device T11 is electrically connected to the pull-up point of the shift register unit of the current stage, the drain of the eleventh switching device T11 is electrically connected to the gate of the seventh switching device, and the source of the eleventh switching device T11 is electrically connected to the low level signal source. The low-frequency voltage-stabilizing signal source converts the low-frequency clock signal LCK into a low-frequency voltage-stabilizing signal P1(n) so as to meet the requirement of eliminating timing noise, and simultaneously avoid the interference of the pull-up point and the scanning signal output end which are clamped in a low level state all the time to the high level of the scanning signal G (n). Specifically, when the pull-up signal PU (n-1) of the shift register unit of the previous stage is at the second highest level and the highest level, the eighth switching device T8 and the ninth switching device T9 are in the on state, so that the gate of the seventh switching device T7 and the first end L1 of the first voltage regulator sub-module 111a are in the low level state under the action of the low level signal VSS, at this time, the seventh switching device T7, the first switching device T1 and the second switching device T2 are all in the off state, and the pull-up point of the shift register unit of the present stage is disconnected from the low level signal source. Similarly, when the pull-up signal pu (n) of the shift register unit of the present stage is at the second highest level and the highest level, the tenth switching device T10 and the eleventh switching device T11 are both in the on state, so that the gate of the seventh switching device T7 and the first end L1 of the first voltage regulator sub-module 111a are in the low level state under the action of the low level signal VSS, at this time, the seventh switching device T7, the first switching device T1 and the second switching device T2 are all in the off state, and the pull-up point of the shift register unit of the present stage is disconnected from the low level signal source. That is, when the pull-up signals of the previous stage shift register unit and the present stage shift register unit are at the second highest level and the highest level, the corresponding low-frequency voltage-stabilizing signal P1(n) is at the lowest level, and the pull-up point and the scan signal output terminal are disconnected from the low-level signal source, so as to avoid the interference caused by the fact that the pull-up point and the scan signal output terminal are clamped at the lowest level to the generation of the highest level of the present stage scan signal.
Meanwhile, two groups of symmetrical low-frequency voltage-stabilizing signal sources are arranged, and switching of the low-frequency voltage-stabilizing signal sources is achieved within a certain period, so that the service lives of all relevant switching devices and low-frequency clock signal sources are prolonged. When the low-frequency clock signal LCK in the low-frequency voltage-stabilizing signal source is in a high-level state, the corresponding low-frequency voltage-stabilizing signal source is in use, otherwise, the corresponding low-frequency voltage-stabilizing signal source is in an unused state. The frequency of the low-frequency clock signal LCK may be set to be an integer fraction of the frame rate of the display device.
As shown in fig. 5, the charging module 112 includes a twelfth switching device T12, a gate of the twelfth switching device T12 is electrically connected to the feedback signal output terminal of the pre-stage shift register unit, a drain of the twelfth switching device T12 is electrically connected to the gate of the twelfth switching device or a high level signal source, and a source of the twelfth switching device T12 is electrically connected to the pull-up point of the present stage shift register unit, so as to implement the pre-charging of the pull-up point.
As shown in fig. 5, the output module 113 includes a tenth switching device T13, a gate of a thirteenth switching device T13 is electrically connected to the pull-up point of the shift register unit of the current stage, a drain of the thirteenth switching device T13 is electrically connected to the clock signal source of the current stage, and a source of the thirteenth switching device T13 is electrically connected to the scan signal output terminal of the shift register unit of the current stage. When the tenth switching device T13 is turned on by the pull-up signal pu (n), the clock signal ck (n) is at a high level, thereby generating a high level of the scan signal g (n). In addition, a coupling capacitor C may be further disposed between the pull-up point of the shift register unit and the scan signal output end, so that the clock signal ck (n) is better coupled to the pull-up point to generate the high level of the scan signal g (n).
Further, the output module 113 further includes a fourteenth switching device T14, a gate of the fourteenth switching device T14 is electrically connected to the pull-up point of the shift register unit of the current stage, a drain of the fourteenth switching device T14 is electrically connected to the clock signal source of the current stage, and a source of the fourteenth switching device T14 is electrically connected to the feedback signal output terminal of the shift register unit of the current stage. The fourteenth switching device 114 and the thirteenth switching device 113 work in the same principle, and the generated feedback signal f (n) is also consistent with the scan signal g (n), and the feedback signal f (n) is used as a pre-charge signal of the next stage shift register unit or a pull-down signal of the previous stage shift register unit. Of course, in other embodiments, the fourteenth switching device T14 may be combined with the thirteenth switching device T13 as a same device, and the present stage scan signal g (n) and the feedback signal f (n) are respectively derived.
As shown in fig. 5, the reset module 114 includes a fifteenth switching device T15 and a sixteenth switching device T16, a gate of the fifteenth switching device T15 is electrically connected to the pull-down point of the shift register unit of the current stage, a drain of the fifteenth switching device T15 is electrically connected to the scan signal output terminal of the shift register unit of the current stage, and a source of the fifteenth switching device T15 is electrically connected to the low-level signal source; the grid electrode of the sixteenth switching device T16 is electrically connected with the pull-down point of the current-stage shift temporary storage unit, the drain electrode of the sixteenth switching device T16 is electrically connected with the pull-up point of the current-stage shift temporary storage unit, and the source electrode of the sixteenth switching device T16 is electrically connected with the low-level signal source; the pull-down point of the shift temporary storage unit at the current stage is electrically connected with the feedback signal output end of the shift temporary storage unit at the later stage. In the reset module 114, under the action of the pull-down signal pd (n), the on/off of the fifteenth switching device T15 and the sixteenth switching device T16 are controlled to pull down the pull-up point and the scan signal output terminal to a low level, so as to implement progressive scanning.
Fig. 6 is a timing diagram of the case of 8CK based on the corresponding shift register circuit in fig. 5. As can be seen from fig. 6, under the combined action of the low frequency stabilized signal and the high frequency stabilized signal, the timing noise in the pull-up signal and the scan signal is effectively eliminated, as shown by the oval dashed line box in fig. 6.
The present invention further provides a display device, as shown in fig. 3, the display device includes a display panel and a driving unit, the driving unit is configured to drive the display of the display panel, the driving unit includes a shift register circuit 110, and the specific structure of the shift register circuit 110 refers to the above embodiments. The shift register circuit is a gate drive integrated circuit on the array substrate to reduce material cost and process cost.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. The utility model provides a shift temporary storage circuit, its characterized in that, shift temporary storage circuit is including the multistage shift temporary storage unit that cascades the setting, shift temporary storage unit is including charging module, output module, module and voltage stabilizing module reset, wherein, voltage stabilizing module includes:
the first voltage stabilizing sub-module is electrically connected with a low-frequency voltage stabilizing signal source at a first end, electrically connected with a scanning signal output end of a shift temporary storage unit at the current stage at a second end, electrically connected with a pull-up point of the shift temporary storage unit at the current stage at a third end, and electrically connected with a low-level signal source at a fourth end, wherein when a low-frequency voltage stabilizing signal generated by the low-frequency voltage stabilizing signal source is at a high level, the first voltage stabilizing sub-module is communicated with the pull-up point, the scanning signal output end and the low-level signal source so as to eliminate timing noises of the pull-up point and the scanning signal output end;
the first end of the second voltage stabilizing sub-module is electrically connected with a high-frequency voltage stabilizing signal source, the second end of the second voltage stabilizing sub-module is electrically connected with the scanning signal output end of the current-stage shift temporary storage unit, the third end of the second voltage stabilizing sub-module is electrically connected with the pull-up point of the current-stage shift temporary storage unit, the fourth end of the second voltage stabilizing sub-module is electrically connected with the low-level signal source, and when a high-frequency voltage stabilizing signal generated by the high-frequency voltage stabilizing signal source is at a high level, the second voltage stabilizing sub-module is communicated with the pull-up point, the scanning signal output end and the low-level signal source so as to eliminate timing noise of the pull-up point and the scanning signal output end;
the shift temporary storage unit further comprises a fifth switching device, a grid electrode of the fifth switching device is electrically connected with a pull-up point of the shift temporary storage unit at the current stage, a drain electrode of the fifth switching device is electrically connected with the high-frequency voltage-stabilizing signal source, and a source electrode of the fifth switching device is electrically connected with the low-level signal source;
the high-frequency voltage-stabilizing signal source is a previous-stage clock signal source.
2. The shift register circuit of claim 1, wherein the first regulator sub-module comprises:
the grid electrode of the first switching device is electrically connected with the low-frequency voltage-stabilizing signal source, the drain electrode of the first switching device is electrically connected with the scanning signal output end of the current-stage shift temporary storage unit, and the source electrode of the first switching device is electrically connected with the low-level signal source;
and the grid electrode of the second switching device is electrically connected with the low-frequency voltage-stabilizing signal source, the drain electrode of the second switching device is electrically connected with the pull-up point of the shift temporary storage unit at the current stage, and the source electrode of the second switching device is electrically connected with the low-level signal source.
3. The shift register circuit of claim 1, wherein the high frequency regulated signal source is a previous stage clock signal source;
the second voltage regulator sub-module includes:
a grid electrode of the third switching device is electrically connected with the previous stage clock signal source, a drain electrode of the third switching device is electrically connected with a scanning signal output end of the current stage shift temporary storage unit, and a source electrode of the third switching device is electrically connected with the low level signal source;
and the grid electrode of the fourth switching device is electrically connected with the previous-stage clock signal source, the drain electrode of the fourth switching device is electrically connected with the pull-up point of the current-stage shift temporary storage unit, and the source electrode of the fourth switching device is electrically connected with the low-level signal source.
4. The shift register circuit of claim 1, wherein the low frequency regulated signal source comprises:
a grid electrode and a drain electrode of the sixth switching device are electrically connected with a low-frequency clock signal source;
a gate of the seventh switching device is electrically connected with a source of the sixth switching device, a drain of the seventh switching device is electrically connected with a drain of the sixth switching device, and a source of the seventh switching device is electrically connected with the first end of the first voltage regulator module;
a gate of the eighth switching device is electrically connected with a pull-up point of a previous stage shift temporary storage unit, a drain of the eighth switching device is electrically connected with a source of the seventh switching device, and the source of the eighth switching device is electrically connected with the low level signal source;
a gate of the ninth switching device is electrically connected with a pull-up point of a previous stage shift temporary storage unit, a drain of the ninth switching device is electrically connected with a gate of the seventh switching device, and a source of the ninth switching device is electrically connected with the low level signal source;
a tenth switching device, a gate of which is electrically connected to the pull-up point of the shift register unit of the current stage, a drain of which is electrically connected to a source of the seventh switching device, and a source of which is electrically connected to the low level signal source;
and a grid electrode of the eleventh switching device is electrically connected with a pull-up point of the current-stage shift temporary storage unit, a drain electrode of the eleventh switching device is electrically connected with a grid electrode of the seventh switching device, and a source electrode of the eleventh switching device is electrically connected with the low-level signal source.
5. The shift register circuit of claim 1, wherein the charging module comprises a twelfth switching device, a gate of the twelfth switching device is electrically connected to the feedback signal output terminal of the previous stage shift register unit, a drain of the twelfth switching device is electrically connected to the gate of the twelfth switching device or a high level signal source, and a source of the twelfth switching device is electrically connected to the pull-up point of the present stage shift register unit.
6. The shift register circuit as claimed in claim 1, wherein the output module includes a tenth switching device, a gate of the tenth switching device is electrically connected to the pull-up point of the shift register unit of the current stage, a drain of the tenth switching device is electrically connected to the clock signal source of the current stage, and a source of the tenth switching device is electrically connected to the scan signal output terminal of the shift register unit of the current stage.
7. The shift register circuit as claimed in claim 6, wherein the output module further includes a fourteenth switching device, a gate of the fourteenth switching device is electrically connected to the pull-up point of the shift register unit of the current stage, a drain of the fourteenth switching device is electrically connected to the clock signal source of the current stage, and a source of the fourteenth switching device is electrically connected to the feedback signal output terminal of the shift register unit of the current stage.
8. The shift register circuit of claim 1, wherein the reset module comprises:
a gate of the fifteenth switching device is electrically connected with a pull-down point of the current-stage shift temporary storage unit, a drain of the fifteenth switching device is electrically connected with a scanning signal output end of the current-stage shift temporary storage unit, and a source of the fifteenth switching device is electrically connected with the low-level signal source;
a gate of the sixteenth switching device is electrically connected with a pull-down point of the shift temporary storage unit of the current stage, a drain of the sixteenth switching device is electrically connected with a pull-up point of the shift temporary storage unit of the current stage, and a source of the sixteenth switching device is electrically connected with the low level signal source;
the pull-down point of the shift temporary storage unit at the current stage is electrically connected with the feedback signal output end of the shift temporary storage unit at the later stage.
9. A display device, characterized in that the display device comprises:
a display panel; and
a driving unit comprising the shift register circuit according to any one of claims 1 to 8, wherein the shift register circuit is a gate driver integrated circuit on an array substrate.
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| CN109448657A (en) * | 2018-12-26 | 2019-03-08 | 惠科股份有限公司 | Shift register and gate drive circuit |
| CN109859701B (en) * | 2018-12-26 | 2020-12-22 | 惠科股份有限公司 | Shift register and gate drive circuit |
| CN109448656B (en) * | 2018-12-26 | 2021-01-26 | 惠科股份有限公司 | Shift register and gate drive circuit |
| TWI695362B (en) * | 2019-01-14 | 2020-06-01 | 友達光電股份有限公司 | Light-emitting control circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680450A (en) * | 2013-12-18 | 2014-03-26 | 友达光电股份有限公司 | Drive circuit capable of achieving two-way transmission of signals and shifting register thereof |
| CN107016973A (en) * | 2017-05-05 | 2017-08-04 | 惠科股份有限公司 | Shift register circuit and display panel using same |
| CN107221299A (en) * | 2017-07-12 | 2017-09-29 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| CN107492361A (en) * | 2017-09-26 | 2017-12-19 | 惠科股份有限公司 | Shift register circuit and display panel using same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI400686B (en) * | 2009-04-08 | 2013-07-01 | Au Optronics Corp | Shift register of lcd devices |
-
2018
- 2018-08-13 CN CN201810925485.3A patent/CN108986732B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680450A (en) * | 2013-12-18 | 2014-03-26 | 友达光电股份有限公司 | Drive circuit capable of achieving two-way transmission of signals and shifting register thereof |
| CN107016973A (en) * | 2017-05-05 | 2017-08-04 | 惠科股份有限公司 | Shift register circuit and display panel using same |
| CN107221299A (en) * | 2017-07-12 | 2017-09-29 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| CN107492361A (en) * | 2017-09-26 | 2017-12-19 | 惠科股份有限公司 | Shift register circuit and display panel using same |
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| CN108986732A (en) | 2018-12-11 |
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