CN108962121B - Shift register circuit and display device - Google Patents
Shift register circuit and display device Download PDFInfo
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- CN108962121B CN108962121B CN201810920993.2A CN201810920993A CN108962121B CN 108962121 B CN108962121 B CN 108962121B CN 201810920993 A CN201810920993 A CN 201810920993A CN 108962121 B CN108962121 B CN 108962121B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention discloses a shift register circuit and a display device. The shift temporary storage circuit comprises a plurality of cascaded shift temporary storage units, each shift temporary storage unit comprises a reset module, a reset signal input end of each reset module is electrically connected with a pull-up point of a rear-stage shift temporary storage unit, and when the pull-up point of the rear-stage shift temporary storage unit and a scanning signal output end are reset, the pull-up signal of the pull-up point of the rear-stage shift temporary storage unit is in a high-level state. The technical scheme of the invention is beneficial to reducing the reset time required by the shift register circuit and avoiding the display image abnormity caused by the trailing of the scanning signal.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register circuit and a display device.
Background
In order to adapt to the development of light weight, thin frame and low cost of the display device, Gate Drive on Array (GOA) is generally adopted to output the line scanning signals, and specifically, the shift register circuit is integrated on the Array substrate of the display device. The shift temporary storage circuit comprises a plurality of stages of shift temporary storage units which are arranged in a cascade mode, and a pull-up point and a scanning signal output end of each stage of shift temporary storage unit are reset to be in a low level state under the action of a scanning signal output by the next stage of shift temporary storage unit. However, the high level of the scan signal output by the post-stage shift register unit is limited, which often results in a long reset time required by the pull-up point and the scan signal output terminal, and when the reset is insufficient, the scan signal generated by the post-stage shift register unit will be trailing, that is, the scan signal cannot be completely turned off, thereby resulting in an abnormal display image.
Disclosure of Invention
The present invention is directed to a shift register circuit, which solves the technical problem of long reset time required in the shift register circuit, and avoids trailing of scanning signals, thereby avoiding an abnormal display image and improving the display effect of a display device.
In order to achieve the above object, the shift register circuit provided by the present invention includes a plurality of cascaded shift register units, each of the shift register units includes a reset module, a reset signal input terminal of the reset module is electrically connected to a pull-up point of a next-stage shift register unit, and when the pull-up point of the current-stage shift register unit and a scan signal output terminal are reset, a pull-up signal of the pull-up point of the next-stage shift register unit is in a high level state.
Optionally, the reset module includes a first switch device and a second switch device, a gate of the first switch device is electrically connected to the reset signal input terminal, a drain of the first switch device is electrically connected to the scan signal output terminal of the shift register unit of the current stage, and a source of the first switch device is electrically connected to the low level signal source; the grid electrode of the second switch device is electrically connected with the reset signal input end, the drain electrode of the second switch device is electrically connected with the pull-up point of the shift temporary storage unit at the current stage, and the source electrode of the second switch device is electrically connected with the low-level signal source.
Optionally, the shift temporary storage unit further includes a charging module, the charging module includes a third switching device, a gate of the third switching device is electrically connected to the precharge signal source, a drain of the third switching device is electrically connected to the scan signal output end or the high level signal source of the preceding stage shift temporary storage unit, and a source of the third switching device is electrically connected to the pull-up point of the present stage shift temporary storage unit.
Optionally, the precharge signal of the precharge signal source includes a scan signal output by a scan signal output terminal of the pre-stage shift register unit; or the pre-charging signal of the pre-charging signal source comprises a pull-up signal of a pull-up point of the pre-stage shift register unit.
Optionally, the charging module further includes a fourth switching device, a gate of the fourth switching device is electrically connected to the pull-up point of the pre-stage shift temporary storage unit, a drain of the fourth switching device is electrically connected to a source of the third switching device, and the source of the fourth switching device is electrically connected to the pull-up point of the present-stage shift temporary storage unit.
Optionally, the shift temporary storage unit further includes an output module, the output module includes a fifth switching device, a gate of the fifth switching device is electrically connected to the pull-up point of the shift temporary storage unit of the current stage, a drain of the fifth switching device is electrically connected to the clock signal source, and a source of the fifth switching device is electrically connected to the scan signal output terminal of the shift temporary storage unit of the current stage.
Optionally, the shift register unit further includes a coupling capacitor, and the coupling capacitor is connected between the pull-up point of the shift register unit and the scan signal output end.
Optionally, the shift temporary storage unit further includes a voltage stabilizing module, a first end of the voltage stabilizing module is electrically connected to a voltage stabilizing signal source, a second end of the voltage stabilizing module is electrically connected to the scanning signal output end of the shift temporary storage unit of the current stage, a third end of the voltage stabilizing module is electrically connected to a pull-up point of the shift temporary storage unit of the current stage, a fourth end of the voltage stabilizing module is electrically connected to the low level signal source, and the voltage stabilizing module pulls down the scanning signal output end and the pull-up point to a low level state under the control of the voltage stabilizing signal.
In order to achieve the above object, the present invention further provides a shift register circuit, where the shift register circuit includes cascaded multiple stages of shift register units, and the shift register unit includes a charging module, an output module, a reset module, and a voltage stabilizing module, where: the reset signal input end of the reset module is electrically connected with the pull-up point of the rear-stage shift temporary storage unit, and when the pull-up point of the current-stage shift temporary storage unit and the scanning signal output end are reset, the pull-up signal of the pull-up point of the rear-stage shift temporary storage unit is in a high-level state.
In order to achieve the above object, the present invention further provides a display device, where the display device includes a display panel and a driving unit, the driving unit includes a shift register circuit, the shift register circuit includes multiple stages of shift register units arranged in a cascade manner, the shift register unit includes a reset module, a reset signal input end of the reset module is electrically connected to a pull-up point of a next-stage shift register unit, when a pull-up point and a scan signal output end of the current-stage shift register unit are reset, a pull-up signal of the pull-up point of the next-stage shift register unit is in a high-level state, and the shift register circuit is an array substrate gate drive integrated circuit; or the shift temporary storage circuit comprises a plurality of cascade-arranged shift temporary storage units, and each shift temporary storage unit comprises a charging module, an output module, a reset module and a voltage stabilizing module, wherein: the reset signal input end of the reset module is electrically connected with the pull-up point of the rear-stage shift temporary storage unit, and when the pull-up point of the current-stage shift temporary storage unit and the scanning signal output end are reset, the pull-up signal of the pull-up point of the rear-stage shift temporary storage unit is in a high-level state.
In the technical scheme of the invention, the shift temporary storage circuit comprises a plurality of stages of shift temporary storage units which are arranged in a cascade mode, and each shift temporary storage unit comprises a reset module which is used for resetting a pull-up point and a scanning signal output end of the shift temporary storage unit at the current stage. The reset signal input end of the reset module is electrically connected with the pull-up point of the rear-stage shift temporary storage unit, and when the pull-up point of the current-stage shift temporary storage unit and the scanning signal output end are reset, the pull-up signal of the pull-up point of the rear-stage shift temporary storage unit is in a high level state. Because the high level of the pull-up signal of the rear-stage shift temporary storage unit is about twice as large as the secondary high level of the pull-up signal or the high level of the scanning signal, the pull-up signal of the rear-stage shift temporary storage unit is adopted as the reset signal of the shift temporary storage unit, the reduction of the required reset time is facilitated, the scanning signal generated by the shift temporary storage unit is rapidly turned off, the tailing is avoided, and the display effect of the display device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a circuit diagram illustrating an exemplary nth shift register unit of a shift register circuit;
FIG. 2 is a timing diagram of an exemplary 4CK shift register circuit;
FIG. 3 is a schematic structural diagram of a display device according to an embodiment of the present invention;
FIG. 4 is a block diagram of an nth shift register unit according to an embodiment of the shift register circuit of the present invention;
FIG. 5 is a schematic circuit diagram of an nth shift register unit according to another embodiment of the shift register circuit of the present invention;
FIG. 6 is a timing diagram of the 4CK shift register circuit of the present invention;
fig. 7 is a circuit diagram of an nth shift register unit according to another embodiment of the shift register circuit of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Fig. 1 is a schematic block diagram of an nth stage shift register unit of an exemplary shift register circuit, where the shift register unit includes a charging module 111 ', an output module 112 ', and a reset module 113 ', and the charging module 111 ' pre-charges a pull-up point of the shift register unit, where a pull-up signal corresponding to the pull-up point is PU ' (n), i is a positive integer, and a specific value of i is related to a timing sequence in the shift register circuit. The output module 112 'generates the high level of the present stage scanning signal G' (n) under the action of the pull-up signal PU '(n) and the clock signal CK' (n). The reset module 113 ' includes a switch device T1 ' and a switch device T2 ', gates of the switch device T1 ' and the switch device T2 ' are electrically connected to a scan signal output terminal of the next-stage shift register unit, when the next-stage scan signal G ' (n + i) is in a high level state, the switch device T1 ' and the switch device T2 ' are in a conducting state, and reset of a pull-up point and the scan signal output terminal of the current-stage shift register unit is realized under the action of a level signal VSS ' output by a low level signal source. FIG. 2 is a timing diagram of the 4CK shift register circuit. Taking the case of resetting the first stage shift register unit as an example, after the high level of the first stage scan signal G '(1) is generated, the second stage scan signal G' (2) is in the high level state, so that the switching device T1 'and the switching device T2' are turned on, and under the action of the low level signal VSS 'generated by the low level signal source, the pull-up point and the scan signal output terminal of the first stage shift register unit are reset to the low level state, so that the first stage scan signal G' (1) is reset to the low level state. However, since the high level of the scan signal G '(n + i) in the next stage is limited, the reset time required by the pull-up point and the scan signal output terminal is often long, and when the reset is insufficient, the scan signal generated by the output module 112' will be smeared, that is, the scan signal cannot be completely turned off, thereby causing an abnormal display.
The invention provides a shift register circuit, which aims to solve the problems that the reset time required in a display device is long and the generated scanning signals are trailing, avoid the abnormity of a display picture and improve the display effect of the display device. In an embodiment of the present invention, as shown in fig. 3 and 4, the shift register circuit includes a plurality of cascaded shift register units, each of the shift register units includes a reset module 113, a reset signal input terminal of the reset module 113 is electrically connected to a pull-up point of a next shift register unit, and when the pull-up point and the scan signal output terminal of the current shift register unit are reset, a pull-up signal at the pull-up point of the next shift register unit is in a high level state.
Hereinafter, a liquid crystal display device will be taken as an example to describe the embodiments of the present invention in detail. As shown in fig. 3, the display device includes a display panel including an array substrate 100, a color filter substrate 200, and liquid crystal (not shown) filled between the array substrate 100 and the color filter substrate 200. The display panel is provided with a plurality of pixels arranged in a rectangular array, each pixel generally includes a plurality of sub-pixels, the array substrate 100 is provided with a switching device corresponding to each sub-pixel, and the color filter substrate 200 is provided with a color filter block corresponding to each sub-pixel. Under the control of the switching device on the array substrate 100, the liquid crystal in the region corresponding to each sub-pixel is deflected at a certain angle to realize the display of a specific image. In the display device with the GOA architecture, a shift register circuit 110 is further disposed on the array substrate 100 for driving each row of sub-pixels. The shift register circuit 110 is directly integrated on the array substrate 100 through a micro-processing process, so that an external shift register circuit is omitted, the material cost and the process cost of the display device are reduced, and the light, thin and narrow frame design of the display device is facilitated. The switching devices on the array substrate 100 and the switching devices in the shift register circuit 110 may be n-type thin film transistors, which will be described as an example later.
The shift register circuit 110 is developed based on the thompson circuit, and includes a plurality of stages of shift register units arranged in a cascade manner, wherein a first feedback signal output by a preceding stage of shift register unit can be used as a pre-charge signal of the present stage of shift register unit, a second feedback signal output by a following stage of shift register unit can be used as a reset signal of the present stage of shift register unit, and a cascade relationship between the shift register units of each stage is related to a time sequence in the shift register circuit, which is not described herein again. In particular, for the first stage of shift register unit, the separately provided start signal may be used as its precharge signal, and for the last stage of shift register unit, a redundant shift register unit may be provided to provide it with a reset signal.
In each stage of shift register unit, as shown in fig. 4, a first end of the charging module 111 receives the precharge signal st (n), a second end of the charging module 111 is connected to a first end of the output module 112, and a pull-up point of the shift register unit is located between the charging module 111 and the output module 112, where a pull-up signal corresponding to the pull-up point is denoted by pu (n). The second end of the output module 112 receives the clock signal ck (n), and it should be noted that in the shift register circuit, the same clock signal is often used to control multiple stages of shift register units, for example, for a TCK shift register circuit, the T-th stage clock signal will control the T + Tm stage of shift register units, where m is an integer greater than or equal to zero, and T is the total number of clock signal sources. The third terminal of the output module 112 outputs a scan signal g (n), wherein the scan signal g (n) is used to drive the corresponding sub-pixel row. The first end of the reset module 113 is connected to the pull-up point of the current stage of the shift register unit, the second end of the reset module 113 is connected to the third end of the output module 112, the third end of the reset module 113 is connected to the low level signal source, and the fourth end of the reset module 113 receives the reset signal pd (n) of the current stage of the shift register unit. Under the control of the reset signal pd (n), the reset module 113 is turned on or off, and when the reset module 113 is in an on state, the low level signal VSS output by the low level signal source pulls down the pull-up point and the scan signal output end of the shift register unit of the current stage to reset to a low level, so that the scan signal is reset to an off state after being turned on, thereby implementing the progressive scan driving.
In order to reduce the reset time required for resetting the scan signal to the off state, the pull-up signal PU (n + j) at the pull-up point of the next stage of shift register unit is used as the second feedback signal, i.e. the reset signal pd (n) of the present stage of shift register unit. When the pull-up signal PU (n + j) is in a high level state, the reset module 113 is turned on, and the pull-up point and the scan signal output end of the shift register unit of the current stage are pulled down and reset to a low level state under the action of the low level signal VSS output by the low level signal source. Because the high level of the pull-up signal PU (n + j) is usually twice as high as the second high level of the pull-up signal or the high level of the scan signal, the pull-up signal PU (n + j) is used as the reset signal, which is beneficial to optimizing the conduction performance of the reset module 113, so that the pull-up point and the scan signal output end discharge rapidly, the required reset time is reduced, thereby avoiding the scan signal from trailing, and improving the display effect of the display device.
In this embodiment, the shift register circuit includes a plurality of cascaded shift register units, and the shift register unit includes a reset module 113 to reset the pull-up point and the scan signal output terminal of the shift register unit to a low level state. The reset signal input terminal of the reset module 113 is electrically connected to the pull-up point of the next-stage shift register unit, and when the pull-up point of the current-stage shift register unit and the scan signal output terminal are reset, the pull-up signal of the pull-up point of the next-stage shift register unit is in a high level state. Because the high level of the pull-up signal of the rear-stage shift temporary storage unit is about twice the high level of the scanning signal, the pull-up signal of the rear-stage shift temporary storage unit is adopted as the reset signal of the shift temporary storage unit, so that the reduction of the required reset time is facilitated, the scanning signal generated by the shift temporary storage unit is rapidly turned off, the tailing is avoided, and the display effect of the display device is improved.
Based on the above embodiments, in another embodiment of the present invention, as shown in fig. 5, the reset module includes a first switching device T1 and a second switching device T2, a gate of the first switching device T1 is electrically connected to the reset signal input terminal, a drain of the first switching device T1 is electrically connected to the scan signal output terminal of the shift register unit of the present stage, and a source of the first switching device T1 is electrically connected to the low-level signal source; the gate of the second switching device T2 is electrically connected to the reset signal input terminal, the drain of the second switching device T2 is electrically connected to the pull-up point of the current stage shift register unit, and the source of the second switching device T2 is electrically connected to the low level signal source.
Fig. 6 is a timing diagram of a specific example of a 4CK shift register circuit, where j is 1, that is, a pull-up signal of a shift register unit of a next stage is used as a reset signal of the shift register unit of the present stage. Taking the situation of resetting the first-stage scanning signal G (1) as an example, when the scanning signal output end of the first-stage shift temporary storage unit is reset, the pull-up signal PU (2) of the second-stage shift temporary storage unit is in a high level state, at this time, the first switch device T1 and the second switch device T2 are in a conducting state, correspondingly, the source and drain electrodes of the first switch device T1 are communicated, and the source and drain electrodes of the second switch device are communicated, so that the pull-up point of the first-stage shift temporary storage unit and the scanning signal output end are respectively pulled down by the low level signal VSS to be reset to a low level state. The high level of the pull-up signal is about twice as high as the secondary high level of the pull-up signal or the high level of the scanning signal, so that the reset time is favorably shortened, the pull-up signal and the scanning signal are quickly turned off, and the tailing is avoided. It should be noted that, due to the pull-up signal of the post-stage shift register unit, the pull-up signal PU (2) of the second stage shift register unit is also reset to the low level state after the high level, so as to reduce the interference between the signals and further optimize the display effect of the display device.
In this embodiment, as shown in fig. 5, the shift register unit further includes a charging module 111, the charging module 111 includes a third switching device T3, a gate of the third switching device T3 is electrically connected to the precharge signal source to receive the precharge signal st (n), a drain of the third switching device T3 is electrically connected to the scan signal output terminal of the previous stage shift register unit or the high level signal source to receive the scan signal G (n-p) of the previous stage shift register unit or the high level signal VDD output by the high level signal source, and a source of the third switching device T3 is electrically connected to the pull-up point of the current stage shift register unit. The specific value of p is related to the timing sequence in the shift register circuit, and is not described herein again. Under the action of the precharge signal st (n), the third switching device T3 is turned on or off. When the third switching device T3 is in the on state, the source and drain are connected, and the pull-up point of the current stage shift register unit is precharged by the previous stage scan signal G (n-p) or the high level signal VDD, so that the pull-up point of the current stage shift register unit reaches the next high level state.
In one embodiment, the precharge signal st (n) of the precharge signal source includes a scan signal output from a scan signal output terminal of the pre-stage shift register unit, that is, the scan signal of the pre-stage shift register unit is used as the first feedback signal to control the operation of the charging module 111. When the scan signal of the previous stage shift register unit is in a high level state, the third switching device T3 of the charging module 111 is turned on, and the scan signal G (n-p) or the high level signal VDD of the previous stage shift register unit precharges the pull-up point of the current stage shift register unit. Particularly, when the drain of the third switching device T3 is electrically connected to the high level signal source, since the waveform of the high level signal VDD is easier to control than that of the scan signal, the corresponding precharging effect on the pull-up point tends to be better.
In another embodiment, the precharge signal st (n) of the precharge signal source includes a pull-up signal of a pull-up point of the pre-stage shift register unit, that is, the pull-up signal of the pre-stage shift register unit is used as the first feedback signal to control the operation of the charging module 111. When the pull-up signal of the preceding stage shift register unit is in a high level state, the level of the pull-up signal is about twice as high as the second high level of the pull-up signal or the high level of the scan signal, so that the turn-on performance of the third switching device T3 is more optimized, the precharge time required for charging the pull-up point is reduced, and the waveform of the generated scan signal of the present stage is improved.
In another embodiment of the present invention, as shown in fig. 7, the charging module 111 further includes a fourth switching device T4, a gate of the fourth switching device T4 is electrically connected to the pull-up point of the previous stage shift register unit, a drain of the fourth switching device T4 is electrically connected to a source of the third switching device, and a source of the fourth switching device T4 is electrically connected to the pull-up point of the present stage shift register unit.
When the previous stage pull-up signal PU (n-q) is at a high level, the fourth switching device T4 is in a conducting state, and meanwhile, the third switching device T3 is also in a conducting state under the action of the precharge signal st (n), and the drain of the third switching device T3 is conducted with the pull-up point of the shift register unit of the current stage, so that the pull-up point is precharged under the action of the previous stage scan signal G (n-p) or the high level signal VDD. Because the fourth switching device T4 is opened more thoroughly under the action of the preceding stage pull-up signal PU (n-q), its turn-on performance is better, thereby facilitating to reduce the required charging time, improving the waveform of the generated scanning signal, and further improving the display effect of the display device. The specific values of p and q are related to the timing sequence in the shift register circuit, and are not described herein again.
In the above embodiments of the present invention, as shown in fig. 4, fig. 5 and fig. 7, the shift register unit further includes an output module 113, the output module 113 includes a fifth switching device T5, a gate of the fifth switching device T5 is electrically connected to a pull-up point of the shift register unit of the present stage, a drain of the fifth switching device T5 is electrically connected to the clock signal source, and a source of the fifth switching device T5 is electrically connected to a scan signal output terminal of the shift register unit of the present stage. When the fifth switching device T5 is turned on by the coupling of the pull-up signal pu (n) and the clock signal ck (n), the source-drain sets of the fifth switching device T5 are connected, so as to generate the high level of the scan signal g (n) by the high level of the clock signal ck (n).
In addition, as shown in fig. 5 and 7, the shift register unit further includes a coupling capacitor C connected between the pull-up point of the shift register unit and the scan signal output terminal. By providing the coupling capacitor C, the clock signal ck (n) is better coupled to the pull-up point of the shift register unit of the current stage, so as to further increase the level of the high level state of the pull-up signal pu (n), so that the turn-on performance of the fifth switching device T5 is better, and the waveform of the generated scan signal g (n) is optimized.
As shown in fig. 4, fig. 5 and fig. 7, in the above embodiment of the present invention, the shift register unit further includes a voltage stabilizing module 114, a first end of the voltage stabilizing module 114 is electrically connected to the voltage stabilizing signal source, a second end of the voltage stabilizing module 114 is electrically connected to the scan signal output end of the shift register unit of the current stage, a third end of the voltage stabilizing module 114 is electrically connected to the pull-up point of the shift register unit of the current stage, a fourth end of the voltage stabilizing module 114 is electrically connected to the low level signal source, and the voltage stabilizing module 114 resets the scan signal output end and the pull-up point to the low level state under the control of the voltage stabilizing signal, so as to eliminate the interference of the timing noise caused by the multi-.
Specifically, the voltage stabilizing module 114 includes a pull-down sub-module and a pull-down control sub-module, the pull-down sub-module is configured to maintain the pull-up point of the shift register unit and the scan signal output end at a low level state at a preset time, and the pull-down control sub-module is configured to control the operation of the pull-down sub-module. The entire voltage stabilizing module 114 can operate under the control of the low frequency voltage stabilizing signal to eliminate timing noise and improve the display effect of the display device.
Of course, the voltage regulation module 114 may also include a first voltage regulation sub-module and a second voltage regulation sub-module. The first end of the first voltage stabilizing submodule is electrically connected with a low-frequency voltage stabilizing signal source so as to receive a low-frequency voltage stabilizing signal P1 (n); the second end of the first voltage stabilizing submodule is electrically connected with the scanning signal output end of the current-stage shift temporary storage unit and pulls the scanning signal output end down to a low level; the third end of the first voltage stabilizing submodule is electrically connected with a pull-up point of the current-stage shift temporary storage unit so as to pull down the pull-up point to a low level; and the fourth end of the first voltage stabilizing sub-module is electrically connected with a low-level signal source so as to receive a low-level signal VSS. When a low-frequency voltage-stabilizing signal P1(n) generated by the low-frequency voltage-stabilizing signal source is at a high level, the first voltage-stabilizing submodule is communicated with the pull-up point, the scanning signal output end and the low-level signal source so as to eliminate timing noise of the pull-up point and the scanning signal output end. Similarly, the first end of the second voltage-stabilizing submodule is electrically connected with the high-frequency voltage-stabilizing signal source to receive a high-frequency voltage-stabilizing signal P2 (n); the second end of the second voltage stabilizing submodule is electrically connected with the scanning signal output end of the current-stage shift temporary storage unit and pulls the scanning signal output end down to a low level; the third end of the second voltage stabilizing submodule is electrically connected with the pull-up point of the current-stage shift temporary storage unit so as to pull down the pull-up point to a low level; and the fourth end of the second voltage stabilizing sub-module is electrically connected with the low-level signal source so as to receive the low-level signal VSS. When a high-frequency voltage-stabilizing signal P2(n) generated by the high-frequency voltage-stabilizing signal source is at a high level, the second voltage-stabilizing submodule is communicated with the pull-up point, the scanning signal output end and the low-level signal source so as to eliminate timing noise of the pull-up point and the scanning signal output end. By designing the corresponding time sequences of the low-frequency voltage-stabilizing signal P1(n) and the high-frequency voltage-stabilizing signal P2(n), the low-frequency voltage-stabilizing signal P1(n) and the high-frequency voltage-stabilizing signal P2(n) are both in a high level state at the moment when timing noise possibly occurs in the shift register unit, so that the scanning signal output end and the pull-up point are pulled down to a low level state, rapid discharge of the scanning signal output end and the pull-up point is realized, the timing noise is thoroughly eliminated, and the normal operation of the display device is guaranteed.
The present invention further provides a display device, as shown in fig. 3, the display device includes a display panel and a driving unit, the driving unit is configured to drive the display of the display panel, the driving unit includes a shift register circuit 110, and the specific structure of the shift register circuit 110 refers to the above embodiments. The shift register circuit is a gate drive integrated circuit on the array substrate, so that material cost and process cost are reduced, and meanwhile, the light and thin and narrow frame of the display device are realized.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. A shift temporary storage circuit is characterized by comprising a plurality of stages of shift temporary storage units which are arranged in a cascade mode, wherein each shift temporary storage unit comprises a reset module, a reset signal input end of each reset module is electrically connected with a pull-up point of a next-stage shift temporary storage unit, and when the pull-up point of the current-stage shift temporary storage unit and a scanning signal output end are reset, a pull-up signal of the pull-up point of the next-stage shift temporary storage unit is in a high level state;
the shift register unit further comprises a charging module, and the charging module comprises:
the grid electrode of the third switching device is electrically connected with a pre-charging signal source, the drain electrode of the third switching device is electrically connected with the scanning signal output end of the preceding stage shift temporary storage unit or the high-level signal source, and the source electrode of the third switching device is electrically connected with the pull-up point of the current stage shift temporary storage unit;
and the grid electrode of the fourth switching device is electrically connected with the pull-up point of the preceding stage shift temporary storage unit, the drain electrode of the fourth switching device is electrically connected with the source electrode of the third switching device, and the source electrode of the fourth switching device is electrically connected with the pull-up point of the current stage shift temporary storage unit.
2. The shift register circuit of claim 1, wherein the reset module comprises:
a grid electrode of the first switch device is electrically connected with the reset signal input end, a drain electrode of the first switch device is electrically connected with a scanning signal output end of the shift temporary storage unit at the current stage, and a source electrode of the first switch device is electrically connected with a low level signal source;
and the grid electrode of the second switching device is electrically connected with the reset signal input end, the drain electrode of the second switching device is electrically connected with the pull-up point of the shift temporary storage unit at the current stage, and the source electrode of the second switching device is electrically connected with the low-level signal source.
3. The shift register circuit of claim 1, wherein the pre-charge signal of the pre-charge signal source comprises a scan signal output from a scan signal output terminal of a preceding stage of the shift register unit; or the pre-charging signal of the pre-charging signal source comprises a pull-up signal of a pull-up point of the pre-stage shift register unit.
4. The shift register circuit of claim 1, wherein said shift register unit further comprises an output module, said output module comprising:
and a grid electrode of the fifth switching device is electrically connected with the pull-up point of the shift temporary storage unit at the current stage, a drain electrode of the fifth switching device is electrically connected with a clock signal source, and a source electrode of the fifth switching device is electrically connected with the scanning signal output end of the shift temporary storage unit at the current stage.
5. The shift register circuit of claim 1, wherein said shift register unit further comprises:
and the coupling capacitor is connected between the pull-up point of the shift temporary storage unit at the current stage and the scanning signal output end.
6. The shift register circuit of any of claims 1-5, wherein the shift register unit further comprises:
the first end of the voltage stabilizing module is electrically connected with a voltage stabilizing signal source, the second end of the voltage stabilizing module is electrically connected with the scanning signal output end of the current-stage shift temporary storage unit, the third end of the voltage stabilizing module is electrically connected with the pull-up point of the current-stage shift temporary storage unit, the fourth end of the voltage stabilizing module is electrically connected with a low level signal source, and the voltage stabilizing module pulls down the scanning signal output end and the pull-up point to a low level state under the control of a voltage stabilizing signal.
7. The utility model provides a shift temporary storage circuit, its characterized in that, shift temporary storage circuit is including the multistage shift temporary storage unit that cascades the setting, shift temporary storage unit is including charging module, output module, module and voltage stabilizing module reset, wherein:
the reset signal input end of the reset module is electrically connected with the pull-up point of the next-stage shift temporary storage unit, and when the pull-up point of the current-stage shift temporary storage unit and the scanning signal output end are reset, the pull-up signal of the pull-up point of the next-stage shift temporary storage unit is in a high level state;
the shift register unit further comprises a charging module, and the charging module comprises:
the grid electrode of the third switching device is electrically connected with a pre-charging signal source, the drain electrode of the third switching device is electrically connected with the scanning signal output end of the preceding stage shift temporary storage unit or the high-level signal source, and the source electrode of the third switching device is electrically connected with the pull-up point of the current stage shift temporary storage unit;
and the grid electrode of the fourth switching device is electrically connected with the pull-up point of the preceding stage shift temporary storage unit, the drain electrode of the fourth switching device is electrically connected with the source electrode of the third switching device, and the source electrode of the fourth switching device is electrically connected with the pull-up point of the current stage shift temporary storage unit.
8. A display device, characterized in that the display device comprises:
a display panel; and
the driving unit comprises the shift register circuit as claimed in any one of claims 1 to 7, wherein the shift register circuit is a gate driver integrated circuit on an array substrate.
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| CN109377934A (en) * | 2018-12-27 | 2019-02-22 | 厦门天马微电子有限公司 | Shift register cell, its driving method, gate driving circuit and display device |
| CN113948049B (en) * | 2021-09-28 | 2023-04-25 | 惠科股份有限公司 | Driving circuit, array substrate and display panel |
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| CN105528988A (en) * | 2016-02-15 | 2016-04-27 | 京东方科技集团股份有限公司 | Gate driving circuit, touch control display panel and display device |
| CN205595037U (en) * | 2016-05-13 | 2016-09-21 | 合肥鑫晟光电科技有限公司 | Shifting register, grid driving circuit and display device |
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| CN107833552B (en) * | 2017-11-17 | 2020-09-25 | 合肥鑫晟光电科技有限公司 | Gate driving unit, gate driving circuit, driving method of gate driving circuit and display device |
| CN107945759B (en) * | 2018-01-02 | 2021-01-22 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display device |
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| CN105528988A (en) * | 2016-02-15 | 2016-04-27 | 京东方科技集团股份有限公司 | Gate driving circuit, touch control display panel and display device |
| CN205595037U (en) * | 2016-05-13 | 2016-09-21 | 合肥鑫晟光电科技有限公司 | Shifting register, grid driving circuit and display device |
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