CN109377934A - Shift register cell, its driving method, gate driving circuit and display device - Google Patents
Shift register cell, its driving method, gate driving circuit and display device Download PDFInfo
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- CN109377934A CN109377934A CN201811610074.1A CN201811610074A CN109377934A CN 109377934 A CN109377934 A CN 109377934A CN 201811610074 A CN201811610074 A CN 201811610074A CN 109377934 A CN109377934 A CN 109377934A
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000010408 sweeping Methods 0.000 claims abstract description 51
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 230000004044 response Effects 0.000 claims description 23
- 230000008878 coupling Effects 0.000 claims description 17
- 238000010168 coupling process Methods 0.000 claims description 17
- 238000005859 coupling reaction Methods 0.000 claims description 17
- 239000000126 substance Substances 0.000 claims description 8
- 230000017105 transposition Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 25
- 230000005856 abnormality Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 17
- 239000013078 crystal Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000006073 displacement reaction Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
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- 101100443272 Arabidopsis thaliana DIR2 gene Proteins 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The invention discloses a kind of shift register cell, its driving method, gate driving circuit and display devices, when carrying out forward scan to display panel, using just sweeping input module to pull-up node input signal, pull-up node is resetted using reseting module is just swept, and the collective effect by output module and coupled capacitor, output end output signal can be made.When carrying out reverse scan to display panel, using anti-input module of sweeping to pull-up node input signal, sweeps reseting module using anti-pull-up node is resetted, and by the collective effect of output module and coupled capacitor, output end output signal can be made.Different input module and reseting module is respectively adopted when carrying out forward scan and reverse scan to display panel in this way, when pulling up node input signal, different signal circulation paths can be used, so as to avoid the problem that shift register cell is switched to the output abnormality occurred when reverse scan by forward scan.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of shift register cell, its driving method, gate driving
Circuit and display device.
Background technique
With the rapid development of display technology, display panel presents the development trend of high integration and low cost.Its
In, GOA (Gate Driver on Array, array substrate row driving) technology by TFT (Thin Film Transistor, it is thin
Film transistor) gate driving circuit is integrated in the array substrate of display panel to be formed to the turntable driving of display panel.Mesh
Before, GOA circuit is usually made of multiple cascade shift register cells, the signal output end point of shift register cells at different levels
Not Dui Ying a grid line, for successively to the grid line of connection input scanning signal.However, GOA circuit switches by forward scan
To when reverse scan, it may appear that the problem of output abnormality.
Summary of the invention
The embodiment of the present invention provides a kind of shift register cell, its driving method, gate driving circuit and display device,
To solve the problems, such as that GOA circuit is switched to the output abnormality occurred when reverse scan by forward scan.
Therefore, the embodiment of the invention provides a kind of shift register cells, comprising: is just sweeping input module, is just sweeping reset
Module counter sweep input module, counter sweeps reseting module, output module and coupled capacitor；Wherein, the coupled capacitor is connected to down
It draws between node and the first clock signal terminal；
The input module of just sweeping is configured to respond to first control signal and the first input signal, and described first is controlled
Signal processed is supplied to pull-up node；
The reseting module of just sweeping is configured to respond to the first control signal and the first reset signal, by the second control
Signal processed is supplied to the pull-up node；
The anti-input module of sweeping is configured to respond to the second control signal and the second input signal, by described
Two control signals are supplied to the pull-up node；
The anti-reseting module of sweeping is configured to respond to the second control signal and the second reset signal, by described
One control signal is supplied to the pull-up node；
The output module is configured to respond to the signal of the pull-up node and the pull-down node, exports signal
Hold output signal.
Correspondingly, the embodiment of the invention also provides a kind of driving methods of above-mentioned shift register cell, comprising:
Input phase in forward scan, the input module of just sweeping are believed in response to first control signal and the first input
Number, the first control signal is supplied to pull-up node；Reseting stage, the reseting module of just sweeping is in response to first control
Second control signal is supplied to the pull-up node by signal processed and the first reset signal；
Input phase in negative sense scanning, the anti-input module of sweeping is in response to the second control signal and described the
The second control signal is supplied to the pull-up node by two input signals；Reseting stage, the anti-reseting module of sweeping respond
In the second control signal and second reset signal, the first control signal is supplied to the pull-up node.
Correspondingly, the embodiment of the invention also provides a kind of gate driving circuits, comprising: cascade 1st to N displacement is posted
Storage unit；Wherein, N is positive integer, and each shift register cell is above-mentioned shift register cell；
First input signal of the 1st grade of shift register cell is just being swept trigger signal by first and is being provided；2nd grade of shift LD
First input signal of device unit is just being swept trigger signal by second and is being provided；Also, the first input of n-th grade of shift register cell
Signal is provided by the signal output end of the n-th -2 grades shift register cells；First reset signal of n-th grade of shift register cell
It is provided by the signal output end of the n-th+2 grades shift register cells；
Second input signal of N grades of shift register cells is provided by the first anti-trigger signal of sweeping；N-1 grades of displacements are posted
Second input signal of storage unit is provided by the second anti-trigger signal of sweeping；Also, the second of n-th grade of shift register cell is defeated
Enter signal to be provided by the signal output end of the n-th+2 grades shift register cells；The second of n-th grade of shift register cell resets letter
It number is provided by the signal output end of the n-th -2 grades shift register cells.
Correspondingly, the embodiment of the invention also provides a kind of display transposition, including above-mentioned gate driving circuit.
The present invention has the beneficial effect that:
Shift register cell, its driving method, gate driving circuit and display device provided in an embodiment of the present invention,
It, can be using just sweeping input module to pull-up node input signal, using just sweeping reset when carrying out forward scan to display panel
Module resets pull-up node, and by the collective effect of output module and coupled capacitor, output end can be made to export
Signal.It, can be using anti-input module of sweeping to pull-up node input signal, using anti-when carrying out reverse scan to display panel
It sweeps reseting module to reset pull-up node, and by the collective effect of output module and coupled capacitor, can make to export
Hold output signal.Display panel is being carried out that different input modules is respectively adopted when forward scan and reverse scan and answered in this way
Position module, different signal circulation paths can be used when pulling up node input signal, so as to avoid displacement from posting
The problem of storage unit is switched to the output abnormality occurred when reverse scan by forward scan.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of shift register cell in the related technology；
Fig. 2 is the circuit timing diagram of shift register cell shown in FIG. 1；
Fig. 3 is the structural schematic diagram of the shift register cell in the embodiment of the present invention；
Fig. 4 is one of the concrete structure schematic diagram of shift register cell in the embodiment of the present invention；
Fig. 5 is the circuit timing diagram of shift register cell shown in Fig. 4；
Fig. 6 is the two of the concrete structure schematic diagram of the shift register cell in the embodiment of the present invention；
Fig. 7 is the circuit timing diagram of shift register cell shown in fig. 6；
Fig. 8 is the three of the concrete structure schematic diagram of the shift register cell in the embodiment of the present invention；
Fig. 9 is the circuit timing diagram of shift register cell shown in Fig. 8；
Figure 10 is one of the structural schematic diagram of gate driving circuit in the embodiment of the present invention；
Figure 11 is the second structural representation of the gate driving circuit in the embodiment of the present invention；
Figure 12 is the third structural representation of the gate driving circuit in the embodiment of the present invention；
Figure 13 is the structural schematic diagram of the display device in the embodiment of the present invention.
Specific embodiment
In order to make the purpose of the present invention, the technical scheme and advantages are more clear, with reference to the accompanying drawing, to the embodiment of the present invention
The shift register cell of offer, its driving method, gate driving circuit and display device specific embodiment carry out it is detailed
Ground explanation.It should be appreciated that preferred embodiment disclosed below is merely to illustrate and explain the present invention, it is not used to limit this hair
It is bright.And in the absence of conflict, the features in the embodiments and the embodiments of the present application can be combined with each other.It should be noted that
, each figure and shape do not reflect actual proportions in attached drawing, and purpose is schematically illustrate the content of present invention.And from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.
As shown in Figure 1, shift register cell may include transistor M01~M07 and capacitor C01~C02.Fig. 1 institute
For the shift register cell shown in forward scan, corresponding timing diagram is as shown in Figure 2.Specifically, in input phase T1, due to
Signal RE is low level signal, therefore transistor M02 ends.Since clock signal CK is high level signal, transistor M07
It is connected and low level signal VGL is supplied to signal output end OUT, signal output end OUT is made to export low level signal.Due to defeated
Entering signal INPUT is high level signal, therefore transistor M01 is connected, and the signal DIR1 of high level is supplied to pull-up node
PU, so that the signal of pull-up node PU is high level signal, to control transistor M04, M05 conducting.The transistor M04 of conducting
Low level signal VGL is supplied to pull-down node PD, so that the signal of pull-down node PD is low level signal, to control crystal
Pipe M03, M06 cut-off.Low level clock signal CKB is supplied to signal output end OUT by the transistor M05 of conducting, so that letter
Number output end OUT exports low level signal.
In output stage T2, since signal RE is low level signal, transistor M02 cut-off.Due to clock signal CK
For low level signal, therefore transistor M07 ends.Since input signal INPUT is low level signal, transistor M01 is cut
Only.It is high level signal since capacitor C01 effect can keep the signal of pull-up node PU, to control transistor M04, M05
Conducting.The clock signal CKB of high level is supplied to signal output end OUT by the transistor M05 of conducting, so that signal output end
OUT exports high level signal, and due to the effect of capacitor C01, pull-up node PU is further pulled up, so that the crystal of conducting
The clock signal CKB of high level is supplied to signal output end OUT by pipe M05.The transistor M04 of conducting is by low level signal VGL
It is supplied to pull-down node PD, so that the signal of pull-down node PD is low level signal, to control transistor M03, M06 cut-off.
In reseting stage T3, since input signal INPUT is low level signal, transistor M01 cut-off.Due to signal
RE is high level signal, therefore transistor M02 is connected and low level signal DIR2 is supplied to pull-up node PU, so that pull-up
The signal of node PU is low level signal, to control transistor M04, M05 cut-off.Since clock signal CK is high level letter
Number, therefore transistor M07 is connected and low level signal VGL is supplied to signal output end OUT, exports signal output end OUT
Low level signal.
When shift register cell shown in Fig. 1 carries out reverse scan, by the function of transistor M01 and transistor M02
It is interchangeable.That is, will be drawn high pull-up node PU using transistor M02 in the input phase T1 of reverse scan,
In reseting stage T3, pull-up node PU will be dragged down using transistor M01.However, due to the reseting stage T3 in forward scan
In, there is biggish positive gate source voltage Vgs between the grid and source electrode of transistor M02, to will lead to the threshold value of transistor M02
Voltage Vth positive excursion.In this way when being switched to reverse scan after forward scan is complete, in the input phase T1 of reverse scan,
It will lead to transistor M02 to open not exclusively, or even cannot normally open.Pull-up node PU will be will lead in this way to be charged to
Given voltage opens exception so as to cause transistor M05, and then leads to signal output abnormality.Especially carried out just in long-time
When being switched to reverse scan after to scanning, the problem is more serious.
Based on this, the embodiment of the invention provides a kind of shift register cell, the problem of for improving output abnormality.
As shown in figure 3, shift register cell provided in an embodiment of the present invention may include: just to sweep input module 10, just
Reseting module 20 is swept, anti-input module 30 swept, counter sweeps reseting module 40, output module 50 and coupled capacitor CF；Wherein, it couples
Capacitor CF is connected between pull-down node PD and the first clock signal terminal CK1；Wherein,
It is just sweeping input module 10 and is being configured to respond to first control signal DR1 and the first input signal INPUT1, by
One control signal DR1 is supplied to pull-up node PU；
It is just sweeping reseting module 20 and is being configured to respond to first control signal DR1 and the first reset signal RE1, by the second control
Signal DR2 processed is supplied to pull-up node PU；
Anti- input module 30 of sweeping is configured to respond to second control signal DR2 and the second input signal INPUT2, by
Two control signal DR2 are supplied to pull-up node PU；
Anti- reseting module 40 of sweeping is configured to respond to second control signal DR2 and the second reset signal RE2, by the first control
Signal DR1 processed is supplied to pull-up node PU；
Output module 50 is configured to respond to the signal of pull-up node PU and pull-down node PD, makes signal output end OUT
Output signal.
Above-mentioned shift register cell provided in an embodiment of the present invention can be with when carrying out forward scan to display panel
Using input module is just swept to pull-up node input signal, pull-up node is resetted using reseting module is just swept, Yi Jitong
The collective effect of output module and coupled capacitor is crossed, output end output signal can be made.Reverse scan is being carried out to display panel
When, it can sweep reseting module using counter using counter input module of sweeping to pull-up node input signal pull-up node is resetted,
And the collective effect by output module and coupled capacitor, output end output signal can be made.In this way to display panel into
Different input module and reseting module are respectively adopted when row forward scan and reverse scan, to pull up node input signal
When, different signal circulation paths can be used, so as to avoid shift register cell from being switched to reversely by forward scan
The problem of output abnormality occurred when scanning.
Combined with specific embodiments below, the present invention is described in detail.It should be noted that be in the present embodiment in order to
It preferably explains the present invention, but does not limit the present invention.
Embodiment one,
In the specific implementation, in embodiments of the present invention, as shown in figure 4, just sweeping input module 10 may include: the first crystalline substance
Body pipe M1 and second transistor M2；Wherein,
The grid of the first transistor M1 is for receiving first control signal DR1, and the first pole of the first transistor M1 is for connecing
The first input signal INPUT1 is received, the second pole of the first transistor M1 and the grid of second transistor M2 couple；
The first pole of second transistor M2 for receiving first control signal DR1, the second pole of second transistor M2 with it is upper
Draw node PU coupling.
In the specific implementation, in embodiments of the present invention, the first transistor M1 is under the control of first control signal DR1
When on state, the first input signal INPUT1 can be supplied to the grid of second transistor M2.Second transistor M2 exists
When in the conductive state under the control of the signal of its grid, first control signal DR1 can be supplied to pull-up node PU, with control
The signal of pull-up node PU processed.
In the specific implementation, in embodiments of the present invention, as shown in figure 4, just sweeping reseting module 20 may include: third crystalline substance
Body pipe M3 and the 4th transistor M4；Wherein,
The grid of third transistor M3 is for receiving first control signal DR1, and the first pole of third transistor M3 is for connecing
The first reset signal RE1 is received, the second pole of third transistor M3 and the grid of the 4th transistor M4 couple；
The first pole of 4th transistor M4 for receiving second control signal DR2, the second pole of the 4th transistor M4 with it is upper
Draw node PU coupling.
In the specific implementation, in embodiments of the present invention, third transistor M3 is under the control of first control signal DR1
When on state, the first reset signal RE1 can be supplied to the grid of the 4th transistor M4.4th transistor M4 is in its grid
When in the conductive state under the control of the signal of pole, second control signal DR2 can be supplied to pull-up node PU, in control
Draw the signal of node PU.
In the specific implementation, in embodiments of the present invention, as shown in figure 4, anti-input module 30 of sweeping may include: the 5th crystalline substance
Body pipe M5 and the 6th transistor M6；Wherein,
The grid of 5th transistor M5 is for receiving second control signal DR2, and the first pole of the 5th transistor M5 is for connecing
The grid of the second pole and the 6th transistor M6 of receiving the second input signal INPUT2, the 5th transistor M5 couples；
The first pole of 6th transistor M6 for receiving second control signal DR2, the second pole of the 6th transistor M6 with it is upper
Draw node PU coupling.
In the specific implementation, in embodiments of the present invention, the 5th transistor M5 is under the control of second control signal DR2
When on state, the second input signal INPUT can be supplied to the grid of the 6th transistor M6.6th transistor M6 is at it
When in the conductive state under the control of the signal of grid, second control signal DR2 can be supplied to pull-up node PU, with control
The signal of pull-up node PU.
In the specific implementation, in embodiments of the present invention, as shown in figure 4, anti-reseting module 40 of sweeping may include: the 7th crystalline substance
Body pipe M7 and the 8th transistor M8；Wherein,
The grid of 7th transistor M7 is for receiving second control signal DR2, and the first pole of the 7th transistor M7 is for connecing
The grid of the second pole and the 8th transistor M8 of receiving the second reset signal RE2, the 7th transistor M7 couples；
The first pole of 8th transistor M8 for receiving first control signal DR1, the second pole of the 8th transistor M8 with it is upper
Draw node PU coupling.
In the specific implementation, in embodiments of the present invention, the 7th transistor M7 is under the control of second control signal DR2
When on state, the second reset signal RE2 can be supplied to the grid of the 8th transistor M8.8th transistor M8 is in its grid
When in the conductive state under the control of the signal of pole, first control signal DR1 can be supplied to pull-up node PU, in control
Draw the signal of node PU.
In the specific implementation, in embodiments of the present invention, as shown in figure 4, output module 50 may include: output control
Module 51 and signal output sub-module 52；Wherein,
Output control submodule 51 is configured to respond to the signal of pull-up node PU, and reference signal VREF is supplied to down
Node PD is drawn, and in response to the signal of pull-down node PD, reference signal VREF is supplied to pull-up node PU.
Signal output sub-module 52 provides the signal of the first clock signal terminal CK1 in response to the signal of pull-up node PU
Signal output end OUT is given, and in response to the signal of pull-down node PD, reference signal VREF is supplied to signal output end OUT.
In the specific implementation, in embodiments of the present invention, as shown in figure 4, output control submodule 51 may include: the 9th
Transistor M9 and the tenth transistor M10；
The grid and pull-up node PU of 9th transistor M9 couples, and the first pole of the 9th transistor M9 is for receiving with reference to letter
The second pole of number VREF, the 9th transistor M9 and pull-down node PD are coupled；
The grid and pull-down node PD of tenth transistor M10 couples, and the first pole of the tenth transistor M10 is for receiving reference
The second pole of signal VREF, the tenth transistor M10 and pull-up node PU are coupled.
In the specific implementation, in embodiments of the present invention, the 9th transistor M9 is under the control of the signal of pull-up node PU
When in the conductive state, reference signal VREF can be supplied to pull-down node PD, to control the signal of pull-down node PD.Tenth
When transistor M10 is in the conductive state under the control of the signal of pull-down node PD, reference signal VREF can be supplied to
Node PU is drawn, to control the signal of pull-up node PU.
In the specific implementation, in embodiments of the present invention, as shown in figure 4, signal output sub-module 52 may include: the tenth
One transistor M11, the tenth two-transistor M12 and storage capacitance CT；Wherein,
The grid and pull-up node PU of 11st transistor M11 couples, when the first pole of the 11st transistor M11 is with first
Clock signal end CK1 coupling, the second pole of the 11st transistor M11 and signal output end OUT are coupled.
The grid and pull-down node PD of tenth two-transistor M12 couples, and the first pole of the tenth two-transistor M12 is for receiving
The second pole of reference signal VREF, the tenth two-transistor M12 and signal output end OUT are coupled.
Storage capacitance CT is connected between pull-up node PU and signal output end OUT.
In the specific implementation, in embodiments of the present invention, control of the 11st transistor M11 in the signal of pull-up node PU
Under it is in the conductive state when, the signal of the first clock signal terminal CK1 can be supplied to signal output end OUT, to control signal
The signal of output end OUT output.When tenth two-transistor M12 is in the conductive state under the control of the signal of pull-down node PD,
Reference signal VREF can be supplied to signal output end OUT, the signal exported with control signal output OUT.Storage capacitance
CT can save the voltage for being input to pull-up node PU Yu signal output end OUT.Also, floating is in pull-up node PU
When, storage capacitance CT can also make the voltage difference between pull-up node PU and signal output end OUT keep stablizing.
The above is only the specific structures for illustrating each module in shift register cell, in the specific implementation, above-mentioned each
The specific structure of module is not limited to above structure provided in an embodiment of the present invention, can also be skilled person will appreciate that its
His structure, is not limited thereto.
In the specific implementation, in embodiments of the present invention, above-mentioned transistor generally uses the transistor of same material.?
When it is implemented, the transistor in shift register cell can be N-type transistor, in embodiments of the present invention, carrying out just
To when scanning, the effective impulse signal of the first input signal can be high level signal, and first control signal can be high level
Signal, second control signal can be low level signal, and reference signal can be low level signal.When carrying out reverse scan,
The effective impulse signal of second input signal can be high level signal, first control signal can be low level signal, second
Controlling signal can be high level signal, and reference signal can be low level signal.
In the specific implementation, the transistor in shift register cell may be P-type transistor, in the embodiment of the present invention
In, when carrying out forward scan, the effective impulse signal of the first input signal can be low level signal, and first control signal can
Think low level signal, second control signal can be high level signal, and reference signal can be high level signal.It is carrying out instead
To when scanning, the effective impulse signal of the second input signal can be low level signal, and first control signal can be high level
Signal, second control signal can be low level signal, and reference signal can be high level signal.
Further, in the specific implementation, N-type transistor is connected under high level signal effect, makees in low level signal
With lower cut-off；P-type transistor ends under high level signal effect, is connected under low level signal effect.
It should be noted that the transistor mentioned in the above embodiment of the present invention can be thin film transistor (TFT) (TFT, Thin
Film Transistor), it is also possible to metal oxide semiconductor field effect tube (MOS, Metal Oxide
Scmiconductor), it is not limited thereto.It in specific implementation, can be according to transistor types and received signal not
Together, using the first pole of these transistors as source electrode, the second pole is as drain electrode, alternatively, using the first pole as drain electrode, the second pole is made
For source electrode, specific differentiation is not done herein specifically.
Below by taking structure shown in Fig. 4 as an example, circuit timing diagram as shown in connection with fig. 5, to provided in an embodiment of the present invention
The course of work of above-mentioned shift register cell is described.High level signal is indicated with 1 in described below, and 0 indicates low level
Signal, wherein 1 and 0 represents its logic level, merely to preferably explaining above-mentioned shift LD provided in an embodiment of the present invention
The course of work of device unit, rather than it is applied to the specific voltage value on the grid of each transistor in the specific implementation.
As shown in figure 5, T10 represents the forward scan period, T20 represents the reverse scan period.T11 represents forward scan
Input phase in period, T12 represent the output stage in the forward scan period, and T13 was represented in the forward scan period
Reseting stage.T21 represents the input phase in the reverse scan period, and T22 represents the output rank in the reverse scan period
Section, T23 represent the reseting stage in the reverse scan period.Wherein, in forward scan, first control signal DR1 is height
Level signal, second control signal DR2 are low level signal, and reference signal VREF is low level signal；And in reverse scan
When, first control signal DR1 is low level signal, and second control signal DR2 is high level signal, and reference signal VREF is low electricity
It is illustrated for ordinary mail number.
In forward scan period T10, due to DR1=1, DR2=0, so that the first transistor M1 and third transistor
M3 is constantly on, and the 5th transistor M5 and the 7th transistor M7 end always.Therefore the second input signal INPUT2 and second
Reset signal RE2 is not used in the signal that pull-up node PU is controlled in the T10 period.
In input phase T11, INPUT1=1, CK1=0, RE1=0.
Due to DR1=1, the first transistor M1 and third transistor M3 are both turned on.The third transistor M3 of conducting will
Low level first reset signal RE1 is supplied to the grid of the 4th transistor M4, to control the 4th transistor M4 cut-off.Conducting
First input signal INPUT1 of high level is supplied to second transistor M2 by the first transistor M1, to control second transistor M2
Conducting.The first control signal DR1 of high level is supplied to pull-up node PU by the second transistor M2 of conducting, so that pull-up node
The signal of PU is high level signal, so that control the 9th transistor M9 and the 11st transistor M11 is both turned on.The 9th of conducting is brilliant
Low level reference signal VREF is supplied to pull-down node PD by body pipe M9, so that the signal of pull-down node PD is low level letter
Number, so that control the tenth transistor M10 and the tenth two-transistor M12 is turned off.11st transistor M11 of conducting is by low level
The signal of the first clock signal terminal CK1 be supplied to signal output end OUT, so that signal output end OUT is exported low level signal, with
And storage capacitance CT is made to charge.
In output stage T12, INPUT1=0, CK1=1, RE1=0.
Due to DR1=1, the first transistor M1 and third transistor M3 are both turned on.The third transistor M3 of conducting will
Low level first reset signal RE1 is supplied to the grid of the 4th transistor M4, to control the 4th transistor M4 cut-off.Conducting
Low level first input signal INPUT1 is supplied to second transistor M2 by the first transistor M1, to control second transistor M2
Cut-off.It is high level signal since the effect of storage capacitance CT can keep the signal of pull-up node PU, so as to control the
Nine transistor M9 and the 11st transistor M11 are both turned on.9th transistor M9 of conducting mentions low level reference signal VREF
Pull-down node PD is supplied, so that the signal of pull-down node PD is low level signal, thus control the tenth transistor M10 and the 12nd
Transistor M12 is turned off.The signal of first clock signal terminal CK1 of high level is supplied to by the 11st transistor M11 of conducting
Signal output end OUT makes signal output end OUT export high level signal.Since pull-up node PU is in floating, due to depositing
Storage holds the effect of CT, and the level of pull-up node PU can be made to be further pulled up, so that the 11st transistor M11 of control opens journey
Degree is as complete as possible, and the signal of the first clock signal terminal CK1 of high level is supplied to signal output end OUT, keeps signal defeated
Outlet OUT exports high level signal.
In reseting stage T13, INPUT1=0, CK1=0, RE1=1.
Due to DR1=1, the first transistor M1 and third transistor M3 are both turned on.The first transistor M1 of conducting will
Low level first input signal INPUT1 is supplied to second transistor M2, to control second transistor M2 cut-off.Also, defeated
Stage T12 completion out was transformed into the period of reseting stage T13, due to the effect of storage capacitance CT, can make pull-up node
The signal of PU remains high level signal, is both turned on so as to control the 9th transistor M9 and the 11st transistor M11.Conducting
The 11st transistor M11 the signal of low level first clock signal terminal CK1 is supplied to signal output end OUT, make signal
Output end OUT exports low level signal.Low level reference signal VREF is supplied to drop-down section by the 9th transistor M9 of conducting
Point PD, so that the signal of pull-down node PD is low level signal, thus control the tenth transistor M10 and the tenth two-transistor M12
It is turned off.Also, it is transformed into the period of reseting stage T13 in output stage T12 completion, the first clock signal terminal CK1's
Signal is converted to low level by high level, therefore the both ends coupled capacitor CF are low level signal.Also, due to reseting stage
In T13, the first reset signal RE1 of high level is supplied to the grid of the 4th transistor M4 by the third transistor M3 of conducting, with
Control the 4th transistor M4 conducting.Low level second control signal DR2 is supplied to pull-up section by the 4th transistor M4 of conducting
Point PU, so that the signal of pull-up node PU is low level signal, so as to control the 9th transistor M9 and the 11st transistor
M11 is turned off.
It certainly, can also include resetting holding stage T14 after reseting stage T13.In resetting holding stage T14,
Firstly, INPUT1=0, CK1=1, RE1=0.Due to DR1=1, the first transistor M1 and third transistor M3 are led
It is logical.Low level first input signal INPUT1 is supplied to second transistor M2 by the first transistor M1 of conducting, to control
Two-transistor M2 cut-off.Low level first reset signal RE1 is supplied to the 4th transistor M4 by the third transistor M3 of conducting
Grid, with control the 4th transistor M4 cut-off.Since the signal of the first clock signal terminal CK1 is changed into high level signal, root
According to the effect of coupled capacitor CF, the signal high level signal of pull-down node PD can be made, to control the tenth transistor M10 and the
Ten two-transistor M12 are both turned on.Low level reference signal VREF is supplied to pull-up node by the tenth transistor M10 of conducting
PU, so that the signal of pull-up node PU is low level signal, so as to control the 9th transistor M9 and the 11st transistor M11
It is turned off.Low level reference signal VREF is supplied to signal output end OUT by the tenth two-transistor M12 of conducting, makes signal
Output end OUT exports low level signal.
Later, INPUT1=0, CK1=0, RE1=0.Therefore, the first transistor M1 and third transistor M3 are both turned on.It leads
Low level first input signal INPUT1 is supplied to second transistor M2 by logical the first transistor M1, to control the second crystal
Pipe M2 cut-off.Low level first reset signal RE1 is supplied to the grid of the 4th transistor M4 by the third transistor M3 of conducting,
To control the 4th transistor M4 cut-off.Since the signal of the first clock signal terminal CK1 is changed into low level signal, according to coupling electricity
The effect for holding CF, can make the signal low level signal of pull-down node PD, to control the tenth transistor M10 and the 12nd crystal
Pipe M12 is turned off.Also, due to the effect of storage capacitance CT, can keep signal output end OUT output low level signal and
The signal for keeping pull-up node PU is low level signal, equal so as to control the 9th transistor M9 and the 11st transistor M11
Cut-off.
After the T14 stage, the process in T14 stage is repeated always, until the level of the first input signal becomes again
For high level.
In reverse scan period T20, due to DR1=0, DR2=1, so that the 5th transistor M5 and the 7th transistor
M7 is constantly on, and the first transistor M1 and third transistor M3 end always.Therefore the first input signal INPUT1 and first
Reset signal RE1 is not used in the signal that pull-up node PU is controlled in the T20 period.
In input phase T21, INPUT2=1, CK1=0, RE2=0.
Due to DR2=1, the 5th transistor M5 and the 7th transistor M7 are both turned on.7th transistor M7 of conducting will
Low level second reset signal RE2 is supplied to the grid of the 8th transistor M8, to control the 8th transistor M8 cut-off.Conducting
Second input signal INPUT2 of high level is supplied to the 6th transistor M6 by the 5th transistor M5, to control the 6th transistor M6
Conducting.The second control signal DR2 of high level is supplied to pull-up node PU by the 6th transistor M6 of conducting, so that pull-up node
The signal of PU is high level signal, so that control the 9th transistor M9 and the 11st transistor M11 is both turned on.The 9th of conducting is brilliant
Low level reference signal VREF is supplied to pull-down node PD by body pipe M9, so that the signal of pull-down node PD is low level letter
Number, so that control the tenth transistor M10 and the tenth two-transistor M12 is turned off.11st transistor M11 of conducting is by low level
The signal of the first clock signal terminal CK1 be supplied to signal output end OUT, so that signal output end OUT is exported low level signal, with
And storage capacitance CT is made to charge.
In output stage T22, INPUT2=0, CK1=1, RE2=0.
Due to DR2=1, the 5th transistor M5 and the 7th transistor M7 are both turned on.7th transistor M7 of conducting will
Low level second reset signal RE2 is supplied to the grid of the 8th transistor M8, to control the 8th transistor M8 cut-off.Conducting
Low level second input signal INPUT2 is supplied to the 6th transistor M6 by the 5th transistor M5, to control the 6th transistor M6
Cut-off.It is high level signal since the effect of storage capacitance CT can keep the signal of pull-up node PU, so as to control the
Nine transistor M9 and the 11st transistor M11 are both turned on.9th transistor M9 of conducting mentions low level reference signal VREF
Pull-down node PD is supplied, so that the signal of pull-down node PD is low level signal, thus control the tenth transistor M10 and the 12nd
Transistor M12 is turned off.The signal of first clock signal terminal CK1 of high level is supplied to by the 11st transistor M11 of conducting
Signal output end OUT makes signal output end OUT export high level signal.Since pull-up node PU is in floating, due to depositing
Storage holds the effect of CT, and the level of pull-up node PU can be made to be further pulled up, so that the 11st transistor M11 of control opens journey
Degree is as complete as possible, and the signal of the first clock signal terminal CK1 of high level is supplied to signal output end OUT, keeps signal defeated
Outlet OUT exports high level signal.
In reseting stage T23, INPUT2=0, CK1=0, RE2=1.
Due to DR2=1, the 5th transistor M5 and the 7th transistor M7 are both turned on.5th transistor M5 of conducting will
Low level second input signal INPUT2 is supplied to the 6th transistor M6, to control the 6th transistor M6 cut-off.Also, defeated
Stage T22 completion out was transformed into the period of reseting stage T23, due to the effect of storage capacitance CT, can make pull-up node
The signal of PU remains high level signal, is both turned on so as to control the 9th transistor M9 and the 11st transistor M11.Conducting
The 11st transistor M11 the signal of low level first clock signal terminal CK1 is supplied to signal output end OUT, make signal
Output end OUT exports low level signal.Low level reference signal VREF is supplied to drop-down section by the 9th transistor M9 of conducting
Point PD, so that the signal of pull-down node PD is low level signal, thus control the tenth transistor M10 and the tenth two-transistor M12
It is turned off.Also, it is transformed into the period of reseting stage T23 in output stage T22 completion, the first clock signal terminal CK1's
Signal is converted to low level by high level, therefore the both ends coupled capacitor CF are low level signal.Also, due to reseting stage
In T23, the second reset signal RE2 of high level is supplied to the grid of the 8th transistor M8 by the 7th transistor M7 of conducting, with
Control the 8th transistor M8 conducting.Low level first control signal DR1 is supplied to pull-up section by the 8th transistor M8 of conducting
Point PU, so that the signal of pull-up node PU is low level signal, so as to control the 9th transistor M9 and the 11st transistor
M11 is turned off.
It certainly, can also include resetting holding stage T24 after reseting stage T23.In resetting holding stage T24,
Firstly, INPUT2=0, CK1=1, RE2=0.Due to DR2=1, the 5th transistor M5 and the 7th transistor M7 are led
It is logical.Low level second input signal INPUT2 is supplied to the 6th transistor M6 by the 5th transistor M5 of conducting, to control the
Six transistor M6 cut-off.Low level second reset signal RE2 is supplied to the 8th transistor M8 by the 7th transistor M7 of conducting
Grid, with control the 8th transistor M8 cut-off.Since the signal of the first clock signal terminal CK1 is changed into high level signal, root
According to the effect of coupled capacitor CF, the signal high level signal of pull-down node PD can be made, to control the tenth transistor M10 and the
Ten two-transistor M12 are both turned on.Low level reference signal VREF is supplied to pull-up node by the tenth transistor M10 of conducting
PU, so that the signal of pull-up node PU is low level signal, so as to control the 9th transistor M9 and the 11st transistor M11
It is turned off.Low level reference signal VREF is supplied to signal output end OUT by the tenth two-transistor M12 of conducting, makes signal
Output end OUT exports low level signal.
Later, INPUT2=0, CK1=0, RE2=0.Therefore, the 5th transistor M5 and the 7th transistor M7 are both turned on.It leads
Low level second input signal INPUT2 is supplied to the 6th transistor M6 by the 5th logical transistor M5, to control the 6th crystal
Pipe M6 cut-off.Low level second reset signal RE2 is supplied to the grid of the 8th transistor M8 by the 7th transistor M7 of conducting,
To control the 8th transistor M8 cut-off.Since the signal of the first clock signal terminal CK1 is changed into low level signal, according to coupling electricity
The effect for holding CF, can make the signal low level signal of pull-down node PD, to control the tenth transistor M10 and the 12nd crystal
Pipe M12 is turned off.Also, due to the effect of storage capacitance CT, can keep signal output end OUT output low level signal and
The signal for keeping pull-up node PU is low level signal, equal so as to control the 9th transistor M9 and the 11st transistor M11
Cut-off.
After the T24 stage, the process in T24 stage is repeated always, until the level of the second input signal becomes again
For high level.
Above-mentioned shift register cell provided in an embodiment of the present invention is carrying out forward direction to the display panel in display device
It, can be using just sweeping transistor in input module 10 in input phase T11 for the level of the signal of pull-up node when scanning
Drawn high, using the transistor just swept in reseting module 20 in reseting stage T13 by the level of the signal of pull-up node into
Row is dragged down to reset.It, can be using the anti-transistor swept in input module 30 defeated when carrying out reverse scan to display panel
Enter in stage T21 and draw high the level of the signal of pull-up node, is being resetted using the anti-transistor swept in reseting module 40
The level of the signal of pull-up node is dragged down to reset in stage T23.In this way to display panel carry out forward scan and
It, can be using different signal circulation paths to pull-up node input signal, so as to avoid shift LD when reverse scan
The problem of device unit is switched to the output abnormality occurred when reverse scan by forward scan.
In the specific implementation, the forward scan period can be an at least frame picture display time.For example, can be a frame
Picture display time.Or, or five frame picture display times.Certainly, in practical applications, different application environment is to just
Demand to the duration of sweep time section is different, therefore the specific duration of forward scan period can be according to actual application environment
Determination is designed, is not limited thereto.
In the specific implementation, the reverse scan period can be an at least frame picture display time.For example, can be a frame
Picture display time.Or, or five frame picture display times.Certainly, in practical applications, different application environment is to anti-
Demand to the duration of sweep time section is different, therefore the specific duration of reverse scan period can be according to actual application environment
Determination is designed, is not limited thereto.
It should be noted that due to can be after the completion of the process of forward scan period, then carry out the reverse scan time
The process of section, alternatively, can also be after the completion of the process of reverse scan period, then carry out the process of forward scan period.
Therefore, the succession of forward scan period and reverse scan period can be determined according to actual application environment,
This is not construed as limiting.
Embodiment two,
The structural schematic diagram of the corresponding shift register cell of the present embodiment as shown in fig. 6, its for being moved in embodiment one
The embodiment of bit register unit is deformed.In place of the difference for only illustrating the present embodiment and embodiment one below, phase
With place, therefore not to repeat here.
In the specific implementation, in embodiments of the present invention, as shown in fig. 6, shift register cell can also include: output
Reseting module 60.The output reseting module 60 is configured to respond to the signal of second clock signal end CK2, by reference signal
VREF is supplied to signal output end OUT.It may further ensure that the stability of the signal of signal output end OUT output in this way.
In the specific implementation, in embodiments of the present invention, as shown in fig. 6, output reseting module 60 may include: the 13rd
Transistor M13；Wherein,
The grid and second clock signal end CK2 of 13rd transistor M13 couples, the first pole of the 13rd transistor M13
For receiving reference signal VREF, the second pole of the 13rd transistor M13 and signal output end OUT are coupled.Wherein, the 13rd is brilliant
When body pipe M13 is in the conductive state under the control of second clock signal end CK2, reference signal VREF can be supplied to signal
Output end OUT, the signal exported with control signal output OUT.
In the specific implementation, in embodiments of the present invention, as shown in fig. 7, the signal and second of the first clock signal terminal CK1
The signal of clock signal terminal CK2 is that the period is identical, the clock signal of opposite in phase.
Below by taking structure shown in fig. 6 as an example, circuit timing diagram as shown in connection with fig. 7, to provided in an embodiment of the present invention
The course of work of above-mentioned shift register cell is described.High level signal is indicated with 1 in described below, and 0 indicates low level
Signal, wherein 1 and 0 represents its logic level, merely to preferably explaining above-mentioned shift LD provided in an embodiment of the present invention
The course of work of device unit, rather than it is applied to the specific voltage value on the grid of each transistor in the specific implementation.
As shown in fig. 7, T10 represents the forward scan period, T20 represents the reverse scan period.T11 represents forward scan
Input phase in period, T12 represent the output stage in the forward scan period, and T13 was represented in the forward scan period
Reseting stage, T14 represent the reset in the forward scan period keep the stage.T21 represents defeated in the reverse scan period
Entering the stage, T22 represents the output stage in the reverse scan period, and T23 represents the reseting stage in the reverse scan period,
T14 represents the reset in the reverse scan period and is kept for the stage.
In forward scan period T10, in input phase T11, due to CK2=1, the 13rd transistor M13 is led
Lead to and low level reference signal VREF is supplied to signal output end OUT, signal output end OUT is made to export low level signal.
The course of work of remaining transistor can be identical as the course of work of input phase T11 in embodiment one in the stage, herein not
It repeats.
In output stage T12, since CK2=0, the 13rd transistor M13 end.Remaining transistor in the stage
The course of work can be identical as the course of work of output stage T12 in embodiment one, and therefore not to repeat here.
In reseting stage T13, due to CK2=1, the 13rd transistor M13 conducting and by low level reference signal
VREF is supplied to signal output end OUT, multiple in time so as to be further ensured that signal output end OUT exports low level signal
Position.The course of work of remaining transistor can be identical as the course of work of reseting stage T13 in embodiment one in the stage, herein
It does not repeat.
Resetting holding stage T14, first CK2=0, therefore the 13rd transistor M13 cut-off.CK2=1 later, therefore
13rd transistor M13 is connected and low level reference signal VREF is supplied to signal output end OUT, so as to further
Guarantee that signal output end OUT exports low level signal.In the stage course of work of remaining transistor can in embodiment one
The course of work for resetting holding stage T14 is identical, and therefore not to repeat here.
In reverse scan stage T20, in input phase T21, since CK2=1, the 13rd transistor M13 are connected
And low level reference signal VREF is supplied to signal output end OUT, so that signal output end OUT is exported low level signal.It should
The course of work of remaining transistor can be identical as the course of work of input phase T21 in embodiment one in stage, does not make herein
It repeats.
In output stage T22, since CK2=0, the 13rd transistor M13 end.Remaining transistor in the stage
The course of work can be identical as the course of work of output stage T22 in embodiment one, and therefore not to repeat here.
In reseting stage T23, due to CK2=1, the 13rd transistor M13 conducting and by low level reference signal
VREF is supplied to signal output end OUT, multiple in time so as to be further ensured that signal output end OUT exports low level signal
Position.The course of work of remaining transistor can be identical as the course of work of reseting stage T23 in embodiment one in the stage, herein
It does not repeat.
Resetting holding stage T24, first CK2=0, therefore the 13rd transistor M13 cut-off.CK2=1 later, therefore
13rd transistor M13 is connected and low level reference signal VREF is supplied to signal output end OUT, so as to further
Guarantee that signal output end OUT exports low level signal.In the stage course of work of remaining transistor can in embodiment one
The course of work for resetting holding stage T24 is identical, and therefore not to repeat here.
Embodiment three,
The structural schematic diagram of the corresponding shift register cell of the present embodiment as shown in fig. 6, its for being moved in embodiment two
The embodiment of bit register unit is deformed.In place of the difference for only illustrating the present embodiment and embodiment two below, phase
With place, therefore not to repeat here.
In the specific implementation, in embodiments of the present invention, as shown in figure 8, shift register cell can also include: that frame is multiple
Position module 60.The frame reseting module 60 is configured to respond to frame reseting signal FRE, and reference signal VREF is respectively supplied to
Draw node PU and signal output end OUT coupling.It may further ensure that the signal of pull-up node PU and signal output end OUT in this way
Stablize.
In the specific implementation, in embodiments of the present invention, as shown in figure 8, output reseting module 60 may include: the 14th
Transistor M14 and the 15th transistor M15；Wherein,
The grid of 14th transistor M14 is used for receiving frame reseting signal FRE, the first pole of the 14th transistor M14
In receiving reference signal VREF, the second pole of the 14th transistor M14 and pull-up node PU are coupled；
The grid of 15th transistor M15 is used for receiving frame reseting signal FRE, the first pole of the 15th transistor M15
In receiving reference signal VREF, the second pole of the 15th transistor M15 and signal output end OUT are coupled.
In the specific implementation, in embodiments of the present invention, the 14th transistor M14 is under the control of frame reseting signal FRE
When in the conductive state, reference signal VREF can be supplied to pull-up node PU, to control the signal of pull-up node PU.Tenth
When five transistor M15 are in the conductive state under the control of frame reseting signal FRE, reference signal VREF can be supplied to signal
Output end OUT, the signal exported with control signal output OUT.Further, each frame show picture will at the end of,
14th transistor M14 and the 15th transistor M15 can be connected under the control of frame reseting signal FRE, corresponding to execute
Function.
Below by taking structure shown in Fig. 8 as an example, circuit timing diagram as shown in connection with fig. 9, to provided in an embodiment of the present invention
The course of work of above-mentioned shift register cell is described.High level signal is indicated with 1 in described below, and 0 indicates low level
Signal, wherein 1 and 0 represents its logic level, merely to preferably explaining above-mentioned shift LD provided in an embodiment of the present invention
The course of work of device unit, rather than it is applied to the specific voltage value on the grid of each transistor in the specific implementation.
As shown in figure 9, T10 represents the forward scan period, T20 represents the reverse scan period.F1 generation table forward scan
A frame in period shows that image time, F2 represent the frame in the reverse scan period and show image time.T11 is represented just
Input phase into sweep time section, T12 represents the output stage in the forward scan period, when T13 represents forward scan
Between reseting stage in section, T14 represents the reset in the forward scan period and kept for the stage.T21 represents the reverse scan period
In input phase, T22 represents the output stage in the reverse scan period, and T23 represents the reset in the reverse scan period
Stage, T14 represent the reset in the reverse scan period and are kept for the stage.
Show in image time F1 that shift register cell successively executes T11, T12, T13, T14 stage, later in a frame
A frame show image time F1 will at the end of, due to FRE=1, the 14th transistor M14 and the 15th transistor
M15 is both turned on.Wherein, low level reference signal VREF is supplied to pull-up node PU by the 14th transistor M14 of conducting, with
The signal for being further ensured that pull-up node PU is low level signal.15th transistor M15 of conducting is by low level with reference to letter
Number VREF is supplied to signal output end OUT, so as to be further ensured that signal output end OUT exports low level signal.Also,
In shift register cell remaining transistor the course of work of above-mentioned T11, T12, T13, T14 can be corresponding with embodiment two
The course of work in stage is identical, and therefore not to repeat here.
Show in image time F2 that shift register cell successively executes T21, T22, T23, T24 stage, later in a frame
A frame show image time F2 will at the end of, due to FRE=1, the 14th transistor M14 and the 15th transistor
M15 is both turned on.Wherein, low level reference signal VREF is supplied to pull-up node PU by the 14th transistor M14 of conducting, with
The signal for being further ensured that pull-up node PU is low level signal.15th transistor M15 of conducting is by low level with reference to letter
Number VREF is supplied to signal output end OUT, so as to be further ensured that signal output end OUT exports low level signal.Also,
In shift register cell remaining transistor the course of work of above-mentioned T21, T22, T23, T24 can be corresponding with embodiment two
The course of work in stage is identical, and therefore not to repeat here.
Based on the same inventive concept, the embodiment of the invention also provides a kind of any of the above-described kind provided in an embodiment of the present invention
The driving method of shift register cell may include:
Input phase in forward scan, is just sweeping input module in response to first control signal and the first input signal,
First control signal is supplied to pull-up node；It is multiple in response to first control signal and first just to sweep reseting module for reseting stage
Position signal, is supplied to pull-up node for second control signal；
Input phase in negative sense scanning, anti-input module of sweeping in response to second control signal and the second input signal,
Second control signal is supplied to pull-up node；Reseting stage, anti-reseting module of sweeping are answered in response to second control signal and second
Position signal, is supplied to pull-up node for first control signal.
In the specific implementation, in embodiments of the present invention, after the input phase in forward scan, and in reseting stage
It before, can also include: output stage.In the output stage, output module keeps signal defeated in response to the signal of pull-up node
Outlet output signal.
In the specific implementation, in embodiments of the present invention, after the input phase in reverse scan, and in reseting stage
It before, can also include: output stage.In the output stage, output module keeps signal defeated in response to the signal of pull-up node
Outlet output signal.
In the specific implementation, when shift register cell further includes output reseting module, in embodiments of the present invention, on
Stating input phase can also include: output reseting module in response to the signal of second clock signal end, and reference signal is supplied to
Signal output end.Also, above-mentioned reseting stage can also include: to export reseting module in response to the letter of second clock signal end
Number, reference signal is supplied to signal output end.
In the specific implementation, when shift register cell further includes frame reseting module, in embodiments of the present invention, multiple
It can also include: to reset the holding stage after the stage of position.The holding stage is being resetted, coupled capacitor is according to the first clock signal terminal
Signal controls the signal of pull-down node, and output module makes signal output end output signal in response to the signal of pull-down node.And
Reseting module is exported in response to the signal of second clock signal end, reference signal is supplied to signal output end.
Based on the same inventive concept, the embodiment of the invention also provides a kind of gate driving circuits, as shown in Figure 10, can be with
It include: the cascade 1st to N shift register cell SR (1)~SR (N)；Wherein, N is positive integer, each shift register cell
For any of the above-described kind of shift register cell provided in an embodiment of the present invention.Specifically, N is shift LD in gate driving circuit
The value of the sum of device unit, N can design determination according to actual application environment, be not limited thereto.Below using N as even number
For be illustrated.
Specifically, the first input signal INPUT1 of the 1st grade of shift register cell SR (1) just sweeps trigger signal by first
STP1 is provided；First input signal INPUT1 of the 2nd grade of shift register cell SR (2) is just sweeping trigger signal STP2 by second and is mentioning
For；Also, the first input signal INPUT1 of n-th grade of shift register cell SR (n) is by the n-th -2 grades shift register cell SR
(n-2) signal output end OUT is provided；The first reset signal RE1 of n-th grade of shift register cell SR (n) is moved by the n-th+2 grades
The signal output end OUT of bit register cell S R (n+2) is provided；Referring specifically to solid line coupling part in Figure 10.
Second input signal INPUT2 of N grades of shift register cell SR (N) is mentioned by the first anti-trigger signal STN1 that sweeps
For；Second input signal INPUT2 of N-1 grades of shift register cell SR (N-1) is mentioned by the second anti-trigger signal STN2 that sweeps
For；Also, the second input signal INPUT2 of n-th grade of shift register cell SR (n) is by the n-th+2 grades shift register cell SR
(n+2) signal output end OUT is provided；The second reset signal RE2 of n-th grade of shift register cell SR (n) is moved by the n-th -2 grades
The signal output end OUTOUT of bit register cell S R (n-2) is provided.Referring specifically to dotted line coupling part in Figure 10.
In the specific implementation, in embodiments of the present invention, as shown in Figure 10, the the 1st to N shift register cell SR (1)
The first control signal DR1 of~SR (N) can be provided by same control terminal dr1, the 1st to N shift register cell SR (1)~
The second control signal DR2 of SR (N) can be provided by same control terminal dr2.Also, odd number shift register cell SR
(1), the signal of the first clock signal terminal CK1 of (3) SR ... SR (N-3) and SR (N-1) is mentioned by same clock end ck1_1
For the first clock signal terminal CK1's of even number shift register cell SR (2), SR (4) ... SR (N-2) and SR (N)
Signal is provided by same clock end ck1_2.
In the specific implementation, when shift register cell further includes output reseting module, in embodiments of the present invention, such as
Shown in Figure 11, the second clock of odd number shift register cell SR (1), SR (3) ... SR (N-3) and SR (N-1) are believed
Number end CK2 signal provided by same clock end ck2_1, even number shift register cell SR (2), SR (4) ... SR (N-
2) and the signal of the second clock signal end CK2 of SR (N) is provided by same clock end ck2_2.
In the specific implementation, when shift register cell further includes frame reseting module, in embodiments of the present invention, such as scheme
Shown in 12, the frame reseting signal FRE of the 1st to N shift register cell SR (1)~SR (N) can be by same frame reset terminal fre
It provides.Entire gate driving circuit can be resetted at the end of a frame shows image time soon in this way.Further
Blanking time (Blanking time) can be also arranged in ground, a frame picture display time, therefore, can be by frame reseting signal FRE's
Effective impulse signal (FRE signal as shown in Figure 9) is arranged in Blanking time.
Also, the specific structure of each shift register in above-mentioned gate driving circuit and the above-mentioned shift LD of the present invention
Device is all the same in function and structure, and overlaps will not be repeated.
Based on the same inventive concept, the embodiment of the invention also provides a kind of display devices, including the embodiment of the present invention to mention
The above-mentioned gate driving circuit supplied.The principle that the display device solves the problems, such as is similar to aforementioned shift register, therefore the display
The implementation of device may refer to the implementation of aforementioned shift register, and repeating place, details are not described herein.
In the specific implementation, above-mentioned display device provided in an embodiment of the present invention can be that organic light-emitting display device can also
Think liquid crystal display device, is not limited thereto.
In the specific implementation, above-mentioned display device provided in an embodiment of the present invention can be comprehensive screen display device, or
Or flexible display apparatus etc., it is not limited thereto.
It in the specific implementation, may include a plurality of grid line and a gate driving circuit in the display panel of display device.
The signal output end of each of gate driving circuit shift register cell connects one to one a grid line.
It in the specific implementation, may include a plurality of grid line and two gate driving circuits in the display panel of display device.
The signal output end of each of one of gate driving circuit shift register cell connects one to one a grid line,
The signal output end of each of another gate driving circuit shift register cell also connects one to one a grid line.
Also, the signal for connecting the shift register cell output of same grid line is identical.
It in the specific implementation, may include a plurality of grid line and two gate driving circuits in the display panel of display device.
Wherein, first gate driving circuit in the two gate driving circuits corresponds to the grid line of odd-numbered line, second gate driving
Circuit corresponds to the grid line of even number line.Specifically, the signal of each of first gate driving circuit shift register cell
Output end connects one to one the grid line of an odd-numbered line, each of second gate driving circuit shift register cell
Signal output end connect one to one the grid line of an even number line.
In the specific implementation, above-mentioned display device provided in an embodiment of the present invention can shield comprehensively as shown in fig. 13 that
Mobile phone.Certainly, above-mentioned display device provided in an embodiment of the present invention may be tablet computer, television set, display, notebook
Any products or components having a display function such as computer, Digital Frame, navigator.Other for the display device must can not
Few component part is it will be apparent to an ordinarily skilled person in the art that having, and this will not be repeated here, also be should not be used as pair
Limitation of the invention.
Shift register cell, its driving method, gate driving circuit and display device provided in an embodiment of the present invention,
It, can be using just sweeping input module to pull-up node input signal, using just sweeping reset when carrying out forward scan to display panel
Module resets pull-up node, and by the collective effect of output module and coupled capacitor, output end can be made to export
Signal.It, can be using anti-input module of sweeping to pull-up node input signal, using anti-when carrying out reverse scan to display panel
It sweeps reseting module to reset pull-up node, and by the collective effect of output module and coupled capacitor, can make to export
Hold output signal.Display panel is being carried out that different input modules is respectively adopted when forward scan and reverse scan and answered in this way
Position module, different signal circulation paths can be used when pulling up node input signal, so as to avoid displacement from posting
The problem of storage unit is switched to the output abnormality occurred when reverse scan by forward scan.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (15)
1. a kind of shift register cell characterized by comprising just sweeping input module, just sweeping reseting module, counter sweeping input mould
Block counter sweeps reseting module, output module and coupled capacitor；Wherein, when the coupled capacitor is connected to pull-down node with first
Between clock signal end；
The input module of just sweeping is configured to respond to first control signal and the first input signal, and first control is believed
Number it is supplied to pull-up node；
The reseting module of just sweeping is configured to respond to the first control signal and the first reset signal, and the second control is believed
Number it is supplied to the pull-up node；
The anti-input module of sweeping is configured to respond to the second control signal and the second input signal, and described second is controlled
Signal processed is supplied to the pull-up node；
The anti-reseting module of sweeping is configured to respond to the second control signal and the second reset signal, and described first is controlled
Signal processed is supplied to the pull-up node；
The output module is configured to respond to the signal of the pull-up node and the pull-down node, keeps signal output end defeated
Signal out.
2. shift register cell as described in claim 1, which is characterized in that the input module of just sweeping includes: the first crystalline substance
Body pipe and second transistor；
The grid of the first transistor is for receiving the first control signal, and the first pole of the first transistor is for connecing
First input signal is received, the second pole of the first transistor and the grid of the second transistor couple；
First pole of the second transistor is for receiving the first control signal, the second pole of the second transistor and institute
State pull-up node coupling.
3. shift register cell as described in claim 1, which is characterized in that the reseting module of just sweeping includes: third crystalline substance
Tetra- transistor of body Guan Yu；
The grid of the third transistor is for receiving the first control signal, and the first pole of the third transistor is for connecing
Receive first reset signal, the grid coupling of the second pole of the third transistor and the 4th transistor；
First pole of the 4th transistor is for receiving the second control signal, the second pole of the 4th transistor and institute
State pull-up node coupling.
4. shift register cell as described in claim 1, which is characterized in that the anti-input module of sweeping includes: the 5th crystalline substance
Six transistor of body Guan Yu；
The grid of 5th transistor is for receiving the second control signal, and the first pole of the 5th transistor is for connecing
Second input signal is received, the second pole of the 5th transistor and the grid of the 6th transistor couple；
First pole of the 6th transistor is for receiving the second control signal, the second pole of the 6th transistor and institute
State pull-up node coupling.
5. shift register cell as described in claim 1, which is characterized in that the anti-reseting module of sweeping includes: the 7th crystalline substance
Eight transistor of body Guan Yu；
The grid of 7th transistor is for receiving the second control signal, and the first pole of the 7th transistor is for connecing
Second reset signal is received, the second pole of the 7th transistor and the grid of the 8th transistor couple；
First pole of the 8th transistor is for receiving the first control signal, the second pole of the 8th transistor and institute
State pull-up node coupling.
6. shift register cell as described in claim 1, which is characterized in that the output module includes: output control
Module and signal output sub-module；
The output control submodule is configured to respond to the signal of the pull-up node, and the reference signal is supplied to institute
Pull-down node is stated, and in response to the signal of the pull-down node, the reference signal is supplied to the pull-up node；
The signal output sub-module provides the signal of first clock signal terminal in response to the signal of the pull-up node
To the signal output end, and in response to the signal of the pull-down node, it is defeated that the reference signal is supplied to the signal
Outlet.
7. shift register cell as claimed in claim 6, which is characterized in that the output control submodule includes: the 9th
Transistor and the tenth transistor；
The grid of 9th transistor and the pull-up node couple, and the first pole of the 9th transistor is described for receiving
Reference signal, the second pole of the 9th transistor and the pull-down node couple；
The grid of tenth transistor and the pull-down node couple, and the first pole of the tenth transistor is described for receiving
Reference signal, the second pole of the tenth transistor and the pull-up node couple.
8. shift register cell as claimed in claim 6, which is characterized in that the signal output sub-module includes: the tenth
One transistor, the tenth two-transistor and storage capacitance；
The grid of 11st transistor and the pull-up node couple, the first pole of the 11st transistor and described the
The coupling of one clock signal terminal, the second pole of the 11st transistor and the signal output end couple；
The grid of tenth two-transistor and the pull-down node couple, and the first pole of the tenth two-transistor is for receiving
The reference signal, the second pole of the tenth two-transistor and the signal output end couple；
The storage capacitance is connected between the pull-up node and the signal output end.
9. such as the described in any item shift register cells of claim 1-8, which is characterized in that the shift register cell is also
Include: output reseting module, be configured to respond to the signal of second clock signal end, reference signal is supplied to the signal
Output end.
10. shift register cell as claimed in claim 9, which is characterized in that the output reseting module includes: the 13rd
Transistor；
The grid and the second clock signal end of 13rd transistor couple, and the first pole of the 13rd transistor is used
In receiving the reference signal, the second pole of the 13rd transistor and the signal output end are coupled.
11. such as the described in any item shift register cells of claim 1-8, which is characterized in that the shift register cell
Further include: frame reseting module is configured to respond to frame reseting signal, by reference signal be respectively supplied to the pull-up node and
The signal output end coupling.
12. shift register cell as claimed in claim 11, which is characterized in that the output reseting module includes: the tenth
Four transistors and the 15th transistor；
For receiving the frame reseting signal, the first pole of the 14th transistor is used for the grid of 14th transistor
The reference signal is received, the second pole of the 14th transistor and the pull-up node couple；
For receiving the frame reseting signal, the first pole of the 15th transistor is used for the grid of 15th transistor
The reference signal is received, the second pole of the 15th transistor and the signal output end couple.
13. a kind of driving method of such as described in any item shift register cells of claim 1-12, which is characterized in that packet
It includes:
Input phase in forward scan, the input module of just sweeping in response to first control signal and the first input signal,
The first control signal is supplied to pull-up node；Reseting stage, the reseting module of just sweeping is in response to first control
Second control signal is supplied to the pull-up node by signal and the first reset signal；
Input phase in negative sense scanning, the anti-input module of sweeping is in response to the second control signal and described second defeated
Enter signal, the second control signal is supplied to the pull-up node；Reseting stage, the anti-reseting module of sweeping is in response to institute
Second control signal and second reset signal are stated, the first control signal is supplied to the pull-up node.
14. a kind of gate driving circuit characterized by comprising the cascade 1st to N shift register cell；Wherein, N is
Positive integer, each shift register cell are such as the described in any item shift register cells of claim 1-12；
First input signal of the 1st grade of shift register cell is just being swept trigger signal by first and is being provided；2nd grade of shift register list
First input signal of member is just being swept trigger signal by second and is being provided；Also, the first input signal of n-th grade of shift register cell
It is provided by the signal output end of the n-th -2 grades shift register cells；First reset signal of n-th grade of shift register cell is by
The signal output end of n+2 grades of shift register cells provides；
Second input signal of N grades of shift register cells is provided by the first anti-trigger signal of sweeping；N-1 grades of shift registers
Second input signal of unit is provided by the second anti-trigger signal of sweeping；Also, the second input letter of n-th grade of shift register cell
It number is provided by the signal output end of the n-th+2 grades shift register cells；Second reset signal of n-th grade of shift register cell by
The signal output end of the n-th -2 grades shift register cells provides.
15. a kind of display transposition, which is characterized in that including gate driving circuit as claimed in claim 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811610074.1A CN109377934A (en) | 2018-12-27 | 2018-12-27 | Shift register cell, its driving method, gate driving circuit and display device |
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|---|---|---|---|
| CN201811610074.1A CN109377934A (en) | 2018-12-27 | 2018-12-27 | Shift register cell, its driving method, gate driving circuit and display device |
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Application publication date: 20190222 |